irq-renesas-h8s.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * H8S interrupt controller driver
  4. *
  5. * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
  6. */
  7. #include <linux/irq.h>
  8. #include <linux/irqchip.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_irq.h>
  11. #include <asm/io.h>
  12. static void *intc_baseaddr;
  13. #define IPRA (intc_baseaddr)
  14. static const unsigned char ipr_table[] = {
  15. 0x03, 0x02, 0x01, 0x00, 0x13, 0x12, 0x11, 0x10, /* 16 - 23 */
  16. 0x23, 0x22, 0x21, 0x20, 0x33, 0x32, 0x31, 0x30, /* 24 - 31 */
  17. 0x43, 0x42, 0x41, 0x40, 0x53, 0x53, 0x52, 0x52, /* 32 - 39 */
  18. 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, /* 40 - 47 */
  19. 0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */
  20. 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, /* 56 - 63 */
  21. 0x61, 0x61, 0x61, 0x61, 0x60, 0x60, 0x60, 0x60, /* 64 - 71 */
  22. 0x73, 0x73, 0x73, 0x73, 0x72, 0x72, 0x72, 0x72, /* 72 - 79 */
  23. 0x71, 0x71, 0x71, 0x71, 0x70, 0x83, 0x82, 0x81, /* 80 - 87 */
  24. 0x80, 0x80, 0x80, 0x80, 0x93, 0x93, 0x93, 0x93, /* 88 - 95 */
  25. 0x92, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x91, /* 96 - 103 */
  26. 0x90, 0x90, 0x90, 0x90, 0xa3, 0xa3, 0xa3, 0xa3, /* 104 - 111 */
  27. 0xa2, 0xa2, 0xa2, 0xa2, 0xa1, 0xa1, 0xa1, 0xa1, /* 112 - 119 */
  28. 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, /* 120 - 127 */
  29. };
  30. static void h8s_disable_irq(struct irq_data *data)
  31. {
  32. int pos;
  33. void __iomem *addr;
  34. unsigned short pri;
  35. int irq = data->irq;
  36. addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
  37. pos = (ipr_table[irq - 16] & 0x0f) * 4;
  38. pri = ~(0x000f << pos);
  39. pri &= readw(addr);
  40. writew(pri, addr);
  41. }
  42. static void h8s_enable_irq(struct irq_data *data)
  43. {
  44. int pos;
  45. void __iomem *addr;
  46. unsigned short pri;
  47. int irq = data->irq;
  48. addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
  49. pos = (ipr_table[irq - 16] & 0x0f) * 4;
  50. pri = ~(0x000f << pos);
  51. pri &= readw(addr);
  52. pri |= 1 << pos;
  53. writew(pri, addr);
  54. }
  55. struct irq_chip h8s_irq_chip = {
  56. .name = "H8S-INTC",
  57. .irq_enable = h8s_enable_irq,
  58. .irq_disable = h8s_disable_irq,
  59. };
  60. static __init int irq_map(struct irq_domain *h, unsigned int virq,
  61. irq_hw_number_t hw_irq_num)
  62. {
  63. irq_set_chip_and_handler(virq, &h8s_irq_chip, handle_simple_irq);
  64. return 0;
  65. }
  66. static const struct irq_domain_ops irq_ops = {
  67. .map = irq_map,
  68. .xlate = irq_domain_xlate_onecell,
  69. };
  70. static int __init h8s_intc_of_init(struct device_node *intc,
  71. struct device_node *parent)
  72. {
  73. struct irq_domain *domain;
  74. int n;
  75. intc_baseaddr = of_iomap(intc, 0);
  76. BUG_ON(!intc_baseaddr);
  77. /* All interrupt priority is 0 (disable) */
  78. /* IPRA to IPRK */
  79. for (n = 0; n <= 'k' - 'a'; n++)
  80. writew(0x0000, IPRA + (n * 2));
  81. domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
  82. BUG_ON(!domain);
  83. irq_set_default_host(domain);
  84. return 0;
  85. }
  86. IRQCHIP_DECLARE(h8s_intc, "renesas,h8s-intc", h8s_intc_of_init);