irq-ompic.c 5.5 KB

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  1. /*
  2. * Open Multi-Processor Interrupt Controller driver
  3. *
  4. * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
  5. * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public License
  8. * version 2. This program is licensed "as is" without any warranty of any
  9. * kind, whether express or implied.
  10. *
  11. * The ompic device handles IPI communication between cores in multi-core
  12. * OpenRISC systems.
  13. *
  14. * Registers
  15. *
  16. * For each CPU the ompic has 2 registers. The control register for sending
  17. * and acking IPIs and the status register for receiving IPIs. The register
  18. * layouts are as follows:
  19. *
  20. * Control register
  21. * +---------+---------+----------+---------+
  22. * | 31 | 30 | 29 .. 16 | 15 .. 0 |
  23. * ----------+---------+----------+----------
  24. * | IRQ ACK | IRQ GEN | DST CORE | DATA |
  25. * +---------+---------+----------+---------+
  26. *
  27. * Status register
  28. * +----------+-------------+----------+---------+
  29. * | 31 | 30 | 29 .. 16 | 15 .. 0 |
  30. * -----------+-------------+----------+---------+
  31. * | Reserved | IRQ Pending | SRC CORE | DATA |
  32. * +----------+-------------+----------+---------+
  33. *
  34. * Architecture
  35. *
  36. * - The ompic generates a level interrupt to the CPU PIC when a message is
  37. * ready. Messages are delivered via the memory bus.
  38. * - The ompic does not have any interrupt input lines.
  39. * - The ompic is wired to the same irq line on each core.
  40. * - Devices are wired to the same irq line on each core.
  41. *
  42. * +---------+ +---------+
  43. * | CPU | | CPU |
  44. * | Core 0 |<==\ (memory access) /==>| Core 1 |
  45. * | [ PIC ]| | | | [ PIC ]|
  46. * +----^-^--+ | | +----^-^--+
  47. * | | v v | |
  48. * <====|=|=================================|=|==> (memory bus)
  49. * | | ^ ^ | |
  50. * (ipi | +------|---------+--------|-------|-+ (device irq)
  51. * irq | | | | |
  52. * core0)| +------|---------|--------|-------+ (ipi irq core1)
  53. * | | | | |
  54. * +----o-o-+ | +--------+ |
  55. * | ompic |<===/ | Device |<===/
  56. * | IPI | +--------+
  57. * +--------+*
  58. *
  59. */
  60. #include <linux/io.h>
  61. #include <linux/ioport.h>
  62. #include <linux/interrupt.h>
  63. #include <linux/smp.h>
  64. #include <linux/of.h>
  65. #include <linux/of_irq.h>
  66. #include <linux/of_address.h>
  67. #include <linux/irqchip.h>
  68. #define OMPIC_CPUBYTES 8
  69. #define OMPIC_CTRL(cpu) (0x0 + (cpu * OMPIC_CPUBYTES))
  70. #define OMPIC_STAT(cpu) (0x4 + (cpu * OMPIC_CPUBYTES))
  71. #define OMPIC_CTRL_IRQ_ACK (1 << 31)
  72. #define OMPIC_CTRL_IRQ_GEN (1 << 30)
  73. #define OMPIC_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
  74. #define OMPIC_STAT_IRQ_PENDING (1 << 30)
  75. #define OMPIC_DATA(x) ((x) & 0xffff)
  76. DEFINE_PER_CPU(unsigned long, ops);
  77. static void __iomem *ompic_base;
  78. static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
  79. {
  80. return ioread32be(base + offset);
  81. }
  82. static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
  83. {
  84. iowrite32be(data, base + offset);
  85. }
  86. static void ompic_raise_softirq(const struct cpumask *mask,
  87. unsigned int ipi_msg)
  88. {
  89. unsigned int dst_cpu;
  90. unsigned int src_cpu = smp_processor_id();
  91. for_each_cpu(dst_cpu, mask) {
  92. set_bit(ipi_msg, &per_cpu(ops, dst_cpu));
  93. /*
  94. * On OpenRISC the atomic set_bit() call implies a memory
  95. * barrier. Otherwise we would need: smp_wmb(); paired
  96. * with the read in ompic_ipi_handler.
  97. */
  98. ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu),
  99. OMPIC_CTRL_IRQ_GEN |
  100. OMPIC_CTRL_DST(dst_cpu) |
  101. OMPIC_DATA(1));
  102. }
  103. }
  104. static irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
  105. {
  106. unsigned int cpu = smp_processor_id();
  107. unsigned long *pending_ops = &per_cpu(ops, cpu);
  108. unsigned long ops;
  109. ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK);
  110. while ((ops = xchg(pending_ops, 0)) != 0) {
  111. /*
  112. * On OpenRISC the atomic xchg() call implies a memory
  113. * barrier. Otherwise we may need an smp_rmb(); paired
  114. * with the write in ompic_raise_softirq.
  115. */
  116. do {
  117. unsigned long ipi_msg;
  118. ipi_msg = __ffs(ops);
  119. ops &= ~(1UL << ipi_msg);
  120. handle_IPI(ipi_msg);
  121. } while (ops);
  122. }
  123. return IRQ_HANDLED;
  124. }
  125. static int __init ompic_of_init(struct device_node *node,
  126. struct device_node *parent)
  127. {
  128. struct resource res;
  129. int irq;
  130. int ret;
  131. /* Validate the DT */
  132. if (ompic_base) {
  133. pr_err("ompic: duplicate ompic's are not supported");
  134. return -EEXIST;
  135. }
  136. if (of_address_to_resource(node, 0, &res)) {
  137. pr_err("ompic: reg property requires an address and size");
  138. return -EINVAL;
  139. }
  140. if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) {
  141. pr_err("ompic: reg size, currently %d must be at least %d",
  142. resource_size(&res),
  143. (num_possible_cpus() * OMPIC_CPUBYTES));
  144. return -EINVAL;
  145. }
  146. /* Setup the device */
  147. ompic_base = ioremap(res.start, resource_size(&res));
  148. if (!ompic_base) {
  149. pr_err("ompic: unable to map registers");
  150. return -ENOMEM;
  151. }
  152. irq = irq_of_parse_and_map(node, 0);
  153. if (irq <= 0) {
  154. pr_err("ompic: unable to parse device irq");
  155. ret = -EINVAL;
  156. goto out_unmap;
  157. }
  158. ret = request_irq(irq, ompic_ipi_handler, IRQF_PERCPU,
  159. "ompic_ipi", NULL);
  160. if (ret)
  161. goto out_irq_disp;
  162. set_smp_cross_call(ompic_raise_softirq);
  163. return 0;
  164. out_irq_disp:
  165. irq_dispose_mapping(irq);
  166. out_unmap:
  167. iounmap(ompic_base);
  168. ompic_base = NULL;
  169. return ret;
  170. }
  171. IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);