irq-nvic.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/irq/irq-nvic.c
  4. *
  5. * Copyright (C) 2008 ARM Limited, All Rights Reserved.
  6. * Copyright (C) 2013 Pengutronix
  7. *
  8. * Support for the Nested Vectored Interrupt Controller found on the
  9. * ARMv7-M CPUs (Cortex-M3/M4)
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/slab.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/irq.h>
  20. #include <linux/irqchip.h>
  21. #include <linux/irqdomain.h>
  22. #include <asm/v7m.h>
  23. #include <asm/exception.h>
  24. #define NVIC_ISER 0x000
  25. #define NVIC_ICER 0x080
  26. #define NVIC_IPR 0x400
  27. #define NVIC_MAX_BANKS 16
  28. /*
  29. * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
  30. * 16 irqs.
  31. */
  32. #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
  33. static struct irq_domain *nvic_irq_domain;
  34. asmlinkage void __exception_irq_entry
  35. nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
  36. {
  37. unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq);
  38. handle_IRQ(irq, regs);
  39. }
  40. static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  41. unsigned int nr_irqs, void *arg)
  42. {
  43. int i, ret;
  44. irq_hw_number_t hwirq;
  45. unsigned int type = IRQ_TYPE_NONE;
  46. struct irq_fwspec *fwspec = arg;
  47. ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
  48. if (ret)
  49. return ret;
  50. for (i = 0; i < nr_irqs; i++)
  51. irq_map_generic_chip(domain, virq + i, hwirq + i);
  52. return 0;
  53. }
  54. static const struct irq_domain_ops nvic_irq_domain_ops = {
  55. .translate = irq_domain_translate_onecell,
  56. .alloc = nvic_irq_domain_alloc,
  57. .free = irq_domain_free_irqs_top,
  58. };
  59. static int __init nvic_of_init(struct device_node *node,
  60. struct device_node *parent)
  61. {
  62. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  63. unsigned int irqs, i, ret, numbanks;
  64. void __iomem *nvic_base;
  65. numbanks = (readl_relaxed(V7M_SCS_ICTR) &
  66. V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
  67. nvic_base = of_iomap(node, 0);
  68. if (!nvic_base) {
  69. pr_warn("unable to map nvic registers\n");
  70. return -ENOMEM;
  71. }
  72. irqs = numbanks * 32;
  73. if (irqs > NVIC_MAX_IRQ)
  74. irqs = NVIC_MAX_IRQ;
  75. nvic_irq_domain =
  76. irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
  77. if (!nvic_irq_domain) {
  78. pr_warn("Failed to allocate irq domain\n");
  79. iounmap(nvic_base);
  80. return -ENOMEM;
  81. }
  82. ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
  83. "nvic_irq", handle_fasteoi_irq,
  84. clr, 0, IRQ_GC_INIT_MASK_CACHE);
  85. if (ret) {
  86. pr_warn("Failed to allocate irq chips\n");
  87. irq_domain_remove(nvic_irq_domain);
  88. iounmap(nvic_base);
  89. return ret;
  90. }
  91. for (i = 0; i < numbanks; ++i) {
  92. struct irq_chip_generic *gc;
  93. gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
  94. gc->reg_base = nvic_base + 4 * i;
  95. gc->chip_types[0].regs.enable = NVIC_ISER;
  96. gc->chip_types[0].regs.disable = NVIC_ICER;
  97. gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
  98. gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
  99. /* This is a no-op as end of interrupt is signaled by the
  100. * exception return sequence.
  101. */
  102. gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
  103. /* disable interrupts */
  104. writel_relaxed(~0, gc->reg_base + NVIC_ICER);
  105. }
  106. /* Set priority on all interrupts */
  107. for (i = 0; i < irqs; i += 4)
  108. writel_relaxed(0, nvic_base + NVIC_IPR + i);
  109. return 0;
  110. }
  111. IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);