irq-mxs.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  4. * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
  5. * Add Alphascale ASM9260 support.
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/init.h>
  9. #include <linux/irq.h>
  10. #include <linux/irqchip.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/io.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/stmp_device.h>
  17. #include <asm/exception.h>
  18. #include "alphascale_asm9260-icoll.h"
  19. /*
  20. * this device provide 4 offsets for each register:
  21. * 0x0 - plain read write mode
  22. * 0x4 - set mode, OR logic.
  23. * 0x8 - clr mode, XOR logic.
  24. * 0xc - togle mode.
  25. */
  26. #define SET_REG 4
  27. #define CLR_REG 8
  28. #define HW_ICOLL_VECTOR 0x0000
  29. #define HW_ICOLL_LEVELACK 0x0010
  30. #define HW_ICOLL_CTRL 0x0020
  31. #define HW_ICOLL_STAT_OFFSET 0x0070
  32. #define HW_ICOLL_INTERRUPT0 0x0120
  33. #define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10)
  34. #define BM_ICOLL_INTR_ENABLE BIT(2)
  35. #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
  36. #define ICOLL_NUM_IRQS 128
  37. enum icoll_type {
  38. ICOLL,
  39. ASM9260_ICOLL,
  40. };
  41. struct icoll_priv {
  42. void __iomem *vector;
  43. void __iomem *levelack;
  44. void __iomem *ctrl;
  45. void __iomem *stat;
  46. void __iomem *intr;
  47. void __iomem *clear;
  48. enum icoll_type type;
  49. };
  50. static struct icoll_priv icoll_priv;
  51. static struct irq_domain *icoll_domain;
  52. /* calculate bit offset depending on number of intterupt per register */
  53. static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
  54. {
  55. /*
  56. * mask lower part of hwirq to convert it
  57. * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
  58. */
  59. return bit << ((d->hwirq & 3) << 3);
  60. }
  61. /* calculate mem offset depending on number of intterupt per register */
  62. static void __iomem *icoll_intr_reg(struct irq_data *d)
  63. {
  64. /* offset = hwirq / intr_per_reg * 0x10 */
  65. return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
  66. }
  67. static void icoll_ack_irq(struct irq_data *d)
  68. {
  69. /*
  70. * The Interrupt Collector is able to prioritize irqs.
  71. * Currently only level 0 is used. So acking can use
  72. * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
  73. */
  74. __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
  75. icoll_priv.levelack);
  76. }
  77. static void icoll_mask_irq(struct irq_data *d)
  78. {
  79. __raw_writel(BM_ICOLL_INTR_ENABLE,
  80. icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
  81. }
  82. static void icoll_unmask_irq(struct irq_data *d)
  83. {
  84. __raw_writel(BM_ICOLL_INTR_ENABLE,
  85. icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
  86. }
  87. static void asm9260_mask_irq(struct irq_data *d)
  88. {
  89. __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
  90. icoll_intr_reg(d) + CLR_REG);
  91. }
  92. static void asm9260_unmask_irq(struct irq_data *d)
  93. {
  94. __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
  95. icoll_priv.clear +
  96. ASM9260_HW_ICOLL_CLEARn(d->hwirq));
  97. __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
  98. icoll_intr_reg(d) + SET_REG);
  99. }
  100. static struct irq_chip mxs_icoll_chip = {
  101. .irq_ack = icoll_ack_irq,
  102. .irq_mask = icoll_mask_irq,
  103. .irq_unmask = icoll_unmask_irq,
  104. .flags = IRQCHIP_MASK_ON_SUSPEND |
  105. IRQCHIP_SKIP_SET_WAKE,
  106. };
  107. static struct irq_chip asm9260_icoll_chip = {
  108. .irq_ack = icoll_ack_irq,
  109. .irq_mask = asm9260_mask_irq,
  110. .irq_unmask = asm9260_unmask_irq,
  111. .flags = IRQCHIP_MASK_ON_SUSPEND |
  112. IRQCHIP_SKIP_SET_WAKE,
  113. };
  114. asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
  115. {
  116. u32 irqnr;
  117. irqnr = __raw_readl(icoll_priv.stat);
  118. __raw_writel(irqnr, icoll_priv.vector);
  119. handle_domain_irq(icoll_domain, irqnr, regs);
  120. }
  121. static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
  122. irq_hw_number_t hw)
  123. {
  124. struct irq_chip *chip;
  125. if (icoll_priv.type == ICOLL)
  126. chip = &mxs_icoll_chip;
  127. else
  128. chip = &asm9260_icoll_chip;
  129. irq_set_chip_and_handler(virq, chip, handle_level_irq);
  130. return 0;
  131. }
  132. static const struct irq_domain_ops icoll_irq_domain_ops = {
  133. .map = icoll_irq_domain_map,
  134. .xlate = irq_domain_xlate_onecell,
  135. };
  136. static void __init icoll_add_domain(struct device_node *np,
  137. int num)
  138. {
  139. icoll_domain = irq_domain_add_linear(np, num,
  140. &icoll_irq_domain_ops, NULL);
  141. if (!icoll_domain)
  142. panic("%pOF: unable to create irq domain", np);
  143. }
  144. static void __iomem * __init icoll_init_iobase(struct device_node *np)
  145. {
  146. void __iomem *icoll_base;
  147. icoll_base = of_io_request_and_map(np, 0, np->name);
  148. if (IS_ERR(icoll_base))
  149. panic("%pOF: unable to map resource", np);
  150. return icoll_base;
  151. }
  152. static int __init icoll_of_init(struct device_node *np,
  153. struct device_node *interrupt_parent)
  154. {
  155. void __iomem *icoll_base;
  156. icoll_priv.type = ICOLL;
  157. icoll_base = icoll_init_iobase(np);
  158. icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR;
  159. icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK;
  160. icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL;
  161. icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET;
  162. icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0;
  163. icoll_priv.clear = NULL;
  164. /*
  165. * Interrupt Collector reset, which initializes the priority
  166. * for each irq to level 0.
  167. */
  168. stmp_reset_block(icoll_priv.ctrl);
  169. icoll_add_domain(np, ICOLL_NUM_IRQS);
  170. return 0;
  171. }
  172. IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
  173. static int __init asm9260_of_init(struct device_node *np,
  174. struct device_node *interrupt_parent)
  175. {
  176. void __iomem *icoll_base;
  177. int i;
  178. icoll_priv.type = ASM9260_ICOLL;
  179. icoll_base = icoll_init_iobase(np);
  180. icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR;
  181. icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK;
  182. icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL;
  183. icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
  184. icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
  185. icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0;
  186. writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
  187. icoll_priv.ctrl);
  188. /*
  189. * ASM9260 don't provide reset bit. So, we need to set level 0
  190. * manually.
  191. */
  192. for (i = 0; i < 16 * 0x10; i += 0x10)
  193. writel(0, icoll_priv.intr + i);
  194. icoll_add_domain(np, ASM9260_NUM_IRQS);
  195. set_handle_irq(icoll_handle_irq);
  196. return 0;
  197. }
  198. IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);