irq-mvebu-pic.c 4.8 KB

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  1. /*
  2. * Copyright (C) 2016 Marvell
  3. *
  4. * Yehuda Yitschak <yehuday@marvell.com>
  5. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/irqchip.h>
  15. #include <linux/irqchip/chained_irq.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/module.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/platform_device.h>
  20. #define PIC_CAUSE 0x0
  21. #define PIC_MASK 0x4
  22. #define PIC_MAX_IRQS 32
  23. #define PIC_MAX_IRQ_MASK ((1UL << PIC_MAX_IRQS) - 1)
  24. struct mvebu_pic {
  25. void __iomem *base;
  26. u32 parent_irq;
  27. struct irq_domain *domain;
  28. struct irq_chip irq_chip;
  29. };
  30. static void mvebu_pic_reset(struct mvebu_pic *pic)
  31. {
  32. /* ACK and mask all interrupts */
  33. writel(0, pic->base + PIC_MASK);
  34. writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE);
  35. }
  36. static void mvebu_pic_eoi_irq(struct irq_data *d)
  37. {
  38. struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
  39. writel(1 << d->hwirq, pic->base + PIC_CAUSE);
  40. }
  41. static void mvebu_pic_mask_irq(struct irq_data *d)
  42. {
  43. struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
  44. u32 reg;
  45. reg = readl(pic->base + PIC_MASK);
  46. reg |= (1 << d->hwirq);
  47. writel(reg, pic->base + PIC_MASK);
  48. }
  49. static void mvebu_pic_unmask_irq(struct irq_data *d)
  50. {
  51. struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
  52. u32 reg;
  53. reg = readl(pic->base + PIC_MASK);
  54. reg &= ~(1 << d->hwirq);
  55. writel(reg, pic->base + PIC_MASK);
  56. }
  57. static int mvebu_pic_irq_map(struct irq_domain *domain, unsigned int virq,
  58. irq_hw_number_t hwirq)
  59. {
  60. struct mvebu_pic *pic = domain->host_data;
  61. irq_set_percpu_devid(virq);
  62. irq_set_chip_data(virq, pic);
  63. irq_set_chip_and_handler(virq, &pic->irq_chip,
  64. handle_percpu_devid_irq);
  65. irq_set_status_flags(virq, IRQ_LEVEL);
  66. irq_set_probe(virq);
  67. return 0;
  68. }
  69. static const struct irq_domain_ops mvebu_pic_domain_ops = {
  70. .map = mvebu_pic_irq_map,
  71. .xlate = irq_domain_xlate_onecell,
  72. };
  73. static void mvebu_pic_handle_cascade_irq(struct irq_desc *desc)
  74. {
  75. struct mvebu_pic *pic = irq_desc_get_handler_data(desc);
  76. struct irq_chip *chip = irq_desc_get_chip(desc);
  77. unsigned long irqmap, irqn;
  78. unsigned int cascade_irq;
  79. irqmap = readl_relaxed(pic->base + PIC_CAUSE);
  80. chained_irq_enter(chip, desc);
  81. for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
  82. cascade_irq = irq_find_mapping(pic->domain, irqn);
  83. generic_handle_irq(cascade_irq);
  84. }
  85. chained_irq_exit(chip, desc);
  86. }
  87. static void mvebu_pic_enable_percpu_irq(void *data)
  88. {
  89. struct mvebu_pic *pic = data;
  90. mvebu_pic_reset(pic);
  91. enable_percpu_irq(pic->parent_irq, IRQ_TYPE_NONE);
  92. }
  93. static void mvebu_pic_disable_percpu_irq(void *data)
  94. {
  95. struct mvebu_pic *pic = data;
  96. disable_percpu_irq(pic->parent_irq);
  97. }
  98. static int mvebu_pic_probe(struct platform_device *pdev)
  99. {
  100. struct device_node *node = pdev->dev.of_node;
  101. struct mvebu_pic *pic;
  102. struct irq_chip *irq_chip;
  103. struct resource *res;
  104. pic = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pic), GFP_KERNEL);
  105. if (!pic)
  106. return -ENOMEM;
  107. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  108. pic->base = devm_ioremap_resource(&pdev->dev, res);
  109. if (IS_ERR(pic->base))
  110. return PTR_ERR(pic->base);
  111. irq_chip = &pic->irq_chip;
  112. irq_chip->name = dev_name(&pdev->dev);
  113. irq_chip->irq_mask = mvebu_pic_mask_irq;
  114. irq_chip->irq_unmask = mvebu_pic_unmask_irq;
  115. irq_chip->irq_eoi = mvebu_pic_eoi_irq;
  116. pic->parent_irq = irq_of_parse_and_map(node, 0);
  117. if (pic->parent_irq <= 0) {
  118. dev_err(&pdev->dev, "Failed to parse parent interrupt\n");
  119. return -EINVAL;
  120. }
  121. pic->domain = irq_domain_add_linear(node, PIC_MAX_IRQS,
  122. &mvebu_pic_domain_ops, pic);
  123. if (!pic->domain) {
  124. dev_err(&pdev->dev, "Failed to allocate irq domain\n");
  125. return -ENOMEM;
  126. }
  127. irq_set_chained_handler(pic->parent_irq, mvebu_pic_handle_cascade_irq);
  128. irq_set_handler_data(pic->parent_irq, pic);
  129. on_each_cpu(mvebu_pic_enable_percpu_irq, pic, 1);
  130. platform_set_drvdata(pdev, pic);
  131. return 0;
  132. }
  133. static int mvebu_pic_remove(struct platform_device *pdev)
  134. {
  135. struct mvebu_pic *pic = platform_get_drvdata(pdev);
  136. on_each_cpu(mvebu_pic_disable_percpu_irq, pic, 1);
  137. irq_domain_remove(pic->domain);
  138. return 0;
  139. }
  140. static const struct of_device_id mvebu_pic_of_match[] = {
  141. { .compatible = "marvell,armada-8k-pic", },
  142. {},
  143. };
  144. MODULE_DEVICE_TABLE(of, mvebu_pic_of_match);
  145. static struct platform_driver mvebu_pic_driver = {
  146. .probe = mvebu_pic_probe,
  147. .remove = mvebu_pic_remove,
  148. .driver = {
  149. .name = "mvebu-pic",
  150. .of_match_table = mvebu_pic_of_match,
  151. },
  152. };
  153. module_platform_driver(mvebu_pic_driver);
  154. MODULE_AUTHOR("Yehuda Yitschak <yehuday@marvell.com>");
  155. MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
  156. MODULE_LICENSE("GPL v2");
  157. MODULE_ALIAS("platform:mvebu_pic");