irq-mvebu-icu.c 11 KB

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  1. /*
  2. * Copyright (C) 2017 Marvell
  3. *
  4. * Hanna Hawa <hannah@marvell.com>
  5. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqchip.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/jump_label.h>
  16. #include <linux/kernel.h>
  17. #include <linux/msi.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/platform_device.h>
  21. #include <dt-bindings/interrupt-controller/mvebu-icu.h>
  22. /* ICU registers */
  23. #define ICU_SETSPI_NSR_AL 0x10
  24. #define ICU_SETSPI_NSR_AH 0x14
  25. #define ICU_CLRSPI_NSR_AL 0x18
  26. #define ICU_CLRSPI_NSR_AH 0x1c
  27. #define ICU_SET_SEI_AL 0x50
  28. #define ICU_SET_SEI_AH 0x54
  29. #define ICU_CLR_SEI_AL 0x58
  30. #define ICU_CLR_SEI_AH 0x5C
  31. #define ICU_INT_CFG(x) (0x100 + 4 * (x))
  32. #define ICU_INT_ENABLE BIT(24)
  33. #define ICU_IS_EDGE BIT(28)
  34. #define ICU_GROUP_SHIFT 29
  35. /* ICU definitions */
  36. #define ICU_MAX_IRQS 207
  37. #define ICU_SATA0_ICU_ID 109
  38. #define ICU_SATA1_ICU_ID 107
  39. struct mvebu_icu_subset_data {
  40. unsigned int icu_group;
  41. unsigned int offset_set_ah;
  42. unsigned int offset_set_al;
  43. unsigned int offset_clr_ah;
  44. unsigned int offset_clr_al;
  45. };
  46. struct mvebu_icu {
  47. void __iomem *base;
  48. struct device *dev;
  49. };
  50. struct mvebu_icu_msi_data {
  51. struct mvebu_icu *icu;
  52. atomic_t initialized;
  53. const struct mvebu_icu_subset_data *subset_data;
  54. };
  55. struct mvebu_icu_irq_data {
  56. struct mvebu_icu *icu;
  57. unsigned int icu_group;
  58. unsigned int type;
  59. };
  60. static DEFINE_STATIC_KEY_FALSE(legacy_bindings);
  61. static void mvebu_icu_init(struct mvebu_icu *icu,
  62. struct mvebu_icu_msi_data *msi_data,
  63. struct msi_msg *msg)
  64. {
  65. const struct mvebu_icu_subset_data *subset = msi_data->subset_data;
  66. if (atomic_cmpxchg(&msi_data->initialized, false, true))
  67. return;
  68. /* Set 'SET' ICU SPI message address in AP */
  69. writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah);
  70. writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al);
  71. if (subset->icu_group != ICU_GRP_NSR)
  72. return;
  73. /* Set 'CLEAR' ICU SPI message address in AP (level-MSI only) */
  74. writel_relaxed(msg[1].address_hi, icu->base + subset->offset_clr_ah);
  75. writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al);
  76. }
  77. static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
  78. {
  79. struct irq_data *d = irq_get_irq_data(desc->irq);
  80. struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d->domain);
  81. struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
  82. struct mvebu_icu *icu = icu_irqd->icu;
  83. unsigned int icu_int;
  84. if (msg->address_lo || msg->address_hi) {
  85. /* One off initialization per domain */
  86. mvebu_icu_init(icu, msi_data, msg);
  87. /* Configure the ICU with irq number & type */
  88. icu_int = msg->data | ICU_INT_ENABLE;
  89. if (icu_irqd->type & IRQ_TYPE_EDGE_RISING)
  90. icu_int |= ICU_IS_EDGE;
  91. icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT;
  92. } else {
  93. /* De-configure the ICU */
  94. icu_int = 0;
  95. }
  96. writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq));
  97. /*
  98. * The SATA unit has 2 ports, and a dedicated ICU entry per
  99. * port. The ahci sata driver supports only one irq interrupt
  100. * per SATA unit. To solve this conflict, we configure the 2
  101. * SATA wired interrupts in the south bridge into 1 GIC
  102. * interrupt in the north bridge. Even if only a single port
  103. * is enabled, if sata node is enabled, both interrupts are
  104. * configured (regardless of which port is actually in use).
  105. */
  106. if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) {
  107. writel_relaxed(icu_int,
  108. icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID));
  109. writel_relaxed(icu_int,
  110. icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID));
  111. }
  112. }
  113. static struct irq_chip mvebu_icu_nsr_chip = {
  114. .name = "ICU-NSR",
  115. .irq_mask = irq_chip_mask_parent,
  116. .irq_unmask = irq_chip_unmask_parent,
  117. .irq_eoi = irq_chip_eoi_parent,
  118. .irq_set_type = irq_chip_set_type_parent,
  119. .irq_set_affinity = irq_chip_set_affinity_parent,
  120. };
  121. static struct irq_chip mvebu_icu_sei_chip = {
  122. .name = "ICU-SEI",
  123. .irq_ack = irq_chip_ack_parent,
  124. .irq_mask = irq_chip_mask_parent,
  125. .irq_unmask = irq_chip_unmask_parent,
  126. .irq_set_type = irq_chip_set_type_parent,
  127. .irq_set_affinity = irq_chip_set_affinity_parent,
  128. };
  129. static int
  130. mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
  131. unsigned long *hwirq, unsigned int *type)
  132. {
  133. struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d);
  134. struct mvebu_icu *icu = platform_msi_get_host_data(d);
  135. unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2;
  136. /* Check the count of the parameters in dt */
  137. if (WARN_ON(fwspec->param_count != param_count)) {
  138. dev_err(icu->dev, "wrong ICU parameter count %d\n",
  139. fwspec->param_count);
  140. return -EINVAL;
  141. }
  142. if (static_branch_unlikely(&legacy_bindings)) {
  143. *hwirq = fwspec->param[1];
  144. *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
  145. if (fwspec->param[0] != ICU_GRP_NSR) {
  146. dev_err(icu->dev, "wrong ICU group type %x\n",
  147. fwspec->param[0]);
  148. return -EINVAL;
  149. }
  150. } else {
  151. *hwirq = fwspec->param[0];
  152. *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
  153. /*
  154. * The ICU receives level interrupts. While the NSR are also
  155. * level interrupts, SEI are edge interrupts. Force the type
  156. * here in this case. Please note that this makes the interrupt
  157. * handling unreliable.
  158. */
  159. if (msi_data->subset_data->icu_group == ICU_GRP_SEI)
  160. *type = IRQ_TYPE_EDGE_RISING;
  161. }
  162. if (*hwirq >= ICU_MAX_IRQS) {
  163. dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq);
  164. return -EINVAL;
  165. }
  166. return 0;
  167. }
  168. static int
  169. mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  170. unsigned int nr_irqs, void *args)
  171. {
  172. int err;
  173. unsigned long hwirq;
  174. struct irq_fwspec *fwspec = args;
  175. struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(domain);
  176. struct mvebu_icu *icu = msi_data->icu;
  177. struct mvebu_icu_irq_data *icu_irqd;
  178. struct irq_chip *chip = &mvebu_icu_nsr_chip;
  179. icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL);
  180. if (!icu_irqd)
  181. return -ENOMEM;
  182. err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq,
  183. &icu_irqd->type);
  184. if (err) {
  185. dev_err(icu->dev, "failed to translate ICU parameters\n");
  186. goto free_irqd;
  187. }
  188. if (static_branch_unlikely(&legacy_bindings))
  189. icu_irqd->icu_group = fwspec->param[0];
  190. else
  191. icu_irqd->icu_group = msi_data->subset_data->icu_group;
  192. icu_irqd->icu = icu;
  193. err = platform_msi_domain_alloc(domain, virq, nr_irqs);
  194. if (err) {
  195. dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n");
  196. goto free_irqd;
  197. }
  198. /* Make sure there is no interrupt left pending by the firmware */
  199. err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false);
  200. if (err)
  201. goto free_msi;
  202. if (icu_irqd->icu_group == ICU_GRP_SEI)
  203. chip = &mvebu_icu_sei_chip;
  204. err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
  205. chip, icu_irqd);
  206. if (err) {
  207. dev_err(icu->dev, "failed to set the data to IRQ domain\n");
  208. goto free_msi;
  209. }
  210. return 0;
  211. free_msi:
  212. platform_msi_domain_free(domain, virq, nr_irqs);
  213. free_irqd:
  214. kfree(icu_irqd);
  215. return err;
  216. }
  217. static void
  218. mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq,
  219. unsigned int nr_irqs)
  220. {
  221. struct irq_data *d = irq_get_irq_data(virq);
  222. struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
  223. kfree(icu_irqd);
  224. platform_msi_domain_free(domain, virq, nr_irqs);
  225. }
  226. static const struct irq_domain_ops mvebu_icu_domain_ops = {
  227. .translate = mvebu_icu_irq_domain_translate,
  228. .alloc = mvebu_icu_irq_domain_alloc,
  229. .free = mvebu_icu_irq_domain_free,
  230. };
  231. static const struct mvebu_icu_subset_data mvebu_icu_nsr_subset_data = {
  232. .icu_group = ICU_GRP_NSR,
  233. .offset_set_ah = ICU_SETSPI_NSR_AH,
  234. .offset_set_al = ICU_SETSPI_NSR_AL,
  235. .offset_clr_ah = ICU_CLRSPI_NSR_AH,
  236. .offset_clr_al = ICU_CLRSPI_NSR_AL,
  237. };
  238. static const struct mvebu_icu_subset_data mvebu_icu_sei_subset_data = {
  239. .icu_group = ICU_GRP_SEI,
  240. .offset_set_ah = ICU_SET_SEI_AH,
  241. .offset_set_al = ICU_SET_SEI_AL,
  242. };
  243. static const struct of_device_id mvebu_icu_subset_of_match[] = {
  244. {
  245. .compatible = "marvell,cp110-icu-nsr",
  246. .data = &mvebu_icu_nsr_subset_data,
  247. },
  248. {
  249. .compatible = "marvell,cp110-icu-sei",
  250. .data = &mvebu_icu_sei_subset_data,
  251. },
  252. {},
  253. };
  254. static int mvebu_icu_subset_probe(struct platform_device *pdev)
  255. {
  256. struct mvebu_icu_msi_data *msi_data;
  257. struct device_node *msi_parent_dn;
  258. struct device *dev = &pdev->dev;
  259. struct irq_domain *irq_domain;
  260. msi_data = devm_kzalloc(dev, sizeof(*msi_data), GFP_KERNEL);
  261. if (!msi_data)
  262. return -ENOMEM;
  263. if (static_branch_unlikely(&legacy_bindings)) {
  264. msi_data->icu = dev_get_drvdata(dev);
  265. msi_data->subset_data = &mvebu_icu_nsr_subset_data;
  266. } else {
  267. msi_data->icu = dev_get_drvdata(dev->parent);
  268. msi_data->subset_data = of_device_get_match_data(dev);
  269. }
  270. dev->msi_domain = of_msi_get_domain(dev, dev->of_node,
  271. DOMAIN_BUS_PLATFORM_MSI);
  272. if (!dev->msi_domain)
  273. return -EPROBE_DEFER;
  274. msi_parent_dn = irq_domain_get_of_node(dev->msi_domain);
  275. if (!msi_parent_dn)
  276. return -ENODEV;
  277. irq_domain = platform_msi_create_device_tree_domain(dev, ICU_MAX_IRQS,
  278. mvebu_icu_write_msg,
  279. &mvebu_icu_domain_ops,
  280. msi_data);
  281. if (!irq_domain) {
  282. dev_err(dev, "Failed to create ICU MSI domain\n");
  283. return -ENOMEM;
  284. }
  285. return 0;
  286. }
  287. static struct platform_driver mvebu_icu_subset_driver = {
  288. .probe = mvebu_icu_subset_probe,
  289. .driver = {
  290. .name = "mvebu-icu-subset",
  291. .of_match_table = mvebu_icu_subset_of_match,
  292. },
  293. };
  294. builtin_platform_driver(mvebu_icu_subset_driver);
  295. static int mvebu_icu_probe(struct platform_device *pdev)
  296. {
  297. struct mvebu_icu *icu;
  298. struct resource *res;
  299. int i;
  300. icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu),
  301. GFP_KERNEL);
  302. if (!icu)
  303. return -ENOMEM;
  304. icu->dev = &pdev->dev;
  305. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  306. icu->base = devm_ioremap_resource(&pdev->dev, res);
  307. if (IS_ERR(icu->base)) {
  308. dev_err(&pdev->dev, "Failed to map icu base address.\n");
  309. return PTR_ERR(icu->base);
  310. }
  311. /*
  312. * Legacy bindings: ICU is one node with one MSI parent: force manually
  313. * the probe of the NSR interrupts side.
  314. * New bindings: ICU node has children, one per interrupt controller
  315. * having its own MSI parent: call platform_populate().
  316. * All ICU instances should use the same bindings.
  317. */
  318. if (!of_get_child_count(pdev->dev.of_node))
  319. static_branch_enable(&legacy_bindings);
  320. /*
  321. * Clean all ICU interrupts of type NSR and SEI, required to
  322. * avoid unpredictable SPI assignments done by firmware.
  323. */
  324. for (i = 0 ; i < ICU_MAX_IRQS ; i++) {
  325. u32 icu_int, icu_grp;
  326. icu_int = readl_relaxed(icu->base + ICU_INT_CFG(i));
  327. icu_grp = icu_int >> ICU_GROUP_SHIFT;
  328. if (icu_grp == ICU_GRP_NSR ||
  329. (icu_grp == ICU_GRP_SEI &&
  330. !static_branch_unlikely(&legacy_bindings)))
  331. writel_relaxed(0x0, icu->base + ICU_INT_CFG(i));
  332. }
  333. platform_set_drvdata(pdev, icu);
  334. if (static_branch_unlikely(&legacy_bindings))
  335. return mvebu_icu_subset_probe(pdev);
  336. else
  337. return devm_of_platform_populate(&pdev->dev);
  338. }
  339. static const struct of_device_id mvebu_icu_of_match[] = {
  340. { .compatible = "marvell,cp110-icu", },
  341. {},
  342. };
  343. static struct platform_driver mvebu_icu_driver = {
  344. .probe = mvebu_icu_probe,
  345. .driver = {
  346. .name = "mvebu-icu",
  347. .of_match_table = mvebu_icu_of_match,
  348. },
  349. };
  350. builtin_platform_driver(mvebu_icu_driver);