irq-mtk-cirq.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016 MediaTek Inc.
  4. * Author: Youlin.Pei <youlin.pei@mediatek.com>
  5. */
  6. #include <linux/interrupt.h>
  7. #include <linux/io.h>
  8. #include <linux/irq.h>
  9. #include <linux/irqchip.h>
  10. #include <linux/irqdomain.h>
  11. #include <linux/of.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/of_address.h>
  14. #include <linux/slab.h>
  15. #include <linux/syscore_ops.h>
  16. #define CIRQ_ACK 0x40
  17. #define CIRQ_MASK_SET 0xc0
  18. #define CIRQ_MASK_CLR 0x100
  19. #define CIRQ_SENS_SET 0x180
  20. #define CIRQ_SENS_CLR 0x1c0
  21. #define CIRQ_POL_SET 0x240
  22. #define CIRQ_POL_CLR 0x280
  23. #define CIRQ_CONTROL 0x300
  24. #define CIRQ_EN 0x1
  25. #define CIRQ_EDGE 0x2
  26. #define CIRQ_FLUSH 0x4
  27. struct mtk_cirq_chip_data {
  28. void __iomem *base;
  29. unsigned int ext_irq_start;
  30. unsigned int ext_irq_end;
  31. struct irq_domain *domain;
  32. };
  33. static struct mtk_cirq_chip_data *cirq_data;
  34. static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset)
  35. {
  36. struct mtk_cirq_chip_data *chip_data = data->chip_data;
  37. unsigned int cirq_num = data->hwirq;
  38. u32 mask = 1 << (cirq_num % 32);
  39. writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4);
  40. }
  41. static void mtk_cirq_mask(struct irq_data *data)
  42. {
  43. mtk_cirq_write_mask(data, CIRQ_MASK_SET);
  44. irq_chip_mask_parent(data);
  45. }
  46. static void mtk_cirq_unmask(struct irq_data *data)
  47. {
  48. mtk_cirq_write_mask(data, CIRQ_MASK_CLR);
  49. irq_chip_unmask_parent(data);
  50. }
  51. static int mtk_cirq_set_type(struct irq_data *data, unsigned int type)
  52. {
  53. int ret;
  54. switch (type & IRQ_TYPE_SENSE_MASK) {
  55. case IRQ_TYPE_EDGE_FALLING:
  56. mtk_cirq_write_mask(data, CIRQ_POL_CLR);
  57. mtk_cirq_write_mask(data, CIRQ_SENS_CLR);
  58. break;
  59. case IRQ_TYPE_EDGE_RISING:
  60. mtk_cirq_write_mask(data, CIRQ_POL_SET);
  61. mtk_cirq_write_mask(data, CIRQ_SENS_CLR);
  62. break;
  63. case IRQ_TYPE_LEVEL_LOW:
  64. mtk_cirq_write_mask(data, CIRQ_POL_CLR);
  65. mtk_cirq_write_mask(data, CIRQ_SENS_SET);
  66. break;
  67. case IRQ_TYPE_LEVEL_HIGH:
  68. mtk_cirq_write_mask(data, CIRQ_POL_SET);
  69. mtk_cirq_write_mask(data, CIRQ_SENS_SET);
  70. break;
  71. default:
  72. break;
  73. }
  74. data = data->parent_data;
  75. ret = data->chip->irq_set_type(data, type);
  76. return ret;
  77. }
  78. static struct irq_chip mtk_cirq_chip = {
  79. .name = "MT_CIRQ",
  80. .irq_mask = mtk_cirq_mask,
  81. .irq_unmask = mtk_cirq_unmask,
  82. .irq_eoi = irq_chip_eoi_parent,
  83. .irq_set_type = mtk_cirq_set_type,
  84. .irq_retrigger = irq_chip_retrigger_hierarchy,
  85. #ifdef CONFIG_SMP
  86. .irq_set_affinity = irq_chip_set_affinity_parent,
  87. #endif
  88. };
  89. static int mtk_cirq_domain_translate(struct irq_domain *d,
  90. struct irq_fwspec *fwspec,
  91. unsigned long *hwirq,
  92. unsigned int *type)
  93. {
  94. if (is_of_node(fwspec->fwnode)) {
  95. if (fwspec->param_count != 3)
  96. return -EINVAL;
  97. /* No PPI should point to this domain */
  98. if (fwspec->param[0] != 0)
  99. return -EINVAL;
  100. /* cirq support irq number check */
  101. if (fwspec->param[1] < cirq_data->ext_irq_start ||
  102. fwspec->param[1] > cirq_data->ext_irq_end)
  103. return -EINVAL;
  104. *hwirq = fwspec->param[1] - cirq_data->ext_irq_start;
  105. *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
  106. return 0;
  107. }
  108. return -EINVAL;
  109. }
  110. static int mtk_cirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  111. unsigned int nr_irqs, void *arg)
  112. {
  113. int ret;
  114. irq_hw_number_t hwirq;
  115. unsigned int type;
  116. struct irq_fwspec *fwspec = arg;
  117. struct irq_fwspec parent_fwspec = *fwspec;
  118. ret = mtk_cirq_domain_translate(domain, fwspec, &hwirq, &type);
  119. if (ret)
  120. return ret;
  121. if (WARN_ON(nr_irqs != 1))
  122. return -EINVAL;
  123. irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
  124. &mtk_cirq_chip,
  125. domain->host_data);
  126. parent_fwspec.fwnode = domain->parent->fwnode;
  127. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
  128. &parent_fwspec);
  129. }
  130. static const struct irq_domain_ops cirq_domain_ops = {
  131. .translate = mtk_cirq_domain_translate,
  132. .alloc = mtk_cirq_domain_alloc,
  133. .free = irq_domain_free_irqs_common,
  134. };
  135. #ifdef CONFIG_PM_SLEEP
  136. static int mtk_cirq_suspend(void)
  137. {
  138. u32 value, mask;
  139. unsigned int irq, hwirq_num;
  140. bool pending, masked;
  141. int i, pendret, maskret;
  142. /*
  143. * When external interrupts happened, CIRQ will record the status
  144. * even CIRQ is not enabled. When execute flush command, CIRQ will
  145. * resend the signals according to the status. So if don't clear the
  146. * status, CIRQ will resend the wrong signals.
  147. *
  148. * arch_suspend_disable_irqs() will be called before CIRQ suspend
  149. * callback. If clear all the status simply, the external interrupts
  150. * which happened between arch_suspend_disable_irqs and CIRQ suspend
  151. * callback will be lost. Using following steps to avoid this issue;
  152. *
  153. * - Iterate over all the CIRQ supported interrupts;
  154. * - For each interrupt, inspect its pending and masked status at GIC
  155. * level;
  156. * - If pending and unmasked, it happened between
  157. * arch_suspend_disable_irqs and CIRQ suspend callback, don't ACK
  158. * it. Otherwise, ACK it.
  159. */
  160. hwirq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
  161. for (i = 0; i < hwirq_num; i++) {
  162. irq = irq_find_mapping(cirq_data->domain, i);
  163. if (irq) {
  164. pendret = irq_get_irqchip_state(irq,
  165. IRQCHIP_STATE_PENDING,
  166. &pending);
  167. maskret = irq_get_irqchip_state(irq,
  168. IRQCHIP_STATE_MASKED,
  169. &masked);
  170. if (pendret == 0 && maskret == 0 &&
  171. (pending && !masked))
  172. continue;
  173. }
  174. mask = 1 << (i % 32);
  175. writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4);
  176. }
  177. /* set edge_only mode, record edge-triggerd interrupts */
  178. /* enable cirq */
  179. value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
  180. value |= (CIRQ_EDGE | CIRQ_EN);
  181. writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
  182. return 0;
  183. }
  184. static void mtk_cirq_resume(void)
  185. {
  186. u32 value;
  187. /* flush recored interrupts, will send signals to parent controller */
  188. value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
  189. writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL);
  190. /* disable cirq */
  191. value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
  192. value &= ~(CIRQ_EDGE | CIRQ_EN);
  193. writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
  194. }
  195. static struct syscore_ops mtk_cirq_syscore_ops = {
  196. .suspend = mtk_cirq_suspend,
  197. .resume = mtk_cirq_resume,
  198. };
  199. static void mtk_cirq_syscore_init(void)
  200. {
  201. register_syscore_ops(&mtk_cirq_syscore_ops);
  202. }
  203. #else
  204. static inline void mtk_cirq_syscore_init(void) {}
  205. #endif
  206. static int __init mtk_cirq_of_init(struct device_node *node,
  207. struct device_node *parent)
  208. {
  209. struct irq_domain *domain, *domain_parent;
  210. unsigned int irq_num;
  211. int ret;
  212. domain_parent = irq_find_host(parent);
  213. if (!domain_parent) {
  214. pr_err("mtk_cirq: interrupt-parent not found\n");
  215. return -EINVAL;
  216. }
  217. cirq_data = kzalloc(sizeof(*cirq_data), GFP_KERNEL);
  218. if (!cirq_data)
  219. return -ENOMEM;
  220. cirq_data->base = of_iomap(node, 0);
  221. if (!cirq_data->base) {
  222. pr_err("mtk_cirq: unable to map cirq register\n");
  223. ret = -ENXIO;
  224. goto out_free;
  225. }
  226. ret = of_property_read_u32_index(node, "mediatek,ext-irq-range", 0,
  227. &cirq_data->ext_irq_start);
  228. if (ret)
  229. goto out_unmap;
  230. ret = of_property_read_u32_index(node, "mediatek,ext-irq-range", 1,
  231. &cirq_data->ext_irq_end);
  232. if (ret)
  233. goto out_unmap;
  234. irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
  235. domain = irq_domain_add_hierarchy(domain_parent, 0,
  236. irq_num, node,
  237. &cirq_domain_ops, cirq_data);
  238. if (!domain) {
  239. ret = -ENOMEM;
  240. goto out_unmap;
  241. }
  242. cirq_data->domain = domain;
  243. mtk_cirq_syscore_init();
  244. return 0;
  245. out_unmap:
  246. iounmap(cirq_data->base);
  247. out_free:
  248. kfree(cirq_data);
  249. return ret;
  250. }
  251. IRQCHIP_DECLARE(mtk_cirq, "mediatek,mtk-cirq", mtk_cirq_of_init);