irq-mips-cpu.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2001 MontaVista Software Inc.
  4. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  5. *
  6. * Copyright (C) 2001 Ralf Baechle
  7. * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
  8. * Author: Maciej W. Rozycki <macro@mips.com>
  9. *
  10. * This file define the irq handler for MIPS CPU interrupts.
  11. */
  12. /*
  13. * Almost all MIPS CPUs define 8 interrupt sources. They are typically
  14. * level triggered (i.e., cannot be cleared from CPU; must be cleared from
  15. * device).
  16. *
  17. * The first two are software interrupts (i.e. not exposed as pins) which
  18. * may be used for IPIs in multi-threaded single-core systems.
  19. *
  20. * The last one is usually the CPU timer interrupt if the counter register
  21. * is present, or for old CPUs with an external FPU by convention it's the
  22. * FPU exception interrupt.
  23. */
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/kernel.h>
  27. #include <linux/irq.h>
  28. #include <linux/irqchip.h>
  29. #include <linux/irqdomain.h>
  30. #include <asm/irq_cpu.h>
  31. #include <asm/mipsregs.h>
  32. #include <asm/mipsmtregs.h>
  33. #include <asm/setup.h>
  34. static struct irq_domain *irq_domain;
  35. static struct irq_domain *ipi_domain;
  36. static inline void unmask_mips_irq(struct irq_data *d)
  37. {
  38. set_c0_status(IE_SW0 << d->hwirq);
  39. irq_enable_hazard();
  40. }
  41. static inline void mask_mips_irq(struct irq_data *d)
  42. {
  43. clear_c0_status(IE_SW0 << d->hwirq);
  44. irq_disable_hazard();
  45. }
  46. static struct irq_chip mips_cpu_irq_controller = {
  47. .name = "MIPS",
  48. .irq_ack = mask_mips_irq,
  49. .irq_mask = mask_mips_irq,
  50. .irq_mask_ack = mask_mips_irq,
  51. .irq_unmask = unmask_mips_irq,
  52. .irq_eoi = unmask_mips_irq,
  53. .irq_disable = mask_mips_irq,
  54. .irq_enable = unmask_mips_irq,
  55. };
  56. /*
  57. * Basically the same as above but taking care of all the MT stuff
  58. */
  59. static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
  60. {
  61. unsigned int vpflags = dvpe();
  62. clear_c0_cause(C_SW0 << d->hwirq);
  63. evpe(vpflags);
  64. unmask_mips_irq(d);
  65. return 0;
  66. }
  67. /*
  68. * While we ack the interrupt interrupts are disabled and thus we don't need
  69. * to deal with concurrency issues. Same for mips_cpu_irq_end.
  70. */
  71. static void mips_mt_cpu_irq_ack(struct irq_data *d)
  72. {
  73. unsigned int vpflags = dvpe();
  74. clear_c0_cause(C_SW0 << d->hwirq);
  75. evpe(vpflags);
  76. mask_mips_irq(d);
  77. }
  78. #ifdef CONFIG_GENERIC_IRQ_IPI
  79. static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu)
  80. {
  81. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  82. unsigned long flags;
  83. int vpflags;
  84. local_irq_save(flags);
  85. /* We can only send IPIs to VPEs within the local core */
  86. WARN_ON(!cpus_are_siblings(smp_processor_id(), cpu));
  87. vpflags = dvpe();
  88. settc(cpu_vpe_id(&cpu_data[cpu]));
  89. write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq));
  90. evpe(vpflags);
  91. local_irq_restore(flags);
  92. }
  93. #endif /* CONFIG_GENERIC_IRQ_IPI */
  94. static struct irq_chip mips_mt_cpu_irq_controller = {
  95. .name = "MIPS",
  96. .irq_startup = mips_mt_cpu_irq_startup,
  97. .irq_ack = mips_mt_cpu_irq_ack,
  98. .irq_mask = mask_mips_irq,
  99. .irq_mask_ack = mips_mt_cpu_irq_ack,
  100. .irq_unmask = unmask_mips_irq,
  101. .irq_eoi = unmask_mips_irq,
  102. .irq_disable = mask_mips_irq,
  103. .irq_enable = unmask_mips_irq,
  104. #ifdef CONFIG_GENERIC_IRQ_IPI
  105. .ipi_send_single = mips_mt_send_ipi,
  106. #endif
  107. };
  108. asmlinkage void __weak plat_irq_dispatch(void)
  109. {
  110. unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
  111. unsigned int virq;
  112. int irq;
  113. if (!pending) {
  114. spurious_interrupt();
  115. return;
  116. }
  117. pending >>= CAUSEB_IP;
  118. while (pending) {
  119. irq = fls(pending) - 1;
  120. if (IS_ENABLED(CONFIG_GENERIC_IRQ_IPI) && irq < 2)
  121. virq = irq_linear_revmap(ipi_domain, irq);
  122. else
  123. virq = irq_linear_revmap(irq_domain, irq);
  124. do_IRQ(virq);
  125. pending &= ~BIT(irq);
  126. }
  127. }
  128. static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
  129. irq_hw_number_t hw)
  130. {
  131. struct irq_chip *chip;
  132. if (hw < 2 && cpu_has_mipsmt) {
  133. /* Software interrupts are used for MT/CMT IPI */
  134. chip = &mips_mt_cpu_irq_controller;
  135. } else {
  136. chip = &mips_cpu_irq_controller;
  137. }
  138. if (cpu_has_vint)
  139. set_vi_handler(hw, plat_irq_dispatch);
  140. irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
  141. return 0;
  142. }
  143. static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
  144. .map = mips_cpu_intc_map,
  145. .xlate = irq_domain_xlate_onecell,
  146. };
  147. #ifdef CONFIG_GENERIC_IRQ_IPI
  148. struct cpu_ipi_domain_state {
  149. DECLARE_BITMAP(allocated, 2);
  150. };
  151. static int mips_cpu_ipi_alloc(struct irq_domain *domain, unsigned int virq,
  152. unsigned int nr_irqs, void *arg)
  153. {
  154. struct cpu_ipi_domain_state *state = domain->host_data;
  155. unsigned int i, hwirq;
  156. int ret;
  157. for (i = 0; i < nr_irqs; i++) {
  158. hwirq = find_first_zero_bit(state->allocated, 2);
  159. if (hwirq == 2)
  160. return -EBUSY;
  161. bitmap_set(state->allocated, hwirq, 1);
  162. ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq,
  163. &mips_mt_cpu_irq_controller,
  164. NULL);
  165. if (ret)
  166. return ret;
  167. ret = irq_domain_set_hwirq_and_chip(domain->parent, virq + i, hwirq,
  168. &mips_mt_cpu_irq_controller,
  169. NULL);
  170. if (ret)
  171. return ret;
  172. ret = irq_set_irq_type(virq + i, IRQ_TYPE_LEVEL_HIGH);
  173. if (ret)
  174. return ret;
  175. }
  176. return 0;
  177. }
  178. static int mips_cpu_ipi_match(struct irq_domain *d, struct device_node *node,
  179. enum irq_domain_bus_token bus_token)
  180. {
  181. bool is_ipi;
  182. switch (bus_token) {
  183. case DOMAIN_BUS_IPI:
  184. is_ipi = d->bus_token == bus_token;
  185. return (!node || (to_of_node(d->fwnode) == node)) && is_ipi;
  186. default:
  187. return 0;
  188. }
  189. }
  190. static const struct irq_domain_ops mips_cpu_ipi_chip_ops = {
  191. .alloc = mips_cpu_ipi_alloc,
  192. .match = mips_cpu_ipi_match,
  193. };
  194. static void mips_cpu_register_ipi_domain(struct device_node *of_node)
  195. {
  196. struct cpu_ipi_domain_state *ipi_domain_state;
  197. ipi_domain_state = kzalloc(sizeof(*ipi_domain_state), GFP_KERNEL);
  198. ipi_domain = irq_domain_add_hierarchy(irq_domain,
  199. IRQ_DOMAIN_FLAG_IPI_SINGLE,
  200. 2, of_node,
  201. &mips_cpu_ipi_chip_ops,
  202. ipi_domain_state);
  203. if (!ipi_domain)
  204. panic("Failed to add MIPS CPU IPI domain");
  205. irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
  206. }
  207. #else /* !CONFIG_GENERIC_IRQ_IPI */
  208. static inline void mips_cpu_register_ipi_domain(struct device_node *of_node) {}
  209. #endif /* !CONFIG_GENERIC_IRQ_IPI */
  210. static void __init __mips_cpu_irq_init(struct device_node *of_node)
  211. {
  212. /* Mask interrupts. */
  213. clear_c0_status(ST0_IM);
  214. clear_c0_cause(CAUSEF_IP);
  215. irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
  216. &mips_cpu_intc_irq_domain_ops,
  217. NULL);
  218. if (!irq_domain)
  219. panic("Failed to add irqdomain for MIPS CPU");
  220. /*
  221. * Only proceed to register the software interrupt IPI implementation
  222. * for CPUs which implement the MIPS MT (multi-threading) ASE.
  223. */
  224. if (cpu_has_mipsmt)
  225. mips_cpu_register_ipi_domain(of_node);
  226. }
  227. void __init mips_cpu_irq_init(void)
  228. {
  229. __mips_cpu_irq_init(NULL);
  230. }
  231. int __init mips_cpu_irq_of_init(struct device_node *of_node,
  232. struct device_node *parent)
  233. {
  234. __mips_cpu_irq_init(of_node);
  235. return 0;
  236. }
  237. IRQCHIP_DECLARE(cpu_intc, "mti,cpu-interrupt-controller", mips_cpu_irq_of_init);