irq-mbigen.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
  4. * Author: Jun Ma <majun258@huawei.com>
  5. * Author: Yun Wu <wuyun.wu@huawei.com>
  6. */
  7. #include <linux/acpi.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/irqchip.h>
  10. #include <linux/module.h>
  11. #include <linux/msi.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. /* Interrupt numbers per mbigen node supported */
  18. #define IRQS_PER_MBIGEN_NODE 128
  19. /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
  20. #define RESERVED_IRQ_PER_MBIGEN_CHIP 64
  21. /* The maximum IRQ pin number of mbigen chip(start from 0) */
  22. #define MAXIMUM_IRQ_PIN_NUM 1407
  23. /**
  24. * In mbigen vector register
  25. * bit[21:12]: event id value
  26. * bit[11:0]: device id
  27. */
  28. #define IRQ_EVENT_ID_SHIFT 12
  29. #define IRQ_EVENT_ID_MASK 0x3ff
  30. /* register range of each mbigen node */
  31. #define MBIGEN_NODE_OFFSET 0x1000
  32. /* offset of vector register in mbigen node */
  33. #define REG_MBIGEN_VEC_OFFSET 0x200
  34. /**
  35. * offset of clear register in mbigen node
  36. * This register is used to clear the status
  37. * of interrupt
  38. */
  39. #define REG_MBIGEN_CLEAR_OFFSET 0xa000
  40. /**
  41. * offset of interrupt type register
  42. * This register is used to configure interrupt
  43. * trigger type
  44. */
  45. #define REG_MBIGEN_TYPE_OFFSET 0x0
  46. /**
  47. * struct mbigen_device - holds the information of mbigen device.
  48. *
  49. * @pdev: pointer to the platform device structure of mbigen chip.
  50. * @base: mapped address of this mbigen chip.
  51. */
  52. struct mbigen_device {
  53. struct platform_device *pdev;
  54. void __iomem *base;
  55. };
  56. static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
  57. {
  58. unsigned int nid, pin;
  59. hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
  60. nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
  61. pin = hwirq % IRQS_PER_MBIGEN_NODE;
  62. return pin * 4 + nid * MBIGEN_NODE_OFFSET
  63. + REG_MBIGEN_VEC_OFFSET;
  64. }
  65. static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
  66. u32 *mask, u32 *addr)
  67. {
  68. unsigned int nid, irq_ofst, ofst;
  69. hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
  70. nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
  71. irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
  72. *mask = 1 << (irq_ofst % 32);
  73. ofst = irq_ofst / 32 * 4;
  74. *addr = ofst + nid * MBIGEN_NODE_OFFSET
  75. + REG_MBIGEN_TYPE_OFFSET;
  76. }
  77. static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
  78. u32 *mask, u32 *addr)
  79. {
  80. unsigned int ofst = (hwirq / 32) * 4;
  81. *mask = 1 << (hwirq % 32);
  82. *addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
  83. }
  84. static void mbigen_eoi_irq(struct irq_data *data)
  85. {
  86. void __iomem *base = data->chip_data;
  87. u32 mask, addr;
  88. get_mbigen_clear_reg(data->hwirq, &mask, &addr);
  89. writel_relaxed(mask, base + addr);
  90. irq_chip_eoi_parent(data);
  91. }
  92. static int mbigen_set_type(struct irq_data *data, unsigned int type)
  93. {
  94. void __iomem *base = data->chip_data;
  95. u32 mask, addr, val;
  96. if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
  97. return -EINVAL;
  98. get_mbigen_type_reg(data->hwirq, &mask, &addr);
  99. val = readl_relaxed(base + addr);
  100. if (type == IRQ_TYPE_LEVEL_HIGH)
  101. val |= mask;
  102. else
  103. val &= ~mask;
  104. writel_relaxed(val, base + addr);
  105. return 0;
  106. }
  107. static struct irq_chip mbigen_irq_chip = {
  108. .name = "mbigen-v2",
  109. .irq_mask = irq_chip_mask_parent,
  110. .irq_unmask = irq_chip_unmask_parent,
  111. .irq_eoi = mbigen_eoi_irq,
  112. .irq_set_type = mbigen_set_type,
  113. .irq_set_affinity = irq_chip_set_affinity_parent,
  114. };
  115. static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
  116. {
  117. struct irq_data *d = irq_get_irq_data(desc->irq);
  118. void __iomem *base = d->chip_data;
  119. u32 val;
  120. if (!msg->address_lo && !msg->address_hi)
  121. return;
  122. base += get_mbigen_vec_reg(d->hwirq);
  123. val = readl_relaxed(base);
  124. val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
  125. val |= (msg->data << IRQ_EVENT_ID_SHIFT);
  126. /* The address of doorbell is encoded in mbigen register by default
  127. * So,we don't need to program the doorbell address at here
  128. */
  129. writel_relaxed(val, base);
  130. }
  131. static int mbigen_domain_translate(struct irq_domain *d,
  132. struct irq_fwspec *fwspec,
  133. unsigned long *hwirq,
  134. unsigned int *type)
  135. {
  136. if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
  137. if (fwspec->param_count != 2)
  138. return -EINVAL;
  139. if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
  140. (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
  141. return -EINVAL;
  142. else
  143. *hwirq = fwspec->param[0];
  144. /* If there is no valid irq type, just use the default type */
  145. if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
  146. (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
  147. *type = fwspec->param[1];
  148. else
  149. return -EINVAL;
  150. return 0;
  151. }
  152. return -EINVAL;
  153. }
  154. static int mbigen_irq_domain_alloc(struct irq_domain *domain,
  155. unsigned int virq,
  156. unsigned int nr_irqs,
  157. void *args)
  158. {
  159. struct irq_fwspec *fwspec = args;
  160. irq_hw_number_t hwirq;
  161. unsigned int type;
  162. struct mbigen_device *mgn_chip;
  163. int i, err;
  164. err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
  165. if (err)
  166. return err;
  167. err = platform_msi_domain_alloc(domain, virq, nr_irqs);
  168. if (err)
  169. return err;
  170. mgn_chip = platform_msi_get_host_data(domain);
  171. for (i = 0; i < nr_irqs; i++)
  172. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  173. &mbigen_irq_chip, mgn_chip->base);
  174. return 0;
  175. }
  176. static void mbigen_irq_domain_free(struct irq_domain *domain, unsigned int virq,
  177. unsigned int nr_irqs)
  178. {
  179. platform_msi_domain_free(domain, virq, nr_irqs);
  180. }
  181. static const struct irq_domain_ops mbigen_domain_ops = {
  182. .translate = mbigen_domain_translate,
  183. .alloc = mbigen_irq_domain_alloc,
  184. .free = mbigen_irq_domain_free,
  185. };
  186. static int mbigen_of_create_domain(struct platform_device *pdev,
  187. struct mbigen_device *mgn_chip)
  188. {
  189. struct device *parent;
  190. struct platform_device *child;
  191. struct irq_domain *domain;
  192. struct device_node *np;
  193. u32 num_pins;
  194. for_each_child_of_node(pdev->dev.of_node, np) {
  195. if (!of_property_read_bool(np, "interrupt-controller"))
  196. continue;
  197. parent = platform_bus_type.dev_root;
  198. child = of_platform_device_create(np, NULL, parent);
  199. if (!child) {
  200. of_node_put(np);
  201. return -ENOMEM;
  202. }
  203. if (of_property_read_u32(child->dev.of_node, "num-pins",
  204. &num_pins) < 0) {
  205. dev_err(&pdev->dev, "No num-pins property\n");
  206. of_node_put(np);
  207. return -EINVAL;
  208. }
  209. domain = platform_msi_create_device_domain(&child->dev, num_pins,
  210. mbigen_write_msg,
  211. &mbigen_domain_ops,
  212. mgn_chip);
  213. if (!domain) {
  214. of_node_put(np);
  215. return -ENOMEM;
  216. }
  217. }
  218. return 0;
  219. }
  220. #ifdef CONFIG_ACPI
  221. static int mbigen_acpi_create_domain(struct platform_device *pdev,
  222. struct mbigen_device *mgn_chip)
  223. {
  224. struct irq_domain *domain;
  225. u32 num_pins = 0;
  226. int ret;
  227. /*
  228. * "num-pins" is the total number of interrupt pins implemented in
  229. * this mbigen instance, and mbigen is an interrupt controller
  230. * connected to ITS converting wired interrupts into MSI, so we
  231. * use "num-pins" to alloc MSI vectors which are needed by client
  232. * devices connected to it.
  233. *
  234. * Here is the DSDT device node used for mbigen in firmware:
  235. * Device(MBI0) {
  236. * Name(_HID, "HISI0152")
  237. * Name(_UID, Zero)
  238. * Name(_CRS, ResourceTemplate() {
  239. * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
  240. * })
  241. *
  242. * Name(_DSD, Package () {
  243. * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
  244. * Package () {
  245. * Package () {"num-pins", 378}
  246. * }
  247. * })
  248. * }
  249. */
  250. ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
  251. if (ret || num_pins == 0)
  252. return -EINVAL;
  253. domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
  254. mbigen_write_msg,
  255. &mbigen_domain_ops,
  256. mgn_chip);
  257. if (!domain)
  258. return -ENOMEM;
  259. return 0;
  260. }
  261. #else
  262. static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
  263. struct mbigen_device *mgn_chip)
  264. {
  265. return -ENODEV;
  266. }
  267. #endif
  268. static int mbigen_device_probe(struct platform_device *pdev)
  269. {
  270. struct mbigen_device *mgn_chip;
  271. struct resource *res;
  272. int err;
  273. mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
  274. if (!mgn_chip)
  275. return -ENOMEM;
  276. mgn_chip->pdev = pdev;
  277. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  278. if (!res)
  279. return -EINVAL;
  280. mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
  281. resource_size(res));
  282. if (!mgn_chip->base) {
  283. dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
  284. return -ENOMEM;
  285. }
  286. if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
  287. err = mbigen_of_create_domain(pdev, mgn_chip);
  288. else if (ACPI_COMPANION(&pdev->dev))
  289. err = mbigen_acpi_create_domain(pdev, mgn_chip);
  290. else
  291. err = -EINVAL;
  292. if (err) {
  293. dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n");
  294. return err;
  295. }
  296. platform_set_drvdata(pdev, mgn_chip);
  297. return 0;
  298. }
  299. static const struct of_device_id mbigen_of_match[] = {
  300. { .compatible = "hisilicon,mbigen-v2" },
  301. { /* END */ }
  302. };
  303. MODULE_DEVICE_TABLE(of, mbigen_of_match);
  304. static const struct acpi_device_id mbigen_acpi_match[] = {
  305. { "HISI0152", 0 },
  306. {}
  307. };
  308. MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
  309. static struct platform_driver mbigen_platform_driver = {
  310. .driver = {
  311. .name = "Hisilicon MBIGEN-V2",
  312. .of_match_table = mbigen_of_match,
  313. .acpi_match_table = ACPI_PTR(mbigen_acpi_match),
  314. .suppress_bind_attrs = true,
  315. },
  316. .probe = mbigen_device_probe,
  317. };
  318. module_platform_driver(mbigen_platform_driver);
  319. MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
  320. MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
  321. MODULE_LICENSE("GPL");
  322. MODULE_DESCRIPTION("Hisilicon MBI Generator driver");