irq-lpc32xx.c 5.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
  4. */
  5. #define pr_fmt(fmt) "%s: " fmt, __func__
  6. #include <linux/io.h>
  7. #include <linux/irqchip.h>
  8. #include <linux/irqchip/chained_irq.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_irq.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/slab.h>
  13. #include <asm/exception.h>
  14. #define LPC32XX_INTC_MASK 0x00
  15. #define LPC32XX_INTC_RAW 0x04
  16. #define LPC32XX_INTC_STAT 0x08
  17. #define LPC32XX_INTC_POL 0x0C
  18. #define LPC32XX_INTC_TYPE 0x10
  19. #define LPC32XX_INTC_FIQ 0x14
  20. #define NR_LPC32XX_IC_IRQS 32
  21. struct lpc32xx_irq_chip {
  22. void __iomem *base;
  23. struct irq_domain *domain;
  24. struct irq_chip chip;
  25. };
  26. static struct lpc32xx_irq_chip *lpc32xx_mic_irqc;
  27. static inline u32 lpc32xx_ic_read(struct lpc32xx_irq_chip *ic, u32 reg)
  28. {
  29. return readl_relaxed(ic->base + reg);
  30. }
  31. static inline void lpc32xx_ic_write(struct lpc32xx_irq_chip *ic,
  32. u32 reg, u32 val)
  33. {
  34. writel_relaxed(val, ic->base + reg);
  35. }
  36. static void lpc32xx_irq_mask(struct irq_data *d)
  37. {
  38. struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
  39. u32 val, mask = BIT(d->hwirq);
  40. val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) & ~mask;
  41. lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
  42. }
  43. static void lpc32xx_irq_unmask(struct irq_data *d)
  44. {
  45. struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
  46. u32 val, mask = BIT(d->hwirq);
  47. val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) | mask;
  48. lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
  49. }
  50. static void lpc32xx_irq_ack(struct irq_data *d)
  51. {
  52. struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
  53. u32 mask = BIT(d->hwirq);
  54. lpc32xx_ic_write(ic, LPC32XX_INTC_RAW, mask);
  55. }
  56. static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type)
  57. {
  58. struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
  59. u32 val, mask = BIT(d->hwirq);
  60. bool high, edge;
  61. switch (type) {
  62. case IRQ_TYPE_EDGE_RISING:
  63. edge = true;
  64. high = true;
  65. break;
  66. case IRQ_TYPE_EDGE_FALLING:
  67. edge = true;
  68. high = false;
  69. break;
  70. case IRQ_TYPE_LEVEL_HIGH:
  71. edge = false;
  72. high = true;
  73. break;
  74. case IRQ_TYPE_LEVEL_LOW:
  75. edge = false;
  76. high = false;
  77. break;
  78. default:
  79. pr_info("unsupported irq type %d\n", type);
  80. return -EINVAL;
  81. }
  82. irqd_set_trigger_type(d, type);
  83. val = lpc32xx_ic_read(ic, LPC32XX_INTC_POL);
  84. if (high)
  85. val |= mask;
  86. else
  87. val &= ~mask;
  88. lpc32xx_ic_write(ic, LPC32XX_INTC_POL, val);
  89. val = lpc32xx_ic_read(ic, LPC32XX_INTC_TYPE);
  90. if (edge) {
  91. val |= mask;
  92. irq_set_handler_locked(d, handle_edge_irq);
  93. } else {
  94. val &= ~mask;
  95. irq_set_handler_locked(d, handle_level_irq);
  96. }
  97. lpc32xx_ic_write(ic, LPC32XX_INTC_TYPE, val);
  98. return 0;
  99. }
  100. static void __exception_irq_entry lpc32xx_handle_irq(struct pt_regs *regs)
  101. {
  102. struct lpc32xx_irq_chip *ic = lpc32xx_mic_irqc;
  103. u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
  104. while (hwirq) {
  105. irq = __ffs(hwirq);
  106. hwirq &= ~BIT(irq);
  107. handle_domain_irq(lpc32xx_mic_irqc->domain, irq, regs);
  108. }
  109. }
  110. static void lpc32xx_sic_handler(struct irq_desc *desc)
  111. {
  112. struct lpc32xx_irq_chip *ic = irq_desc_get_handler_data(desc);
  113. struct irq_chip *chip = irq_desc_get_chip(desc);
  114. u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
  115. chained_irq_enter(chip, desc);
  116. while (hwirq) {
  117. irq = __ffs(hwirq);
  118. hwirq &= ~BIT(irq);
  119. generic_handle_irq(irq_find_mapping(ic->domain, irq));
  120. }
  121. chained_irq_exit(chip, desc);
  122. }
  123. static int lpc32xx_irq_domain_map(struct irq_domain *id, unsigned int virq,
  124. irq_hw_number_t hw)
  125. {
  126. struct lpc32xx_irq_chip *ic = id->host_data;
  127. irq_set_chip_data(virq, ic);
  128. irq_set_chip_and_handler(virq, &ic->chip, handle_level_irq);
  129. irq_set_status_flags(virq, IRQ_LEVEL);
  130. irq_set_noprobe(virq);
  131. return 0;
  132. }
  133. static void lpc32xx_irq_domain_unmap(struct irq_domain *id, unsigned int virq)
  134. {
  135. irq_set_chip_and_handler(virq, NULL, NULL);
  136. }
  137. static const struct irq_domain_ops lpc32xx_irq_domain_ops = {
  138. .map = lpc32xx_irq_domain_map,
  139. .unmap = lpc32xx_irq_domain_unmap,
  140. .xlate = irq_domain_xlate_twocell,
  141. };
  142. static int __init lpc32xx_of_ic_init(struct device_node *node,
  143. struct device_node *parent)
  144. {
  145. struct lpc32xx_irq_chip *irqc;
  146. bool is_mic = of_device_is_compatible(node, "nxp,lpc3220-mic");
  147. const __be32 *reg = of_get_property(node, "reg", NULL);
  148. u32 parent_irq, i, addr = reg ? be32_to_cpu(*reg) : 0;
  149. irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
  150. if (!irqc)
  151. return -ENOMEM;
  152. irqc->base = of_iomap(node, 0);
  153. if (!irqc->base) {
  154. pr_err("%pOF: unable to map registers\n", node);
  155. kfree(irqc);
  156. return -EINVAL;
  157. }
  158. irqc->chip.irq_ack = lpc32xx_irq_ack;
  159. irqc->chip.irq_mask = lpc32xx_irq_mask;
  160. irqc->chip.irq_unmask = lpc32xx_irq_unmask;
  161. irqc->chip.irq_set_type = lpc32xx_irq_set_type;
  162. if (is_mic)
  163. irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.mic", addr);
  164. else
  165. irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.sic", addr);
  166. irqc->domain = irq_domain_add_linear(node, NR_LPC32XX_IC_IRQS,
  167. &lpc32xx_irq_domain_ops, irqc);
  168. if (!irqc->domain) {
  169. pr_err("unable to add irq domain\n");
  170. iounmap(irqc->base);
  171. kfree(irqc->chip.name);
  172. kfree(irqc);
  173. return -ENODEV;
  174. }
  175. if (is_mic) {
  176. lpc32xx_mic_irqc = irqc;
  177. set_handle_irq(lpc32xx_handle_irq);
  178. } else {
  179. for (i = 0; i < of_irq_count(node); i++) {
  180. parent_irq = irq_of_parse_and_map(node, i);
  181. if (parent_irq)
  182. irq_set_chained_handler_and_data(parent_irq,
  183. lpc32xx_sic_handler, irqc);
  184. }
  185. }
  186. lpc32xx_ic_write(irqc, LPC32XX_INTC_MASK, 0x00);
  187. lpc32xx_ic_write(irqc, LPC32XX_INTC_POL, 0x00);
  188. lpc32xx_ic_write(irqc, LPC32XX_INTC_TYPE, 0x00);
  189. return 0;
  190. }
  191. IRQCHIP_DECLARE(nxp_lpc32xx_mic, "nxp,lpc3220-mic", lpc32xx_of_ic_init);
  192. IRQCHIP_DECLARE(nxp_lpc32xx_sic, "nxp,lpc3220-sic", lpc32xx_of_ic_init);