irq-ingenic-tcu.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * JZ47xx SoCs TCU IRQ driver
  4. * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/irqchip.h>
  9. #include <linux/irqchip/chained_irq.h>
  10. #include <linux/mfd/ingenic-tcu.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/regmap.h>
  14. struct ingenic_tcu {
  15. struct regmap *map;
  16. struct clk *clk;
  17. struct irq_domain *domain;
  18. unsigned int nb_parent_irqs;
  19. u32 parent_irqs[3];
  20. };
  21. static void ingenic_tcu_intc_cascade(struct irq_desc *desc)
  22. {
  23. struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
  24. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  25. struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
  26. struct regmap *map = gc->private;
  27. uint32_t irq_reg, irq_mask;
  28. unsigned int i;
  29. regmap_read(map, TCU_REG_TFR, &irq_reg);
  30. regmap_read(map, TCU_REG_TMR, &irq_mask);
  31. chained_irq_enter(irq_chip, desc);
  32. irq_reg &= ~irq_mask;
  33. for_each_set_bit(i, (unsigned long *)&irq_reg, 32)
  34. generic_handle_irq(irq_linear_revmap(domain, i));
  35. chained_irq_exit(irq_chip, desc);
  36. }
  37. static void ingenic_tcu_gc_unmask_enable_reg(struct irq_data *d)
  38. {
  39. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  40. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  41. struct regmap *map = gc->private;
  42. u32 mask = d->mask;
  43. irq_gc_lock(gc);
  44. regmap_write(map, ct->regs.ack, mask);
  45. regmap_write(map, ct->regs.enable, mask);
  46. *ct->mask_cache |= mask;
  47. irq_gc_unlock(gc);
  48. }
  49. static void ingenic_tcu_gc_mask_disable_reg(struct irq_data *d)
  50. {
  51. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  52. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  53. struct regmap *map = gc->private;
  54. u32 mask = d->mask;
  55. irq_gc_lock(gc);
  56. regmap_write(map, ct->regs.disable, mask);
  57. *ct->mask_cache &= ~mask;
  58. irq_gc_unlock(gc);
  59. }
  60. static void ingenic_tcu_gc_mask_disable_reg_and_ack(struct irq_data *d)
  61. {
  62. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  63. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  64. struct regmap *map = gc->private;
  65. u32 mask = d->mask;
  66. irq_gc_lock(gc);
  67. regmap_write(map, ct->regs.ack, mask);
  68. regmap_write(map, ct->regs.disable, mask);
  69. irq_gc_unlock(gc);
  70. }
  71. static int __init ingenic_tcu_irq_init(struct device_node *np,
  72. struct device_node *parent)
  73. {
  74. struct irq_chip_generic *gc;
  75. struct irq_chip_type *ct;
  76. struct ingenic_tcu *tcu;
  77. struct regmap *map;
  78. unsigned int i;
  79. int ret, irqs;
  80. map = device_node_to_regmap(np);
  81. if (IS_ERR(map))
  82. return PTR_ERR(map);
  83. tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
  84. if (!tcu)
  85. return -ENOMEM;
  86. tcu->map = map;
  87. irqs = of_property_count_elems_of_size(np, "interrupts", sizeof(u32));
  88. if (irqs < 0 || irqs > ARRAY_SIZE(tcu->parent_irqs)) {
  89. pr_crit("%s: Invalid 'interrupts' property\n", __func__);
  90. ret = -EINVAL;
  91. goto err_free_tcu;
  92. }
  93. tcu->nb_parent_irqs = irqs;
  94. tcu->domain = irq_domain_add_linear(np, 32, &irq_generic_chip_ops,
  95. NULL);
  96. if (!tcu->domain) {
  97. ret = -ENOMEM;
  98. goto err_free_tcu;
  99. }
  100. ret = irq_alloc_domain_generic_chips(tcu->domain, 32, 1, "TCU",
  101. handle_level_irq, 0,
  102. IRQ_NOPROBE | IRQ_LEVEL, 0);
  103. if (ret) {
  104. pr_crit("%s: Invalid 'interrupts' property\n", __func__);
  105. goto out_domain_remove;
  106. }
  107. gc = irq_get_domain_generic_chip(tcu->domain, 0);
  108. ct = gc->chip_types;
  109. gc->wake_enabled = IRQ_MSK(32);
  110. gc->private = tcu->map;
  111. ct->regs.disable = TCU_REG_TMSR;
  112. ct->regs.enable = TCU_REG_TMCR;
  113. ct->regs.ack = TCU_REG_TFCR;
  114. ct->chip.irq_unmask = ingenic_tcu_gc_unmask_enable_reg;
  115. ct->chip.irq_mask = ingenic_tcu_gc_mask_disable_reg;
  116. ct->chip.irq_mask_ack = ingenic_tcu_gc_mask_disable_reg_and_ack;
  117. ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
  118. /* Mask all IRQs by default */
  119. regmap_write(tcu->map, TCU_REG_TMSR, IRQ_MSK(32));
  120. /*
  121. * On JZ4740, timer 0 and timer 1 have their own interrupt line;
  122. * timers 2-7 share one interrupt.
  123. * On SoCs >= JZ4770, timer 5 has its own interrupt line;
  124. * timers 0-4 and 6-7 share one single interrupt.
  125. *
  126. * To keep things simple, we just register the same handler to
  127. * all parent interrupts. The handler will properly detect which
  128. * channel fired the interrupt.
  129. */
  130. for (i = 0; i < irqs; i++) {
  131. tcu->parent_irqs[i] = irq_of_parse_and_map(np, i);
  132. if (!tcu->parent_irqs[i]) {
  133. ret = -EINVAL;
  134. goto out_unmap_irqs;
  135. }
  136. irq_set_chained_handler_and_data(tcu->parent_irqs[i],
  137. ingenic_tcu_intc_cascade,
  138. tcu->domain);
  139. }
  140. return 0;
  141. out_unmap_irqs:
  142. for (; i > 0; i--)
  143. irq_dispose_mapping(tcu->parent_irqs[i - 1]);
  144. out_domain_remove:
  145. irq_domain_remove(tcu->domain);
  146. err_free_tcu:
  147. kfree(tcu);
  148. return ret;
  149. }
  150. IRQCHIP_DECLARE(jz4740_tcu_irq, "ingenic,jz4740-tcu", ingenic_tcu_irq_init);
  151. IRQCHIP_DECLARE(jz4725b_tcu_irq, "ingenic,jz4725b-tcu", ingenic_tcu_irq_init);
  152. IRQCHIP_DECLARE(jz4760_tcu_irq, "ingenic,jz4760-tcu", ingenic_tcu_irq_init);
  153. IRQCHIP_DECLARE(jz4770_tcu_irq, "ingenic,jz4770-tcu", ingenic_tcu_irq_init);
  154. IRQCHIP_DECLARE(x1000_tcu_irq, "ingenic,x1000-tcu", ingenic_tcu_irq_init);