irq-imx-irqsteer.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/irq.h>
  9. #include <linux/irqchip/chained_irq.h>
  10. #include <linux/irqdomain.h>
  11. #include <linux/kernel.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/spinlock.h>
  15. #define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
  16. #define CHANCTRL 0x0
  17. #define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
  18. #define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
  19. #define CHANSTATUS(n, t) (CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
  20. #define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4)
  21. #define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8)
  22. #define CHAN_MAX_OUTPUT_INT 0x8
  23. struct irqsteer_data {
  24. void __iomem *regs;
  25. struct clk *ipg_clk;
  26. int irq[CHAN_MAX_OUTPUT_INT];
  27. int irq_count;
  28. raw_spinlock_t lock;
  29. int reg_num;
  30. int channel;
  31. struct irq_domain *domain;
  32. u32 *saved_reg;
  33. };
  34. static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
  35. unsigned long irqnum)
  36. {
  37. return (data->reg_num - irqnum / 32 - 1);
  38. }
  39. static void imx_irqsteer_irq_unmask(struct irq_data *d)
  40. {
  41. struct irqsteer_data *data = d->chip_data;
  42. int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
  43. unsigned long flags;
  44. u32 val;
  45. raw_spin_lock_irqsave(&data->lock, flags);
  46. val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
  47. val |= BIT(d->hwirq % 32);
  48. writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
  49. raw_spin_unlock_irqrestore(&data->lock, flags);
  50. }
  51. static void imx_irqsteer_irq_mask(struct irq_data *d)
  52. {
  53. struct irqsteer_data *data = d->chip_data;
  54. int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
  55. unsigned long flags;
  56. u32 val;
  57. raw_spin_lock_irqsave(&data->lock, flags);
  58. val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
  59. val &= ~BIT(d->hwirq % 32);
  60. writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
  61. raw_spin_unlock_irqrestore(&data->lock, flags);
  62. }
  63. static struct irq_chip imx_irqsteer_irq_chip = {
  64. .name = "irqsteer",
  65. .irq_mask = imx_irqsteer_irq_mask,
  66. .irq_unmask = imx_irqsteer_irq_unmask,
  67. };
  68. static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
  69. irq_hw_number_t hwirq)
  70. {
  71. irq_set_status_flags(irq, IRQ_LEVEL);
  72. irq_set_chip_data(irq, h->host_data);
  73. irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq);
  74. return 0;
  75. }
  76. static const struct irq_domain_ops imx_irqsteer_domain_ops = {
  77. .map = imx_irqsteer_irq_map,
  78. .xlate = irq_domain_xlate_onecell,
  79. };
  80. static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
  81. {
  82. int i;
  83. for (i = 0; i < data->irq_count; i++) {
  84. if (data->irq[i] == irq)
  85. return i * 64;
  86. }
  87. return -EINVAL;
  88. }
  89. static void imx_irqsteer_irq_handler(struct irq_desc *desc)
  90. {
  91. struct irqsteer_data *data = irq_desc_get_handler_data(desc);
  92. int hwirq;
  93. int irq, i;
  94. chained_irq_enter(irq_desc_get_chip(desc), desc);
  95. irq = irq_desc_get_irq(desc);
  96. hwirq = imx_irqsteer_get_hwirq_base(data, irq);
  97. if (hwirq < 0) {
  98. pr_warn("%s: unable to get hwirq base for irq %d\n",
  99. __func__, irq);
  100. return;
  101. }
  102. for (i = 0; i < 2; i++, hwirq += 32) {
  103. int idx = imx_irqsteer_get_reg_index(data, hwirq);
  104. unsigned long irqmap;
  105. int pos, virq;
  106. if (hwirq >= data->reg_num * 32)
  107. break;
  108. irqmap = readl_relaxed(data->regs +
  109. CHANSTATUS(idx, data->reg_num));
  110. for_each_set_bit(pos, &irqmap, 32) {
  111. virq = irq_find_mapping(data->domain, pos + hwirq);
  112. if (virq)
  113. generic_handle_irq(virq);
  114. }
  115. }
  116. chained_irq_exit(irq_desc_get_chip(desc), desc);
  117. }
  118. static int imx_irqsteer_probe(struct platform_device *pdev)
  119. {
  120. struct device_node *np = pdev->dev.of_node;
  121. struct irqsteer_data *data;
  122. u32 irqs_num;
  123. int i, ret;
  124. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  125. if (!data)
  126. return -ENOMEM;
  127. data->regs = devm_platform_ioremap_resource(pdev, 0);
  128. if (IS_ERR(data->regs)) {
  129. dev_err(&pdev->dev, "failed to initialize reg\n");
  130. return PTR_ERR(data->regs);
  131. }
  132. data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
  133. if (IS_ERR(data->ipg_clk))
  134. return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk),
  135. "failed to get ipg clk\n");
  136. raw_spin_lock_init(&data->lock);
  137. ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
  138. if (ret)
  139. return ret;
  140. ret = of_property_read_u32(np, "fsl,channel", &data->channel);
  141. if (ret)
  142. return ret;
  143. /*
  144. * There is one output irq for each group of 64 inputs.
  145. * One register bit map can represent 32 input interrupts.
  146. */
  147. data->irq_count = DIV_ROUND_UP(irqs_num, 64);
  148. data->reg_num = irqs_num / 32;
  149. if (IS_ENABLED(CONFIG_PM_SLEEP)) {
  150. data->saved_reg = devm_kzalloc(&pdev->dev,
  151. sizeof(u32) * data->reg_num,
  152. GFP_KERNEL);
  153. if (!data->saved_reg)
  154. return -ENOMEM;
  155. }
  156. ret = clk_prepare_enable(data->ipg_clk);
  157. if (ret) {
  158. dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
  159. return ret;
  160. }
  161. /* steer all IRQs into configured channel */
  162. writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
  163. data->domain = irq_domain_add_linear(np, data->reg_num * 32,
  164. &imx_irqsteer_domain_ops, data);
  165. if (!data->domain) {
  166. dev_err(&pdev->dev, "failed to create IRQ domain\n");
  167. ret = -ENOMEM;
  168. goto out;
  169. }
  170. if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
  171. ret = -EINVAL;
  172. goto out;
  173. }
  174. for (i = 0; i < data->irq_count; i++) {
  175. data->irq[i] = irq_of_parse_and_map(np, i);
  176. if (!data->irq[i]) {
  177. ret = -EINVAL;
  178. goto out;
  179. }
  180. irq_set_chained_handler_and_data(data->irq[i],
  181. imx_irqsteer_irq_handler,
  182. data);
  183. }
  184. platform_set_drvdata(pdev, data);
  185. return 0;
  186. out:
  187. clk_disable_unprepare(data->ipg_clk);
  188. return ret;
  189. }
  190. static int imx_irqsteer_remove(struct platform_device *pdev)
  191. {
  192. struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
  193. int i;
  194. for (i = 0; i < irqsteer_data->irq_count; i++)
  195. irq_set_chained_handler_and_data(irqsteer_data->irq[i],
  196. NULL, NULL);
  197. irq_domain_remove(irqsteer_data->domain);
  198. clk_disable_unprepare(irqsteer_data->ipg_clk);
  199. return 0;
  200. }
  201. #ifdef CONFIG_PM_SLEEP
  202. static void imx_irqsteer_save_regs(struct irqsteer_data *data)
  203. {
  204. int i;
  205. for (i = 0; i < data->reg_num; i++)
  206. data->saved_reg[i] = readl_relaxed(data->regs +
  207. CHANMASK(i, data->reg_num));
  208. }
  209. static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
  210. {
  211. int i;
  212. writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
  213. for (i = 0; i < data->reg_num; i++)
  214. writel_relaxed(data->saved_reg[i],
  215. data->regs + CHANMASK(i, data->reg_num));
  216. }
  217. static int imx_irqsteer_suspend(struct device *dev)
  218. {
  219. struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
  220. imx_irqsteer_save_regs(irqsteer_data);
  221. clk_disable_unprepare(irqsteer_data->ipg_clk);
  222. return 0;
  223. }
  224. static int imx_irqsteer_resume(struct device *dev)
  225. {
  226. struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
  227. int ret;
  228. ret = clk_prepare_enable(irqsteer_data->ipg_clk);
  229. if (ret) {
  230. dev_err(dev, "failed to enable ipg clk: %d\n", ret);
  231. return ret;
  232. }
  233. imx_irqsteer_restore_regs(irqsteer_data);
  234. return 0;
  235. }
  236. #endif
  237. static const struct dev_pm_ops imx_irqsteer_pm_ops = {
  238. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_irqsteer_suspend, imx_irqsteer_resume)
  239. };
  240. static const struct of_device_id imx_irqsteer_dt_ids[] = {
  241. { .compatible = "fsl,imx-irqsteer", },
  242. {},
  243. };
  244. static struct platform_driver imx_irqsteer_driver = {
  245. .driver = {
  246. .name = "imx-irqsteer",
  247. .of_match_table = imx_irqsteer_dt_ids,
  248. .pm = &imx_irqsteer_pm_ops,
  249. },
  250. .probe = imx_irqsteer_probe,
  251. .remove = imx_irqsteer_remove,
  252. };
  253. builtin_platform_driver(imx_irqsteer_driver);