irq-imx-gpcv2.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <linux/of_address.h>
  6. #include <linux/of_irq.h>
  7. #include <linux/slab.h>
  8. #include <linux/irqchip.h>
  9. #include <linux/syscore_ops.h>
  10. #define IMR_NUM 4
  11. #define GPC_MAX_IRQS (IMR_NUM * 32)
  12. #define GPC_IMR1_CORE0 0x30
  13. #define GPC_IMR1_CORE1 0x40
  14. #define GPC_IMR1_CORE2 0x1c0
  15. #define GPC_IMR1_CORE3 0x1d0
  16. struct gpcv2_irqchip_data {
  17. struct raw_spinlock rlock;
  18. void __iomem *gpc_base;
  19. u32 wakeup_sources[IMR_NUM];
  20. u32 saved_irq_mask[IMR_NUM];
  21. u32 cpu2wakeup;
  22. };
  23. static struct gpcv2_irqchip_data *imx_gpcv2_instance;
  24. static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
  25. {
  26. return cd->gpc_base + cd->cpu2wakeup + i * 4;
  27. }
  28. static int gpcv2_wakeup_source_save(void)
  29. {
  30. struct gpcv2_irqchip_data *cd;
  31. void __iomem *reg;
  32. int i;
  33. cd = imx_gpcv2_instance;
  34. if (!cd)
  35. return 0;
  36. for (i = 0; i < IMR_NUM; i++) {
  37. reg = gpcv2_idx_to_reg(cd, i);
  38. cd->saved_irq_mask[i] = readl_relaxed(reg);
  39. writel_relaxed(cd->wakeup_sources[i], reg);
  40. }
  41. return 0;
  42. }
  43. static void gpcv2_wakeup_source_restore(void)
  44. {
  45. struct gpcv2_irqchip_data *cd;
  46. int i;
  47. cd = imx_gpcv2_instance;
  48. if (!cd)
  49. return;
  50. for (i = 0; i < IMR_NUM; i++)
  51. writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
  52. }
  53. static struct syscore_ops imx_gpcv2_syscore_ops = {
  54. .suspend = gpcv2_wakeup_source_save,
  55. .resume = gpcv2_wakeup_source_restore,
  56. };
  57. static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
  58. {
  59. struct gpcv2_irqchip_data *cd = d->chip_data;
  60. unsigned int idx = d->hwirq / 32;
  61. unsigned long flags;
  62. u32 mask, val;
  63. raw_spin_lock_irqsave(&cd->rlock, flags);
  64. mask = BIT(d->hwirq % 32);
  65. val = cd->wakeup_sources[idx];
  66. cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
  67. raw_spin_unlock_irqrestore(&cd->rlock, flags);
  68. /*
  69. * Do *not* call into the parent, as the GIC doesn't have any
  70. * wake-up facility...
  71. */
  72. return 0;
  73. }
  74. static void imx_gpcv2_irq_unmask(struct irq_data *d)
  75. {
  76. struct gpcv2_irqchip_data *cd = d->chip_data;
  77. void __iomem *reg;
  78. u32 val;
  79. raw_spin_lock(&cd->rlock);
  80. reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
  81. val = readl_relaxed(reg);
  82. val &= ~BIT(d->hwirq % 32);
  83. writel_relaxed(val, reg);
  84. raw_spin_unlock(&cd->rlock);
  85. irq_chip_unmask_parent(d);
  86. }
  87. static void imx_gpcv2_irq_mask(struct irq_data *d)
  88. {
  89. struct gpcv2_irqchip_data *cd = d->chip_data;
  90. void __iomem *reg;
  91. u32 val;
  92. raw_spin_lock(&cd->rlock);
  93. reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
  94. val = readl_relaxed(reg);
  95. val |= BIT(d->hwirq % 32);
  96. writel_relaxed(val, reg);
  97. raw_spin_unlock(&cd->rlock);
  98. irq_chip_mask_parent(d);
  99. }
  100. static struct irq_chip gpcv2_irqchip_data_chip = {
  101. .name = "GPCv2",
  102. .irq_eoi = irq_chip_eoi_parent,
  103. .irq_mask = imx_gpcv2_irq_mask,
  104. .irq_unmask = imx_gpcv2_irq_unmask,
  105. .irq_set_wake = imx_gpcv2_irq_set_wake,
  106. .irq_retrigger = irq_chip_retrigger_hierarchy,
  107. .irq_set_type = irq_chip_set_type_parent,
  108. #ifdef CONFIG_SMP
  109. .irq_set_affinity = irq_chip_set_affinity_parent,
  110. #endif
  111. };
  112. static int imx_gpcv2_domain_translate(struct irq_domain *d,
  113. struct irq_fwspec *fwspec,
  114. unsigned long *hwirq,
  115. unsigned int *type)
  116. {
  117. if (is_of_node(fwspec->fwnode)) {
  118. if (fwspec->param_count != 3)
  119. return -EINVAL;
  120. /* No PPI should point to this domain */
  121. if (fwspec->param[0] != 0)
  122. return -EINVAL;
  123. *hwirq = fwspec->param[1];
  124. *type = fwspec->param[2];
  125. return 0;
  126. }
  127. return -EINVAL;
  128. }
  129. static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
  130. unsigned int irq, unsigned int nr_irqs,
  131. void *data)
  132. {
  133. struct irq_fwspec *fwspec = data;
  134. struct irq_fwspec parent_fwspec;
  135. irq_hw_number_t hwirq;
  136. unsigned int type;
  137. int err;
  138. int i;
  139. err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq, &type);
  140. if (err)
  141. return err;
  142. if (hwirq >= GPC_MAX_IRQS)
  143. return -EINVAL;
  144. for (i = 0; i < nr_irqs; i++) {
  145. irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
  146. &gpcv2_irqchip_data_chip, domain->host_data);
  147. }
  148. parent_fwspec = *fwspec;
  149. parent_fwspec.fwnode = domain->parent->fwnode;
  150. return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
  151. &parent_fwspec);
  152. }
  153. static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
  154. .translate = imx_gpcv2_domain_translate,
  155. .alloc = imx_gpcv2_domain_alloc,
  156. .free = irq_domain_free_irqs_common,
  157. };
  158. static const struct of_device_id gpcv2_of_match[] = {
  159. { .compatible = "fsl,imx7d-gpc", .data = (const void *) 2 },
  160. { .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
  161. { /* END */ }
  162. };
  163. static int __init imx_gpcv2_irqchip_init(struct device_node *node,
  164. struct device_node *parent)
  165. {
  166. struct irq_domain *parent_domain, *domain;
  167. struct gpcv2_irqchip_data *cd;
  168. const struct of_device_id *id;
  169. unsigned long core_num;
  170. int i;
  171. if (!parent) {
  172. pr_err("%pOF: no parent, giving up\n", node);
  173. return -ENODEV;
  174. }
  175. id = of_match_node(gpcv2_of_match, node);
  176. if (!id) {
  177. pr_err("%pOF: unknown compatibility string\n", node);
  178. return -ENODEV;
  179. }
  180. core_num = (unsigned long)id->data;
  181. parent_domain = irq_find_host(parent);
  182. if (!parent_domain) {
  183. pr_err("%pOF: unable to get parent domain\n", node);
  184. return -ENXIO;
  185. }
  186. cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
  187. if (!cd) {
  188. pr_err("%pOF: kzalloc failed!\n", node);
  189. return -ENOMEM;
  190. }
  191. raw_spin_lock_init(&cd->rlock);
  192. cd->gpc_base = of_iomap(node, 0);
  193. if (!cd->gpc_base) {
  194. pr_err("%pOF: unable to map gpc registers\n", node);
  195. kfree(cd);
  196. return -ENOMEM;
  197. }
  198. domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
  199. node, &gpcv2_irqchip_data_domain_ops, cd);
  200. if (!domain) {
  201. iounmap(cd->gpc_base);
  202. kfree(cd);
  203. return -ENOMEM;
  204. }
  205. irq_set_default_host(domain);
  206. /* Initially mask all interrupts */
  207. for (i = 0; i < IMR_NUM; i++) {
  208. void __iomem *reg = cd->gpc_base + i * 4;
  209. switch (core_num) {
  210. case 4:
  211. writel_relaxed(~0, reg + GPC_IMR1_CORE2);
  212. writel_relaxed(~0, reg + GPC_IMR1_CORE3);
  213. fallthrough;
  214. case 2:
  215. writel_relaxed(~0, reg + GPC_IMR1_CORE0);
  216. writel_relaxed(~0, reg + GPC_IMR1_CORE1);
  217. }
  218. cd->wakeup_sources[i] = ~0;
  219. }
  220. /* Let CORE0 as the default CPU to wake up by GPC */
  221. cd->cpu2wakeup = GPC_IMR1_CORE0;
  222. /*
  223. * Due to hardware design failure, need to make sure GPR
  224. * interrupt(#32) is unmasked during RUN mode to avoid entering
  225. * DSM by mistake.
  226. */
  227. writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
  228. imx_gpcv2_instance = cd;
  229. register_syscore_ops(&imx_gpcv2_syscore_ops);
  230. /*
  231. * Clear the OF_POPULATED flag set in of_irq_init so that
  232. * later the GPC power domain driver will not be skipped.
  233. */
  234. of_node_clear_flag(node, OF_POPULATED);
  235. return 0;
  236. }
  237. IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
  238. IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);