irq-i8259.c 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Code to handle x86 style IRQs plus some generic interrupt stuff.
  7. *
  8. * Copyright (C) 1992 Linus Torvalds
  9. * Copyright (C) 1994 - 2000 Ralf Baechle
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/init.h>
  13. #include <linux/ioport.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/kernel.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/syscore_ops.h>
  21. #include <linux/irq.h>
  22. #include <asm/i8259.h>
  23. #include <asm/io.h>
  24. /*
  25. * This is the 'legacy' 8259A Programmable Interrupt Controller,
  26. * present in the majority of PC/AT boxes.
  27. * plus some generic x86 specific things if generic specifics makes
  28. * any sense at all.
  29. * this file should become arch/i386/kernel/irq.c when the old irq.c
  30. * moves to arch independent land
  31. */
  32. static int i8259A_auto_eoi = -1;
  33. DEFINE_RAW_SPINLOCK(i8259A_lock);
  34. static void disable_8259A_irq(struct irq_data *d);
  35. static void enable_8259A_irq(struct irq_data *d);
  36. static void mask_and_ack_8259A(struct irq_data *d);
  37. static void init_8259A(int auto_eoi);
  38. static int (*i8259_poll)(void) = i8259_irq;
  39. static struct irq_chip i8259A_chip = {
  40. .name = "XT-PIC",
  41. .irq_mask = disable_8259A_irq,
  42. .irq_disable = disable_8259A_irq,
  43. .irq_unmask = enable_8259A_irq,
  44. .irq_mask_ack = mask_and_ack_8259A,
  45. };
  46. /*
  47. * 8259A PIC functions to handle ISA devices:
  48. */
  49. void i8259_set_poll(int (*poll)(void))
  50. {
  51. i8259_poll = poll;
  52. }
  53. /*
  54. * This contains the irq mask for both 8259A irq controllers,
  55. */
  56. static unsigned int cached_irq_mask = 0xffff;
  57. #define cached_master_mask (cached_irq_mask)
  58. #define cached_slave_mask (cached_irq_mask >> 8)
  59. static void disable_8259A_irq(struct irq_data *d)
  60. {
  61. unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
  62. unsigned long flags;
  63. mask = 1 << irq;
  64. raw_spin_lock_irqsave(&i8259A_lock, flags);
  65. cached_irq_mask |= mask;
  66. if (irq & 8)
  67. outb(cached_slave_mask, PIC_SLAVE_IMR);
  68. else
  69. outb(cached_master_mask, PIC_MASTER_IMR);
  70. raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  71. }
  72. static void enable_8259A_irq(struct irq_data *d)
  73. {
  74. unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
  75. unsigned long flags;
  76. mask = ~(1 << irq);
  77. raw_spin_lock_irqsave(&i8259A_lock, flags);
  78. cached_irq_mask &= mask;
  79. if (irq & 8)
  80. outb(cached_slave_mask, PIC_SLAVE_IMR);
  81. else
  82. outb(cached_master_mask, PIC_MASTER_IMR);
  83. raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  84. }
  85. void make_8259A_irq(unsigned int irq)
  86. {
  87. disable_irq_nosync(irq);
  88. irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
  89. enable_irq(irq);
  90. }
  91. /*
  92. * This function assumes to be called rarely. Switching between
  93. * 8259A registers is slow.
  94. * This has to be protected by the irq controller spinlock
  95. * before being called.
  96. */
  97. static inline int i8259A_irq_real(unsigned int irq)
  98. {
  99. int value;
  100. int irqmask = 1 << irq;
  101. if (irq < 8) {
  102. outb(0x0B, PIC_MASTER_CMD); /* ISR register */
  103. value = inb(PIC_MASTER_CMD) & irqmask;
  104. outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
  105. return value;
  106. }
  107. outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
  108. value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
  109. outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
  110. return value;
  111. }
  112. /*
  113. * Careful! The 8259A is a fragile beast, it pretty
  114. * much _has_ to be done exactly like this (mask it
  115. * first, _then_ send the EOI, and the order of EOI
  116. * to the two 8259s is important!
  117. */
  118. static void mask_and_ack_8259A(struct irq_data *d)
  119. {
  120. unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
  121. unsigned long flags;
  122. irqmask = 1 << irq;
  123. raw_spin_lock_irqsave(&i8259A_lock, flags);
  124. /*
  125. * Lightweight spurious IRQ detection. We do not want
  126. * to overdo spurious IRQ handling - it's usually a sign
  127. * of hardware problems, so we only do the checks we can
  128. * do without slowing down good hardware unnecessarily.
  129. *
  130. * Note that IRQ7 and IRQ15 (the two spurious IRQs
  131. * usually resulting from the 8259A-1|2 PICs) occur
  132. * even if the IRQ is masked in the 8259A. Thus we
  133. * can check spurious 8259A IRQs without doing the
  134. * quite slow i8259A_irq_real() call for every IRQ.
  135. * This does not cover 100% of spurious interrupts,
  136. * but should be enough to warn the user that there
  137. * is something bad going on ...
  138. */
  139. if (cached_irq_mask & irqmask)
  140. goto spurious_8259A_irq;
  141. cached_irq_mask |= irqmask;
  142. handle_real_irq:
  143. if (irq & 8) {
  144. inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
  145. outb(cached_slave_mask, PIC_SLAVE_IMR);
  146. outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
  147. outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
  148. } else {
  149. inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
  150. outb(cached_master_mask, PIC_MASTER_IMR);
  151. outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
  152. }
  153. raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  154. return;
  155. spurious_8259A_irq:
  156. /*
  157. * this is the slow path - should happen rarely.
  158. */
  159. if (i8259A_irq_real(irq))
  160. /*
  161. * oops, the IRQ _is_ in service according to the
  162. * 8259A - not spurious, go handle it.
  163. */
  164. goto handle_real_irq;
  165. {
  166. static int spurious_irq_mask;
  167. /*
  168. * At this point we can be sure the IRQ is spurious,
  169. * lets ACK and report it. [once per IRQ]
  170. */
  171. if (!(spurious_irq_mask & irqmask)) {
  172. printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
  173. spurious_irq_mask |= irqmask;
  174. }
  175. atomic_inc(&irq_err_count);
  176. /*
  177. * Theoretically we do not have to handle this IRQ,
  178. * but in Linux this does not cause problems and is
  179. * simpler for us.
  180. */
  181. goto handle_real_irq;
  182. }
  183. }
  184. static void i8259A_resume(void)
  185. {
  186. if (i8259A_auto_eoi >= 0)
  187. init_8259A(i8259A_auto_eoi);
  188. }
  189. static void i8259A_shutdown(void)
  190. {
  191. /* Put the i8259A into a quiescent state that
  192. * the kernel initialization code can get it
  193. * out of.
  194. */
  195. if (i8259A_auto_eoi >= 0) {
  196. outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
  197. outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
  198. }
  199. }
  200. static struct syscore_ops i8259_syscore_ops = {
  201. .resume = i8259A_resume,
  202. .shutdown = i8259A_shutdown,
  203. };
  204. static void init_8259A(int auto_eoi)
  205. {
  206. unsigned long flags;
  207. i8259A_auto_eoi = auto_eoi;
  208. raw_spin_lock_irqsave(&i8259A_lock, flags);
  209. outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
  210. outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
  211. /*
  212. * outb_p - this has to work on a wide range of PC hardware.
  213. */
  214. outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
  215. outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
  216. outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
  217. if (auto_eoi) /* master does Auto EOI */
  218. outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
  219. else /* master expects normal EOI */
  220. outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
  221. outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
  222. outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
  223. outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
  224. outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
  225. if (auto_eoi)
  226. /*
  227. * In AEOI mode we just have to mask the interrupt
  228. * when acking.
  229. */
  230. i8259A_chip.irq_mask_ack = disable_8259A_irq;
  231. else
  232. i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
  233. udelay(100); /* wait for 8259A to initialize */
  234. outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
  235. outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
  236. raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  237. }
  238. static struct resource pic1_io_resource = {
  239. .name = "pic1",
  240. .start = PIC_MASTER_CMD,
  241. .end = PIC_MASTER_IMR,
  242. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  243. };
  244. static struct resource pic2_io_resource = {
  245. .name = "pic2",
  246. .start = PIC_SLAVE_CMD,
  247. .end = PIC_SLAVE_IMR,
  248. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  249. };
  250. static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq,
  251. irq_hw_number_t hw)
  252. {
  253. irq_set_chip_and_handler(virq, &i8259A_chip, handle_level_irq);
  254. irq_set_probe(virq);
  255. return 0;
  256. }
  257. static const struct irq_domain_ops i8259A_ops = {
  258. .map = i8259A_irq_domain_map,
  259. .xlate = irq_domain_xlate_onecell,
  260. };
  261. /*
  262. * On systems with i8259-style interrupt controllers we assume for
  263. * driver compatibility reasons interrupts 0 - 15 to be the i8259
  264. * interrupts even if the hardware uses a different interrupt numbering.
  265. */
  266. struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
  267. {
  268. /*
  269. * PIC_CASCADE_IR is cascade interrupt to second interrupt controller
  270. */
  271. int irq = I8259A_IRQ_BASE + PIC_CASCADE_IR;
  272. struct irq_domain *domain;
  273. insert_resource(&ioport_resource, &pic1_io_resource);
  274. insert_resource(&ioport_resource, &pic2_io_resource);
  275. init_8259A(0);
  276. domain = irq_domain_add_legacy(node, 16, I8259A_IRQ_BASE, 0,
  277. &i8259A_ops, NULL);
  278. if (!domain)
  279. panic("Failed to add i8259 IRQ domain");
  280. if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))
  281. pr_err("Failed to register cascade interrupt\n");
  282. register_syscore_ops(&i8259_syscore_ops);
  283. return domain;
  284. }
  285. void __init init_i8259_irqs(void)
  286. {
  287. __init_i8259_irqs(NULL);
  288. }
  289. static void i8259_irq_dispatch(struct irq_desc *desc)
  290. {
  291. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  292. int hwirq = i8259_poll();
  293. unsigned int irq;
  294. if (hwirq < 0)
  295. return;
  296. irq = irq_linear_revmap(domain, hwirq);
  297. generic_handle_irq(irq);
  298. }
  299. int __init i8259_of_init(struct device_node *node, struct device_node *parent)
  300. {
  301. struct irq_domain *domain;
  302. unsigned int parent_irq;
  303. domain = __init_i8259_irqs(node);
  304. parent_irq = irq_of_parse_and_map(node, 0);
  305. if (!parent_irq) {
  306. pr_err("Failed to map i8259 parent IRQ\n");
  307. irq_domain_remove(domain);
  308. return -ENODEV;
  309. }
  310. irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch,
  311. domain);
  312. return 0;
  313. }
  314. IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init);