irq-goldfish-pic.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for MIPS Goldfish Programmable Interrupt Controller.
  4. *
  5. * Author: Miodrag Dinic <miodrag.dinic@mips.com>
  6. */
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/interrupt.h>
  9. #include <linux/irq.h>
  10. #include <linux/irqchip.h>
  11. #include <linux/irqchip/chained_irq.h>
  12. #include <linux/irqdomain.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_irq.h>
  15. #define GFPIC_NR_IRQS 32
  16. /* 8..39 Cascaded Goldfish PIC interrupts */
  17. #define GFPIC_IRQ_BASE 8
  18. #define GFPIC_REG_IRQ_PENDING 0x04
  19. #define GFPIC_REG_IRQ_DISABLE_ALL 0x08
  20. #define GFPIC_REG_IRQ_DISABLE 0x0c
  21. #define GFPIC_REG_IRQ_ENABLE 0x10
  22. struct goldfish_pic_data {
  23. void __iomem *base;
  24. struct irq_domain *irq_domain;
  25. };
  26. static void goldfish_pic_cascade(struct irq_desc *desc)
  27. {
  28. struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
  29. struct irq_chip *host_chip = irq_desc_get_chip(desc);
  30. u32 pending, hwirq, virq;
  31. chained_irq_enter(host_chip, desc);
  32. pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
  33. while (pending) {
  34. hwirq = __fls(pending);
  35. virq = irq_linear_revmap(gfpic->irq_domain, hwirq);
  36. generic_handle_irq(virq);
  37. pending &= ~(1 << hwirq);
  38. }
  39. chained_irq_exit(host_chip, desc);
  40. }
  41. static const struct irq_domain_ops goldfish_irq_domain_ops = {
  42. .xlate = irq_domain_xlate_onecell,
  43. };
  44. static int __init goldfish_pic_of_init(struct device_node *of_node,
  45. struct device_node *parent)
  46. {
  47. struct goldfish_pic_data *gfpic;
  48. struct irq_chip_generic *gc;
  49. struct irq_chip_type *ct;
  50. unsigned int parent_irq;
  51. int ret = 0;
  52. gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
  53. if (!gfpic) {
  54. ret = -ENOMEM;
  55. goto out_err;
  56. }
  57. parent_irq = irq_of_parse_and_map(of_node, 0);
  58. if (!parent_irq) {
  59. pr_err("Failed to map parent IRQ!\n");
  60. ret = -EINVAL;
  61. goto out_free;
  62. }
  63. gfpic->base = of_iomap(of_node, 0);
  64. if (!gfpic->base) {
  65. pr_err("Failed to map base address!\n");
  66. ret = -ENOMEM;
  67. goto out_unmap_irq;
  68. }
  69. /* Mask interrupts. */
  70. writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
  71. gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
  72. handle_level_irq);
  73. if (!gc) {
  74. pr_err("Failed to allocate chip structures!\n");
  75. ret = -ENOMEM;
  76. goto out_iounmap;
  77. }
  78. ct = gc->chip_types;
  79. ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
  80. ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
  81. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  82. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  83. irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0,
  84. IRQ_NOPROBE | IRQ_LEVEL, 0);
  85. gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
  86. GFPIC_IRQ_BASE, 0,
  87. &goldfish_irq_domain_ops,
  88. NULL);
  89. if (!gfpic->irq_domain) {
  90. pr_err("Failed to add irqdomain!\n");
  91. ret = -ENOMEM;
  92. goto out_destroy_generic_chip;
  93. }
  94. irq_set_chained_handler_and_data(parent_irq,
  95. goldfish_pic_cascade, gfpic);
  96. pr_info("Successfully registered.\n");
  97. return 0;
  98. out_destroy_generic_chip:
  99. irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS),
  100. IRQ_NOPROBE | IRQ_LEVEL, 0);
  101. out_iounmap:
  102. iounmap(gfpic->base);
  103. out_unmap_irq:
  104. irq_dispose_mapping(parent_irq);
  105. out_free:
  106. kfree(gfpic);
  107. out_err:
  108. pr_err("Failed to initialize! (errno = %d)\n", ret);
  109. return ret;
  110. }
  111. IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);