irq-gic-v3-mbi.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 ARM Limited, All Rights Reserved.
  4. * Author: Marc Zyngier <marc.zyngier@arm.com>
  5. */
  6. #define pr_fmt(fmt) "GICv3: " fmt
  7. #include <linux/dma-iommu.h>
  8. #include <linux/irq.h>
  9. #include <linux/irqdomain.h>
  10. #include <linux/kernel.h>
  11. #include <linux/msi.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_pci.h>
  14. #include <linux/slab.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/irqchip/arm-gic-v3.h>
  17. struct mbi_range {
  18. u32 spi_start;
  19. u32 nr_spis;
  20. unsigned long *bm;
  21. };
  22. static DEFINE_MUTEX(mbi_lock);
  23. static phys_addr_t mbi_phys_base;
  24. static struct mbi_range *mbi_ranges;
  25. static unsigned int mbi_range_nr;
  26. static struct irq_chip mbi_irq_chip = {
  27. .name = "MBI",
  28. .irq_mask = irq_chip_mask_parent,
  29. .irq_unmask = irq_chip_unmask_parent,
  30. .irq_eoi = irq_chip_eoi_parent,
  31. .irq_set_type = irq_chip_set_type_parent,
  32. .irq_set_affinity = irq_chip_set_affinity_parent,
  33. };
  34. static int mbi_irq_gic_domain_alloc(struct irq_domain *domain,
  35. unsigned int virq,
  36. irq_hw_number_t hwirq)
  37. {
  38. struct irq_fwspec fwspec;
  39. struct irq_data *d;
  40. int err;
  41. /*
  42. * Using ACPI? There is no MBI support in the spec, you
  43. * shouldn't even be here.
  44. */
  45. if (!is_of_node(domain->parent->fwnode))
  46. return -EINVAL;
  47. /*
  48. * Let's default to edge. This is consistent with traditional
  49. * MSIs, and systems requiring level signaling will just
  50. * enforce the trigger on their own.
  51. */
  52. fwspec.fwnode = domain->parent->fwnode;
  53. fwspec.param_count = 3;
  54. fwspec.param[0] = 0;
  55. fwspec.param[1] = hwirq - 32;
  56. fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
  57. err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
  58. if (err)
  59. return err;
  60. d = irq_domain_get_irq_data(domain->parent, virq);
  61. return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
  62. }
  63. static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq,
  64. int nr_irqs)
  65. {
  66. mutex_lock(&mbi_lock);
  67. bitmap_release_region(mbi->bm, hwirq - mbi->spi_start,
  68. get_count_order(nr_irqs));
  69. mutex_unlock(&mbi_lock);
  70. }
  71. static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  72. unsigned int nr_irqs, void *args)
  73. {
  74. msi_alloc_info_t *info = args;
  75. struct mbi_range *mbi = NULL;
  76. int hwirq, offset, i, err = 0;
  77. mutex_lock(&mbi_lock);
  78. for (i = 0; i < mbi_range_nr; i++) {
  79. offset = bitmap_find_free_region(mbi_ranges[i].bm,
  80. mbi_ranges[i].nr_spis,
  81. get_count_order(nr_irqs));
  82. if (offset >= 0) {
  83. mbi = &mbi_ranges[i];
  84. break;
  85. }
  86. }
  87. mutex_unlock(&mbi_lock);
  88. if (!mbi)
  89. return -ENOSPC;
  90. hwirq = mbi->spi_start + offset;
  91. err = iommu_dma_prepare_msi(info->desc,
  92. mbi_phys_base + GICD_SETSPI_NSR);
  93. if (err)
  94. return err;
  95. for (i = 0; i < nr_irqs; i++) {
  96. err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
  97. if (err)
  98. goto fail;
  99. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  100. &mbi_irq_chip, mbi);
  101. }
  102. return 0;
  103. fail:
  104. irq_domain_free_irqs_parent(domain, virq, nr_irqs);
  105. mbi_free_msi(mbi, hwirq, nr_irqs);
  106. return err;
  107. }
  108. static void mbi_irq_domain_free(struct irq_domain *domain,
  109. unsigned int virq, unsigned int nr_irqs)
  110. {
  111. struct irq_data *d = irq_domain_get_irq_data(domain, virq);
  112. struct mbi_range *mbi = irq_data_get_irq_chip_data(d);
  113. mbi_free_msi(mbi, d->hwirq, nr_irqs);
  114. irq_domain_free_irqs_parent(domain, virq, nr_irqs);
  115. }
  116. static const struct irq_domain_ops mbi_domain_ops = {
  117. .alloc = mbi_irq_domain_alloc,
  118. .free = mbi_irq_domain_free,
  119. };
  120. static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  121. {
  122. msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
  123. msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
  124. msg[0].data = data->parent_data->hwirq;
  125. iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
  126. }
  127. #ifdef CONFIG_PCI_MSI
  128. /* PCI-specific irqchip */
  129. static void mbi_mask_msi_irq(struct irq_data *d)
  130. {
  131. pci_msi_mask_irq(d);
  132. irq_chip_mask_parent(d);
  133. }
  134. static void mbi_unmask_msi_irq(struct irq_data *d)
  135. {
  136. pci_msi_unmask_irq(d);
  137. irq_chip_unmask_parent(d);
  138. }
  139. static struct irq_chip mbi_msi_irq_chip = {
  140. .name = "MSI",
  141. .irq_mask = mbi_mask_msi_irq,
  142. .irq_unmask = mbi_unmask_msi_irq,
  143. .irq_eoi = irq_chip_eoi_parent,
  144. .irq_compose_msi_msg = mbi_compose_msi_msg,
  145. .irq_write_msi_msg = pci_msi_domain_write_msg,
  146. };
  147. static struct msi_domain_info mbi_msi_domain_info = {
  148. .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  149. MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
  150. .chip = &mbi_msi_irq_chip,
  151. };
  152. static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain,
  153. struct irq_domain **pci_domain)
  154. {
  155. *pci_domain = pci_msi_create_irq_domain(nexus_domain->parent->fwnode,
  156. &mbi_msi_domain_info,
  157. nexus_domain);
  158. if (!*pci_domain)
  159. return -ENOMEM;
  160. return 0;
  161. }
  162. #else
  163. static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain,
  164. struct irq_domain **pci_domain)
  165. {
  166. *pci_domain = NULL;
  167. return 0;
  168. }
  169. #endif
  170. static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg)
  171. {
  172. mbi_compose_msi_msg(data, msg);
  173. msg[1].address_hi = upper_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
  174. msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
  175. msg[1].data = data->parent_data->hwirq;
  176. iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), &msg[1]);
  177. }
  178. /* Platform-MSI specific irqchip */
  179. static struct irq_chip mbi_pmsi_irq_chip = {
  180. .name = "pMSI",
  181. .irq_set_type = irq_chip_set_type_parent,
  182. .irq_compose_msi_msg = mbi_compose_mbi_msg,
  183. .flags = IRQCHIP_SUPPORTS_LEVEL_MSI,
  184. };
  185. static struct msi_domain_ops mbi_pmsi_ops = {
  186. };
  187. static struct msi_domain_info mbi_pmsi_domain_info = {
  188. .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  189. MSI_FLAG_LEVEL_CAPABLE),
  190. .ops = &mbi_pmsi_ops,
  191. .chip = &mbi_pmsi_irq_chip,
  192. };
  193. static int mbi_allocate_domains(struct irq_domain *parent)
  194. {
  195. struct irq_domain *nexus_domain, *pci_domain, *plat_domain;
  196. int err;
  197. nexus_domain = irq_domain_create_tree(parent->fwnode,
  198. &mbi_domain_ops, NULL);
  199. if (!nexus_domain)
  200. return -ENOMEM;
  201. irq_domain_update_bus_token(nexus_domain, DOMAIN_BUS_NEXUS);
  202. nexus_domain->parent = parent;
  203. err = mbi_allocate_pci_domain(nexus_domain, &pci_domain);
  204. plat_domain = platform_msi_create_irq_domain(parent->fwnode,
  205. &mbi_pmsi_domain_info,
  206. nexus_domain);
  207. if (err || !plat_domain) {
  208. if (plat_domain)
  209. irq_domain_remove(plat_domain);
  210. if (pci_domain)
  211. irq_domain_remove(pci_domain);
  212. irq_domain_remove(nexus_domain);
  213. return -ENOMEM;
  214. }
  215. return 0;
  216. }
  217. int __init mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent)
  218. {
  219. struct device_node *np;
  220. const __be32 *reg;
  221. int ret, n;
  222. np = to_of_node(fwnode);
  223. if (!of_property_read_bool(np, "msi-controller"))
  224. return 0;
  225. n = of_property_count_elems_of_size(np, "mbi-ranges", sizeof(u32));
  226. if (n <= 0 || n % 2)
  227. return -EINVAL;
  228. mbi_range_nr = n / 2;
  229. mbi_ranges = kcalloc(mbi_range_nr, sizeof(*mbi_ranges), GFP_KERNEL);
  230. if (!mbi_ranges)
  231. return -ENOMEM;
  232. for (n = 0; n < mbi_range_nr; n++) {
  233. ret = of_property_read_u32_index(np, "mbi-ranges", n * 2,
  234. &mbi_ranges[n].spi_start);
  235. if (ret)
  236. goto err_free_mbi;
  237. ret = of_property_read_u32_index(np, "mbi-ranges", n * 2 + 1,
  238. &mbi_ranges[n].nr_spis);
  239. if (ret)
  240. goto err_free_mbi;
  241. mbi_ranges[n].bm = kcalloc(BITS_TO_LONGS(mbi_ranges[n].nr_spis),
  242. sizeof(long), GFP_KERNEL);
  243. if (!mbi_ranges[n].bm) {
  244. ret = -ENOMEM;
  245. goto err_free_mbi;
  246. }
  247. pr_info("MBI range [%d:%d]\n", mbi_ranges[n].spi_start,
  248. mbi_ranges[n].spi_start + mbi_ranges[n].nr_spis - 1);
  249. }
  250. reg = of_get_property(np, "mbi-alias", NULL);
  251. if (reg) {
  252. mbi_phys_base = of_translate_address(np, reg);
  253. if (mbi_phys_base == (phys_addr_t)OF_BAD_ADDR) {
  254. ret = -ENXIO;
  255. goto err_free_mbi;
  256. }
  257. } else {
  258. struct resource res;
  259. if (of_address_to_resource(np, 0, &res)) {
  260. ret = -ENXIO;
  261. goto err_free_mbi;
  262. }
  263. mbi_phys_base = res.start;
  264. }
  265. pr_info("Using MBI frame %pa\n", &mbi_phys_base);
  266. ret = mbi_allocate_domains(parent);
  267. if (ret)
  268. goto err_free_mbi;
  269. return 0;
  270. err_free_mbi:
  271. if (mbi_ranges) {
  272. for (n = 0; n < mbi_range_nr; n++)
  273. kfree(mbi_ranges[n].bm);
  274. kfree(mbi_ranges);
  275. }
  276. return ret;
  277. }