irq-davinci-cp-intc.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Author: Steve Chen <schen@mvista.com>
  4. // Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
  5. // Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
  6. // Copyright (C) 2019, Texas Instruments
  7. //
  8. // TI Common Platform Interrupt Controller (cp_intc) driver
  9. #include <linux/export.h>
  10. #include <linux/init.h>
  11. #include <linux/irq.h>
  12. #include <linux/irqchip.h>
  13. #include <linux/irqchip/irq-davinci-cp-intc.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_irq.h>
  19. #include <asm/exception.h>
  20. #define DAVINCI_CP_INTC_CTRL 0x04
  21. #define DAVINCI_CP_INTC_HOST_CTRL 0x0c
  22. #define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10
  23. #define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24
  24. #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28
  25. #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2c
  26. #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
  27. #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
  28. #define DAVINCI_CP_INTC_PRIO_IDX 0x80
  29. #define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
  30. #define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
  31. #define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
  32. #define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0d00 + (n << 2))
  33. #define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0d80 + (n << 2))
  34. #define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
  35. #define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0)
  36. #define DAVINCI_CP_INTC_GPIR_NONE BIT(31)
  37. static void __iomem *davinci_cp_intc_base;
  38. static struct irq_domain *davinci_cp_intc_irq_domain;
  39. static inline unsigned int davinci_cp_intc_read(unsigned int offset)
  40. {
  41. return readl_relaxed(davinci_cp_intc_base + offset);
  42. }
  43. static inline void davinci_cp_intc_write(unsigned long value,
  44. unsigned int offset)
  45. {
  46. writel_relaxed(value, davinci_cp_intc_base + offset);
  47. }
  48. static void davinci_cp_intc_ack_irq(struct irq_data *d)
  49. {
  50. davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR);
  51. }
  52. static void davinci_cp_intc_mask_irq(struct irq_data *d)
  53. {
  54. /* XXX don't know why we need to disable nIRQ here... */
  55. davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR);
  56. davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR);
  57. davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
  58. }
  59. static void davinci_cp_intc_unmask_irq(struct irq_data *d)
  60. {
  61. davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET);
  62. }
  63. static int davinci_cp_intc_set_irq_type(struct irq_data *d,
  64. unsigned int flow_type)
  65. {
  66. unsigned int reg, mask, polarity, type;
  67. reg = BIT_WORD(d->hwirq);
  68. mask = BIT_MASK(d->hwirq);
  69. polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg));
  70. type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg));
  71. switch (flow_type) {
  72. case IRQ_TYPE_EDGE_RISING:
  73. polarity |= mask;
  74. type |= mask;
  75. break;
  76. case IRQ_TYPE_EDGE_FALLING:
  77. polarity &= ~mask;
  78. type |= mask;
  79. break;
  80. case IRQ_TYPE_LEVEL_HIGH:
  81. polarity |= mask;
  82. type &= ~mask;
  83. break;
  84. case IRQ_TYPE_LEVEL_LOW:
  85. polarity &= ~mask;
  86. type &= ~mask;
  87. break;
  88. default:
  89. return -EINVAL;
  90. }
  91. davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg));
  92. davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg));
  93. return 0;
  94. }
  95. static struct irq_chip davinci_cp_intc_irq_chip = {
  96. .name = "cp_intc",
  97. .irq_ack = davinci_cp_intc_ack_irq,
  98. .irq_mask = davinci_cp_intc_mask_irq,
  99. .irq_unmask = davinci_cp_intc_unmask_irq,
  100. .irq_set_type = davinci_cp_intc_set_irq_type,
  101. .flags = IRQCHIP_SKIP_SET_WAKE,
  102. };
  103. static asmlinkage void __exception_irq_entry
  104. davinci_cp_intc_handle_irq(struct pt_regs *regs)
  105. {
  106. int gpir, irqnr, none;
  107. /*
  108. * The interrupt number is in first ten bits. The NONE field set to 1
  109. * indicates a spurious irq.
  110. */
  111. gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX);
  112. irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK;
  113. none = gpir & DAVINCI_CP_INTC_GPIR_NONE;
  114. if (unlikely(none)) {
  115. pr_err_once("%s: spurious irq!\n", __func__);
  116. return;
  117. }
  118. handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs);
  119. }
  120. static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq,
  121. irq_hw_number_t hw)
  122. {
  123. pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
  124. irq_set_chip(virq, &davinci_cp_intc_irq_chip);
  125. irq_set_probe(virq);
  126. irq_set_handler(virq, handle_edge_irq);
  127. return 0;
  128. }
  129. static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
  130. .map = davinci_cp_intc_host_map,
  131. .xlate = irq_domain_xlate_onetwocell,
  132. };
  133. static int __init
  134. davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
  135. struct device_node *node)
  136. {
  137. unsigned int num_regs = BITS_TO_LONGS(config->num_irqs);
  138. int offset, irq_base;
  139. void __iomem *req;
  140. req = request_mem_region(config->reg.start,
  141. resource_size(&config->reg),
  142. "davinci-cp-intc");
  143. if (!req) {
  144. pr_err("%s: register range busy\n", __func__);
  145. return -EBUSY;
  146. }
  147. davinci_cp_intc_base = ioremap(config->reg.start,
  148. resource_size(&config->reg));
  149. if (!davinci_cp_intc_base) {
  150. pr_err("%s: unable to ioremap register range\n", __func__);
  151. return -EINVAL;
  152. }
  153. davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE);
  154. /* Disable all host interrupts */
  155. davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
  156. /* Disable system interrupts */
  157. for (offset = 0; offset < num_regs; offset++)
  158. davinci_cp_intc_write(~0,
  159. DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset));
  160. /* Set to normal mode, no nesting, no priority hold */
  161. davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
  162. davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
  163. /* Clear system interrupt status */
  164. for (offset = 0; offset < num_regs; offset++)
  165. davinci_cp_intc_write(~0,
  166. DAVINCI_CP_INTC_SYS_STAT_CLR(offset));
  167. /* Enable nIRQ (what about nFIQ?) */
  168. davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
  169. /* Default all priorities to channel 7. */
  170. num_regs = (config->num_irqs + 3) >> 2; /* 4 channels per register */
  171. for (offset = 0; offset < num_regs; offset++)
  172. davinci_cp_intc_write(0x07070707,
  173. DAVINCI_CP_INTC_CHAN_MAP(offset));
  174. irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
  175. if (irq_base < 0) {
  176. pr_err("%s: unable to allocate interrupt descriptors: %d\n",
  177. __func__, irq_base);
  178. return irq_base;
  179. }
  180. davinci_cp_intc_irq_domain = irq_domain_add_legacy(
  181. node, config->num_irqs, irq_base, 0,
  182. &davinci_cp_intc_irq_domain_ops, NULL);
  183. if (!davinci_cp_intc_irq_domain) {
  184. pr_err("%s: unable to create an interrupt domain\n", __func__);
  185. return -EINVAL;
  186. }
  187. set_handle_irq(davinci_cp_intc_handle_irq);
  188. /* Enable global interrupt */
  189. davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE);
  190. return 0;
  191. }
  192. int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config)
  193. {
  194. return davinci_cp_intc_do_init(config, NULL);
  195. }
  196. static int __init davinci_cp_intc_of_init(struct device_node *node,
  197. struct device_node *parent)
  198. {
  199. struct davinci_cp_intc_config config = { };
  200. int ret;
  201. ret = of_address_to_resource(node, 0, &config.reg);
  202. if (ret) {
  203. pr_err("%s: unable to get the register range from device-tree\n",
  204. __func__);
  205. return ret;
  206. }
  207. ret = of_property_read_u32(node, "ti,intc-size", &config.num_irqs);
  208. if (ret) {
  209. pr_err("%s: unable to read the 'ti,intc-size' property\n",
  210. __func__);
  211. return ret;
  212. }
  213. return davinci_cp_intc_do_init(&config, node);
  214. }
  215. IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);