irq-bcm2836.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
  4. *
  5. * Copyright 2015 Broadcom
  6. */
  7. #include <linux/cpu.h>
  8. #include <linux/of_address.h>
  9. #include <linux/of_irq.h>
  10. #include <linux/irqchip.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/irqchip/chained_irq.h>
  13. #include <linux/irqchip/irq-bcm2836.h>
  14. #include <asm/exception.h>
  15. struct bcm2836_arm_irqchip_intc {
  16. struct irq_domain *domain;
  17. void __iomem *base;
  18. };
  19. static struct bcm2836_arm_irqchip_intc intc __read_mostly;
  20. static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
  21. unsigned int bit,
  22. int cpu)
  23. {
  24. void __iomem *reg = intc.base + reg_offset + 4 * cpu;
  25. writel(readl(reg) & ~BIT(bit), reg);
  26. }
  27. static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
  28. unsigned int bit,
  29. int cpu)
  30. {
  31. void __iomem *reg = intc.base + reg_offset + 4 * cpu;
  32. writel(readl(reg) | BIT(bit), reg);
  33. }
  34. static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
  35. {
  36. bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
  37. d->hwirq - LOCAL_IRQ_CNTPSIRQ,
  38. smp_processor_id());
  39. }
  40. static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
  41. {
  42. bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
  43. d->hwirq - LOCAL_IRQ_CNTPSIRQ,
  44. smp_processor_id());
  45. }
  46. static struct irq_chip bcm2836_arm_irqchip_timer = {
  47. .name = "bcm2836-timer",
  48. .irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
  49. .irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
  50. };
  51. static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
  52. {
  53. writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
  54. }
  55. static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
  56. {
  57. writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
  58. }
  59. static struct irq_chip bcm2836_arm_irqchip_pmu = {
  60. .name = "bcm2836-pmu",
  61. .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
  62. .irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
  63. };
  64. static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
  65. {
  66. }
  67. static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
  68. {
  69. }
  70. static struct irq_chip bcm2836_arm_irqchip_gpu = {
  71. .name = "bcm2836-gpu",
  72. .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
  73. .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
  74. };
  75. static void bcm2836_arm_irqchip_dummy_op(struct irq_data *d)
  76. {
  77. }
  78. static struct irq_chip bcm2836_arm_irqchip_dummy = {
  79. .name = "bcm2836-dummy",
  80. .irq_eoi = bcm2836_arm_irqchip_dummy_op,
  81. };
  82. static int bcm2836_map(struct irq_domain *d, unsigned int irq,
  83. irq_hw_number_t hw)
  84. {
  85. struct irq_chip *chip;
  86. switch (hw) {
  87. case LOCAL_IRQ_MAILBOX0:
  88. chip = &bcm2836_arm_irqchip_dummy;
  89. break;
  90. case LOCAL_IRQ_CNTPSIRQ:
  91. case LOCAL_IRQ_CNTPNSIRQ:
  92. case LOCAL_IRQ_CNTHPIRQ:
  93. case LOCAL_IRQ_CNTVIRQ:
  94. chip = &bcm2836_arm_irqchip_timer;
  95. break;
  96. case LOCAL_IRQ_GPU_FAST:
  97. chip = &bcm2836_arm_irqchip_gpu;
  98. break;
  99. case LOCAL_IRQ_PMU_FAST:
  100. chip = &bcm2836_arm_irqchip_pmu;
  101. break;
  102. default:
  103. pr_warn_once("Unexpected hw irq: %lu\n", hw);
  104. return -EINVAL;
  105. }
  106. irq_set_percpu_devid(irq);
  107. irq_domain_set_info(d, irq, hw, chip, d->host_data,
  108. handle_percpu_devid_irq, NULL, NULL);
  109. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  110. return 0;
  111. }
  112. static void
  113. __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
  114. {
  115. int cpu = smp_processor_id();
  116. u32 stat;
  117. stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
  118. if (stat) {
  119. u32 hwirq = ffs(stat) - 1;
  120. handle_domain_irq(intc.domain, hwirq, regs);
  121. }
  122. }
  123. #ifdef CONFIG_SMP
  124. static struct irq_domain *ipi_domain;
  125. static void bcm2836_arm_irqchip_handle_ipi(struct irq_desc *desc)
  126. {
  127. struct irq_chip *chip = irq_desc_get_chip(desc);
  128. int cpu = smp_processor_id();
  129. u32 mbox_val;
  130. chained_irq_enter(chip, desc);
  131. mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
  132. if (mbox_val) {
  133. int hwirq = ffs(mbox_val) - 1;
  134. generic_handle_irq(irq_find_mapping(ipi_domain, hwirq));
  135. }
  136. chained_irq_exit(chip, desc);
  137. }
  138. static void bcm2836_arm_irqchip_ipi_eoi(struct irq_data *d)
  139. {
  140. int cpu = smp_processor_id();
  141. writel_relaxed(BIT(d->hwirq),
  142. intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
  143. }
  144. static void bcm2836_arm_irqchip_ipi_send_mask(struct irq_data *d,
  145. const struct cpumask *mask)
  146. {
  147. int cpu;
  148. void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
  149. /*
  150. * Ensure that stores to normal memory are visible to the
  151. * other CPUs before issuing the IPI.
  152. */
  153. smp_wmb();
  154. for_each_cpu(cpu, mask)
  155. writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
  156. }
  157. static struct irq_chip bcm2836_arm_irqchip_ipi = {
  158. .name = "IPI",
  159. .irq_mask = bcm2836_arm_irqchip_dummy_op,
  160. .irq_unmask = bcm2836_arm_irqchip_dummy_op,
  161. .irq_eoi = bcm2836_arm_irqchip_ipi_eoi,
  162. .ipi_send_mask = bcm2836_arm_irqchip_ipi_send_mask,
  163. };
  164. static int bcm2836_arm_irqchip_ipi_alloc(struct irq_domain *d,
  165. unsigned int virq,
  166. unsigned int nr_irqs, void *args)
  167. {
  168. int i;
  169. for (i = 0; i < nr_irqs; i++) {
  170. irq_set_percpu_devid(virq + i);
  171. irq_domain_set_info(d, virq + i, i, &bcm2836_arm_irqchip_ipi,
  172. d->host_data,
  173. handle_percpu_devid_fasteoi_ipi,
  174. NULL, NULL);
  175. }
  176. return 0;
  177. }
  178. static void bcm2836_arm_irqchip_ipi_free(struct irq_domain *d,
  179. unsigned int virq,
  180. unsigned int nr_irqs)
  181. {
  182. /* Not freeing IPIs */
  183. }
  184. static const struct irq_domain_ops ipi_domain_ops = {
  185. .alloc = bcm2836_arm_irqchip_ipi_alloc,
  186. .free = bcm2836_arm_irqchip_ipi_free,
  187. };
  188. static int bcm2836_cpu_starting(unsigned int cpu)
  189. {
  190. bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
  191. cpu);
  192. return 0;
  193. }
  194. static int bcm2836_cpu_dying(unsigned int cpu)
  195. {
  196. bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
  197. cpu);
  198. return 0;
  199. }
  200. #define BITS_PER_MBOX 32
  201. static void __init bcm2836_arm_irqchip_smp_init(void)
  202. {
  203. struct irq_fwspec ipi_fwspec = {
  204. .fwnode = intc.domain->fwnode,
  205. .param_count = 1,
  206. .param = {
  207. [0] = LOCAL_IRQ_MAILBOX0,
  208. },
  209. };
  210. int base_ipi, mux_irq;
  211. mux_irq = irq_create_fwspec_mapping(&ipi_fwspec);
  212. if (WARN_ON(mux_irq <= 0))
  213. return;
  214. ipi_domain = irq_domain_create_linear(intc.domain->fwnode,
  215. BITS_PER_MBOX, &ipi_domain_ops,
  216. NULL);
  217. if (WARN_ON(!ipi_domain))
  218. return;
  219. ipi_domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
  220. irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
  221. base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, BITS_PER_MBOX,
  222. NUMA_NO_NODE, NULL,
  223. false, NULL);
  224. if (WARN_ON(!base_ipi))
  225. return;
  226. set_smp_ipi_range(base_ipi, BITS_PER_MBOX);
  227. irq_set_chained_handler_and_data(mux_irq,
  228. bcm2836_arm_irqchip_handle_ipi, NULL);
  229. /* Unmask IPIs to the boot CPU. */
  230. cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
  231. "irqchip/bcm2836:starting", bcm2836_cpu_starting,
  232. bcm2836_cpu_dying);
  233. }
  234. #else
  235. #define bcm2836_arm_irqchip_smp_init() do { } while(0)
  236. #endif
  237. static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
  238. .xlate = irq_domain_xlate_onetwocell,
  239. .map = bcm2836_map,
  240. };
  241. /*
  242. * The LOCAL_IRQ_CNT* timer firings are based off of the external
  243. * oscillator with some scaling. The firmware sets up CNTFRQ to
  244. * report 19.2Mhz, but doesn't set up the scaling registers.
  245. */
  246. static void bcm2835_init_local_timer_frequency(void)
  247. {
  248. /*
  249. * Set the timer to source from the 19.2Mhz crystal clock (bit
  250. * 8 unset), and only increment by 1 instead of 2 (bit 9
  251. * unset).
  252. */
  253. writel(0, intc.base + LOCAL_CONTROL);
  254. /*
  255. * Set the timer prescaler to 1:1 (timer freq = input freq *
  256. * 2**31 / prescaler)
  257. */
  258. writel(0x80000000, intc.base + LOCAL_PRESCALER);
  259. }
  260. static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
  261. struct device_node *parent)
  262. {
  263. intc.base = of_iomap(node, 0);
  264. if (!intc.base) {
  265. panic("%pOF: unable to map local interrupt registers\n", node);
  266. }
  267. bcm2835_init_local_timer_frequency();
  268. intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
  269. &bcm2836_arm_irqchip_intc_ops,
  270. NULL);
  271. if (!intc.domain)
  272. panic("%pOF: unable to create IRQ domain\n", node);
  273. irq_domain_update_bus_token(intc.domain, DOMAIN_BUS_WIRED);
  274. bcm2836_arm_irqchip_smp_init();
  275. set_handle_irq(bcm2836_arm_irqchip_handle_irq);
  276. return 0;
  277. }
  278. IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
  279. bcm2836_arm_irqchip_l1_intc_of_init);