irq-bcm2835.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010 Broadcom
  4. * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
  5. *
  6. * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
  7. *
  8. * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
  9. * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
  10. * to look in the bank 1 status register for more information.
  11. *
  12. * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
  13. * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
  14. * status register, but bank 0 bit 8 is _not_ set.
  15. *
  16. * Quirk 2: You can't mask the register 1/2 pending interrupts
  17. *
  18. * In a proper cascaded interrupt controller, the interrupt lines with
  19. * cascaded interrupt controllers on them are just normal interrupt lines.
  20. * You can mask the interrupts and get on with things. With this controller
  21. * you can't do that.
  22. *
  23. * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
  24. *
  25. * Those interrupts that have shortcuts can only be masked/unmasked in
  26. * their respective banks' enable/disable registers. Doing so in the bank 0
  27. * enable/disable registers has no effect.
  28. *
  29. * The FIQ control register:
  30. * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
  31. * Bit 7: Enable FIQ generation
  32. * Bits 8+: Unused
  33. *
  34. * An interrupt must be disabled before configuring it for FIQ generation
  35. * otherwise both handlers will fire at the same time!
  36. */
  37. #include <linux/io.h>
  38. #include <linux/slab.h>
  39. #include <linux/of_address.h>
  40. #include <linux/of_irq.h>
  41. #include <linux/irqchip.h>
  42. #include <linux/irqdomain.h>
  43. #include <asm/exception.h>
  44. /* Put the bank and irq (32 bits) into the hwirq */
  45. #define MAKE_HWIRQ(b, n) ((b << 5) | (n))
  46. #define HWIRQ_BANK(i) (i >> 5)
  47. #define HWIRQ_BIT(i) BIT(i & 0x1f)
  48. #define NR_IRQS_BANK0 8
  49. #define BANK0_HWIRQ_MASK 0xff
  50. /* Shortcuts can't be disabled so any unknown new ones need to be masked */
  51. #define SHORTCUT1_MASK 0x00007c00
  52. #define SHORTCUT2_MASK 0x001f8000
  53. #define SHORTCUT_SHIFT 10
  54. #define BANK1_HWIRQ BIT(8)
  55. #define BANK2_HWIRQ BIT(9)
  56. #define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
  57. | SHORTCUT1_MASK | SHORTCUT2_MASK)
  58. #define REG_FIQ_CONTROL 0x0c
  59. #define FIQ_CONTROL_ENABLE BIT(7)
  60. #define NR_BANKS 3
  61. #define IRQS_PER_BANK 32
  62. static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
  63. static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
  64. static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
  65. static const int bank_irqs[] __initconst = { 8, 32, 32 };
  66. static const int shortcuts[] = {
  67. 7, 9, 10, 18, 19, /* Bank 1 */
  68. 21, 22, 23, 24, 25, 30 /* Bank 2 */
  69. };
  70. struct armctrl_ic {
  71. void __iomem *base;
  72. void __iomem *pending[NR_BANKS];
  73. void __iomem *enable[NR_BANKS];
  74. void __iomem *disable[NR_BANKS];
  75. struct irq_domain *domain;
  76. };
  77. static struct armctrl_ic intc __read_mostly;
  78. static void __exception_irq_entry bcm2835_handle_irq(
  79. struct pt_regs *regs);
  80. static void bcm2836_chained_handle_irq(struct irq_desc *desc);
  81. static void armctrl_mask_irq(struct irq_data *d)
  82. {
  83. writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
  84. }
  85. static void armctrl_unmask_irq(struct irq_data *d)
  86. {
  87. writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
  88. }
  89. static struct irq_chip armctrl_chip = {
  90. .name = "ARMCTRL-level",
  91. .irq_mask = armctrl_mask_irq,
  92. .irq_unmask = armctrl_unmask_irq
  93. };
  94. static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
  95. const u32 *intspec, unsigned int intsize,
  96. unsigned long *out_hwirq, unsigned int *out_type)
  97. {
  98. if (WARN_ON(intsize != 2))
  99. return -EINVAL;
  100. if (WARN_ON(intspec[0] >= NR_BANKS))
  101. return -EINVAL;
  102. if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
  103. return -EINVAL;
  104. if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
  105. return -EINVAL;
  106. *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
  107. *out_type = IRQ_TYPE_NONE;
  108. return 0;
  109. }
  110. static const struct irq_domain_ops armctrl_ops = {
  111. .xlate = armctrl_xlate
  112. };
  113. static int __init armctrl_of_init(struct device_node *node,
  114. struct device_node *parent,
  115. bool is_2836)
  116. {
  117. void __iomem *base;
  118. int irq, b, i;
  119. u32 reg;
  120. base = of_iomap(node, 0);
  121. if (!base)
  122. panic("%pOF: unable to map IC registers\n", node);
  123. intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
  124. &armctrl_ops, NULL);
  125. if (!intc.domain)
  126. panic("%pOF: unable to create IRQ domain\n", node);
  127. for (b = 0; b < NR_BANKS; b++) {
  128. intc.pending[b] = base + reg_pending[b];
  129. intc.enable[b] = base + reg_enable[b];
  130. intc.disable[b] = base + reg_disable[b];
  131. for (i = 0; i < bank_irqs[b]; i++) {
  132. irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
  133. BUG_ON(irq <= 0);
  134. irq_set_chip_and_handler(irq, &armctrl_chip,
  135. handle_level_irq);
  136. irq_set_probe(irq);
  137. }
  138. reg = readl_relaxed(intc.enable[b]);
  139. if (reg) {
  140. writel_relaxed(reg, intc.disable[b]);
  141. pr_err(FW_BUG "Bootloader left irq enabled: "
  142. "bank %d irq %*pbl\n", b, IRQS_PER_BANK, &reg);
  143. }
  144. }
  145. reg = readl_relaxed(base + REG_FIQ_CONTROL);
  146. if (reg & FIQ_CONTROL_ENABLE) {
  147. writel_relaxed(0, base + REG_FIQ_CONTROL);
  148. pr_err(FW_BUG "Bootloader left fiq enabled\n");
  149. }
  150. if (is_2836) {
  151. int parent_irq = irq_of_parse_and_map(node, 0);
  152. if (!parent_irq) {
  153. panic("%pOF: unable to get parent interrupt.\n",
  154. node);
  155. }
  156. irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
  157. } else {
  158. set_handle_irq(bcm2835_handle_irq);
  159. }
  160. return 0;
  161. }
  162. static int __init bcm2835_armctrl_of_init(struct device_node *node,
  163. struct device_node *parent)
  164. {
  165. return armctrl_of_init(node, parent, false);
  166. }
  167. static int __init bcm2836_armctrl_of_init(struct device_node *node,
  168. struct device_node *parent)
  169. {
  170. return armctrl_of_init(node, parent, true);
  171. }
  172. /*
  173. * Handle each interrupt across the entire interrupt controller. This reads the
  174. * status register before handling each interrupt, which is necessary given that
  175. * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
  176. */
  177. static u32 armctrl_translate_bank(int bank)
  178. {
  179. u32 stat = readl_relaxed(intc.pending[bank]);
  180. return MAKE_HWIRQ(bank, ffs(stat) - 1);
  181. }
  182. static u32 armctrl_translate_shortcut(int bank, u32 stat)
  183. {
  184. return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
  185. }
  186. static u32 get_next_armctrl_hwirq(void)
  187. {
  188. u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
  189. if (stat == 0)
  190. return ~0;
  191. else if (stat & BANK0_HWIRQ_MASK)
  192. return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
  193. else if (stat & SHORTCUT1_MASK)
  194. return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
  195. else if (stat & SHORTCUT2_MASK)
  196. return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
  197. else if (stat & BANK1_HWIRQ)
  198. return armctrl_translate_bank(1);
  199. else if (stat & BANK2_HWIRQ)
  200. return armctrl_translate_bank(2);
  201. else
  202. BUG();
  203. }
  204. static void __exception_irq_entry bcm2835_handle_irq(
  205. struct pt_regs *regs)
  206. {
  207. u32 hwirq;
  208. while ((hwirq = get_next_armctrl_hwirq()) != ~0)
  209. handle_domain_irq(intc.domain, hwirq, regs);
  210. }
  211. static void bcm2836_chained_handle_irq(struct irq_desc *desc)
  212. {
  213. u32 hwirq;
  214. while ((hwirq = get_next_armctrl_hwirq()) != ~0)
  215. generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
  216. }
  217. IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
  218. bcm2835_armctrl_of_init);
  219. IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
  220. bcm2836_armctrl_of_init);