irq-aspeed-vic.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
  4. *
  5. * Driver for Aspeed "new" VIC as found in SoC generation 3 and later
  6. *
  7. * Based on irq-vic.c:
  8. *
  9. * Copyright (C) 1999 - 2003 ARM Limited
  10. * Copyright (C) 2000 Deep Blue Solutions Ltd
  11. */
  12. #include <linux/export.h>
  13. #include <linux/init.h>
  14. #include <linux/list.h>
  15. #include <linux/io.h>
  16. #include <linux/irq.h>
  17. #include <linux/irqchip.h>
  18. #include <linux/irqchip/chained_irq.h>
  19. #include <linux/irqdomain.h>
  20. #include <linux/of.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/syscore_ops.h>
  24. #include <linux/device.h>
  25. #include <linux/slab.h>
  26. #include <asm/exception.h>
  27. #include <asm/irq.h>
  28. /* These definitions correspond to the "new mapping" of the
  29. * register set that interleaves "high" and "low". The offsets
  30. * below are for the "low" register, add 4 to get to the high one
  31. */
  32. #define AVIC_IRQ_STATUS 0x00
  33. #define AVIC_FIQ_STATUS 0x08
  34. #define AVIC_RAW_STATUS 0x10
  35. #define AVIC_INT_SELECT 0x18
  36. #define AVIC_INT_ENABLE 0x20
  37. #define AVIC_INT_ENABLE_CLR 0x28
  38. #define AVIC_INT_TRIGGER 0x30
  39. #define AVIC_INT_TRIGGER_CLR 0x38
  40. #define AVIC_INT_SENSE 0x40
  41. #define AVIC_INT_DUAL_EDGE 0x48
  42. #define AVIC_INT_EVENT 0x50
  43. #define AVIC_EDGE_CLR 0x58
  44. #define AVIC_EDGE_STATUS 0x60
  45. #define NUM_IRQS 64
  46. struct aspeed_vic {
  47. void __iomem *base;
  48. u32 edge_sources[2];
  49. struct irq_domain *dom;
  50. };
  51. static struct aspeed_vic *system_avic;
  52. static void vic_init_hw(struct aspeed_vic *vic)
  53. {
  54. u32 sense;
  55. /* Disable all interrupts */
  56. writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);
  57. writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);
  58. /* Make sure no soft trigger is on */
  59. writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);
  60. writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);
  61. /* Set everything to be IRQ */
  62. writel(0, vic->base + AVIC_INT_SELECT);
  63. writel(0, vic->base + AVIC_INT_SELECT + 4);
  64. /* Some interrupts have a programable high/low level trigger
  65. * (4 GPIO direct inputs), for now we assume this was configured
  66. * by firmware. We read which ones are edge now.
  67. */
  68. sense = readl(vic->base + AVIC_INT_SENSE);
  69. vic->edge_sources[0] = ~sense;
  70. sense = readl(vic->base + AVIC_INT_SENSE + 4);
  71. vic->edge_sources[1] = ~sense;
  72. /* Clear edge detection latches */
  73. writel(0xffffffff, vic->base + AVIC_EDGE_CLR);
  74. writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);
  75. }
  76. static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
  77. {
  78. struct aspeed_vic *vic = system_avic;
  79. u32 stat, irq;
  80. for (;;) {
  81. irq = 0;
  82. stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);
  83. if (!stat) {
  84. stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);
  85. irq = 32;
  86. }
  87. if (stat == 0)
  88. break;
  89. irq += ffs(stat) - 1;
  90. handle_domain_irq(vic->dom, irq, regs);
  91. }
  92. }
  93. static void avic_ack_irq(struct irq_data *d)
  94. {
  95. struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
  96. unsigned int sidx = d->hwirq >> 5;
  97. unsigned int sbit = 1u << (d->hwirq & 0x1f);
  98. /* Clear edge latch for edge interrupts, nop for level */
  99. if (vic->edge_sources[sidx] & sbit)
  100. writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
  101. }
  102. static void avic_mask_irq(struct irq_data *d)
  103. {
  104. struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
  105. unsigned int sidx = d->hwirq >> 5;
  106. unsigned int sbit = 1u << (d->hwirq & 0x1f);
  107. writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
  108. }
  109. static void avic_unmask_irq(struct irq_data *d)
  110. {
  111. struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
  112. unsigned int sidx = d->hwirq >> 5;
  113. unsigned int sbit = 1u << (d->hwirq & 0x1f);
  114. writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);
  115. }
  116. /* For level irq, faster than going through a nop "ack" and mask */
  117. static void avic_mask_ack_irq(struct irq_data *d)
  118. {
  119. struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
  120. unsigned int sidx = d->hwirq >> 5;
  121. unsigned int sbit = 1u << (d->hwirq & 0x1f);
  122. /* First mask */
  123. writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
  124. /* Then clear edge latch for edge interrupts */
  125. if (vic->edge_sources[sidx] & sbit)
  126. writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
  127. }
  128. static struct irq_chip avic_chip = {
  129. .name = "AVIC",
  130. .irq_ack = avic_ack_irq,
  131. .irq_mask = avic_mask_irq,
  132. .irq_unmask = avic_unmask_irq,
  133. .irq_mask_ack = avic_mask_ack_irq,
  134. };
  135. static int avic_map(struct irq_domain *d, unsigned int irq,
  136. irq_hw_number_t hwirq)
  137. {
  138. struct aspeed_vic *vic = d->host_data;
  139. unsigned int sidx = hwirq >> 5;
  140. unsigned int sbit = 1u << (hwirq & 0x1f);
  141. /* Check if interrupt exists */
  142. if (sidx > 1)
  143. return -EPERM;
  144. if (vic->edge_sources[sidx] & sbit)
  145. irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq);
  146. else
  147. irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq);
  148. irq_set_chip_data(irq, vic);
  149. irq_set_probe(irq);
  150. return 0;
  151. }
  152. static const struct irq_domain_ops avic_dom_ops = {
  153. .map = avic_map,
  154. .xlate = irq_domain_xlate_onetwocell,
  155. };
  156. static int __init avic_of_init(struct device_node *node,
  157. struct device_node *parent)
  158. {
  159. void __iomem *regs;
  160. struct aspeed_vic *vic;
  161. if (WARN(parent, "non-root Aspeed VIC not supported"))
  162. return -EINVAL;
  163. if (WARN(system_avic, "duplicate Aspeed VIC not supported"))
  164. return -EINVAL;
  165. regs = of_iomap(node, 0);
  166. if (WARN_ON(!regs))
  167. return -EIO;
  168. vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL);
  169. if (WARN_ON(!vic)) {
  170. iounmap(regs);
  171. return -ENOMEM;
  172. }
  173. vic->base = regs;
  174. /* Initialize soures, all masked */
  175. vic_init_hw(vic);
  176. /* Ready to receive interrupts */
  177. system_avic = vic;
  178. set_handle_irq(avic_handle_irq);
  179. /* Register our domain */
  180. vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0,
  181. &avic_dom_ops, vic);
  182. return 0;
  183. }
  184. IRQCHIP_DECLARE(ast2400_vic, "aspeed,ast2400-vic", avic_of_init);
  185. IRQCHIP_DECLARE(ast2500_vic, "aspeed,ast2500-vic", avic_of_init);