irq-aspeed-scu-ic.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller
  4. * Copyright 2019 IBM Corporation
  5. *
  6. * Eddie James <eajames@linux.ibm.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/irq.h>
  10. #include <linux/irqchip.h>
  11. #include <linux/irqchip/chained_irq.h>
  12. #include <linux/irqdomain.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/regmap.h>
  16. #define ASPEED_SCU_IC_REG 0x018
  17. #define ASPEED_SCU_IC_SHIFT 0
  18. #define ASPEED_SCU_IC_ENABLE GENMASK(6, ASPEED_SCU_IC_SHIFT)
  19. #define ASPEED_SCU_IC_NUM_IRQS 7
  20. #define ASPEED_SCU_IC_STATUS_SHIFT 16
  21. #define ASPEED_AST2600_SCU_IC0_REG 0x560
  22. #define ASPEED_AST2600_SCU_IC0_SHIFT 0
  23. #define ASPEED_AST2600_SCU_IC0_ENABLE \
  24. GENMASK(5, ASPEED_AST2600_SCU_IC0_SHIFT)
  25. #define ASPEED_AST2600_SCU_IC0_NUM_IRQS 6
  26. #define ASPEED_AST2600_SCU_IC1_REG 0x570
  27. #define ASPEED_AST2600_SCU_IC1_SHIFT 4
  28. #define ASPEED_AST2600_SCU_IC1_ENABLE \
  29. GENMASK(5, ASPEED_AST2600_SCU_IC1_SHIFT)
  30. #define ASPEED_AST2600_SCU_IC1_NUM_IRQS 2
  31. struct aspeed_scu_ic {
  32. unsigned long irq_enable;
  33. unsigned long irq_shift;
  34. unsigned int num_irqs;
  35. unsigned int reg;
  36. struct regmap *scu;
  37. struct irq_domain *irq_domain;
  38. };
  39. static void aspeed_scu_ic_irq_handler(struct irq_desc *desc)
  40. {
  41. unsigned int irq;
  42. unsigned int sts;
  43. unsigned long bit;
  44. unsigned long enabled;
  45. unsigned long max;
  46. unsigned long status;
  47. struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc);
  48. struct irq_chip *chip = irq_desc_get_chip(desc);
  49. unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT;
  50. chained_irq_enter(chip, desc);
  51. /*
  52. * The SCU IC has just one register to control its operation and read
  53. * status. The interrupt enable bits occupy the lower 16 bits of the
  54. * register, while the interrupt status bits occupy the upper 16 bits.
  55. * The status bit for a given interrupt is always 16 bits shifted from
  56. * the enable bit for the same interrupt.
  57. * Therefore, perform the IRQ operations in the enable bit space by
  58. * shifting the status down to get the mapping and then back up to
  59. * clear the bit.
  60. */
  61. regmap_read(scu_ic->scu, scu_ic->reg, &sts);
  62. enabled = sts & scu_ic->irq_enable;
  63. status = (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled;
  64. bit = scu_ic->irq_shift;
  65. max = scu_ic->num_irqs + bit;
  66. for_each_set_bit_from(bit, &status, max) {
  67. irq = irq_find_mapping(scu_ic->irq_domain,
  68. bit - scu_ic->irq_shift);
  69. generic_handle_irq(irq);
  70. regmap_write_bits(scu_ic->scu, scu_ic->reg, mask,
  71. BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT));
  72. }
  73. chained_irq_exit(chip, desc);
  74. }
  75. static void aspeed_scu_ic_irq_mask(struct irq_data *data)
  76. {
  77. struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);
  78. unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) |
  79. (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
  80. /*
  81. * Status bits are cleared by writing 1. In order to prevent the mask
  82. * operation from clearing the status bits, they should be under the
  83. * mask and written with 0.
  84. */
  85. regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0);
  86. }
  87. static void aspeed_scu_ic_irq_unmask(struct irq_data *data)
  88. {
  89. struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);
  90. unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);
  91. unsigned int mask = bit |
  92. (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
  93. /*
  94. * Status bits are cleared by writing 1. In order to prevent the unmask
  95. * operation from clearing the status bits, they should be under the
  96. * mask and written with 0.
  97. */
  98. regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit);
  99. }
  100. static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data,
  101. const struct cpumask *dest,
  102. bool force)
  103. {
  104. return -EINVAL;
  105. }
  106. static struct irq_chip aspeed_scu_ic_chip = {
  107. .name = "aspeed-scu-ic",
  108. .irq_mask = aspeed_scu_ic_irq_mask,
  109. .irq_unmask = aspeed_scu_ic_irq_unmask,
  110. .irq_set_affinity = aspeed_scu_ic_irq_set_affinity,
  111. };
  112. static int aspeed_scu_ic_map(struct irq_domain *domain, unsigned int irq,
  113. irq_hw_number_t hwirq)
  114. {
  115. irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip, handle_level_irq);
  116. irq_set_chip_data(irq, domain->host_data);
  117. return 0;
  118. }
  119. static const struct irq_domain_ops aspeed_scu_ic_domain_ops = {
  120. .map = aspeed_scu_ic_map,
  121. };
  122. static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic,
  123. struct device_node *node)
  124. {
  125. int irq;
  126. int rc = 0;
  127. if (!node->parent) {
  128. rc = -ENODEV;
  129. goto err;
  130. }
  131. scu_ic->scu = syscon_node_to_regmap(node->parent);
  132. if (IS_ERR(scu_ic->scu)) {
  133. rc = PTR_ERR(scu_ic->scu);
  134. goto err;
  135. }
  136. irq = irq_of_parse_and_map(node, 0);
  137. if (irq < 0) {
  138. rc = irq;
  139. goto err;
  140. }
  141. scu_ic->irq_domain = irq_domain_add_linear(node, scu_ic->num_irqs,
  142. &aspeed_scu_ic_domain_ops,
  143. scu_ic);
  144. if (!scu_ic->irq_domain) {
  145. rc = -ENOMEM;
  146. goto err;
  147. }
  148. irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler,
  149. scu_ic);
  150. return 0;
  151. err:
  152. kfree(scu_ic);
  153. return rc;
  154. }
  155. static int __init aspeed_scu_ic_of_init(struct device_node *node,
  156. struct device_node *parent)
  157. {
  158. struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
  159. if (!scu_ic)
  160. return -ENOMEM;
  161. scu_ic->irq_enable = ASPEED_SCU_IC_ENABLE;
  162. scu_ic->irq_shift = ASPEED_SCU_IC_SHIFT;
  163. scu_ic->num_irqs = ASPEED_SCU_IC_NUM_IRQS;
  164. scu_ic->reg = ASPEED_SCU_IC_REG;
  165. return aspeed_scu_ic_of_init_common(scu_ic, node);
  166. }
  167. static int __init aspeed_ast2600_scu_ic0_of_init(struct device_node *node,
  168. struct device_node *parent)
  169. {
  170. struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
  171. if (!scu_ic)
  172. return -ENOMEM;
  173. scu_ic->irq_enable = ASPEED_AST2600_SCU_IC0_ENABLE;
  174. scu_ic->irq_shift = ASPEED_AST2600_SCU_IC0_SHIFT;
  175. scu_ic->num_irqs = ASPEED_AST2600_SCU_IC0_NUM_IRQS;
  176. scu_ic->reg = ASPEED_AST2600_SCU_IC0_REG;
  177. return aspeed_scu_ic_of_init_common(scu_ic, node);
  178. }
  179. static int __init aspeed_ast2600_scu_ic1_of_init(struct device_node *node,
  180. struct device_node *parent)
  181. {
  182. struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
  183. if (!scu_ic)
  184. return -ENOMEM;
  185. scu_ic->irq_enable = ASPEED_AST2600_SCU_IC1_ENABLE;
  186. scu_ic->irq_shift = ASPEED_AST2600_SCU_IC1_SHIFT;
  187. scu_ic->num_irqs = ASPEED_AST2600_SCU_IC1_NUM_IRQS;
  188. scu_ic->reg = ASPEED_AST2600_SCU_IC1_REG;
  189. return aspeed_scu_ic_of_init_common(scu_ic, node);
  190. }
  191. IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init);
  192. IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init);
  193. IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0",
  194. aspeed_ast2600_scu_ic0_of_init);
  195. IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1",
  196. aspeed_ast2600_scu_ic1_of_init);