irq-al-fic.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  4. */
  5. #include <linux/bitfield.h>
  6. #include <linux/irq.h>
  7. #include <linux/irqchip.h>
  8. #include <linux/irqchip/chained_irq.h>
  9. #include <linux/irqdomain.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. /* FIC Registers */
  15. #define AL_FIC_CAUSE 0x00
  16. #define AL_FIC_SET_CAUSE 0x08
  17. #define AL_FIC_MASK 0x10
  18. #define AL_FIC_CONTROL 0x28
  19. #define CONTROL_TRIGGER_RISING BIT(3)
  20. #define CONTROL_MASK_MSI_X BIT(5)
  21. #define NR_FIC_IRQS 32
  22. MODULE_AUTHOR("Talel Shenhar");
  23. MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
  24. MODULE_LICENSE("GPL v2");
  25. enum al_fic_state {
  26. AL_FIC_UNCONFIGURED = 0,
  27. AL_FIC_CONFIGURED_LEVEL,
  28. AL_FIC_CONFIGURED_RISING_EDGE,
  29. };
  30. struct al_fic {
  31. void __iomem *base;
  32. struct irq_domain *domain;
  33. const char *name;
  34. unsigned int parent_irq;
  35. enum al_fic_state state;
  36. };
  37. static void al_fic_set_trigger(struct al_fic *fic,
  38. struct irq_chip_generic *gc,
  39. enum al_fic_state new_state)
  40. {
  41. irq_flow_handler_t handler;
  42. u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL);
  43. if (new_state == AL_FIC_CONFIGURED_LEVEL) {
  44. handler = handle_level_irq;
  45. control &= ~CONTROL_TRIGGER_RISING;
  46. } else {
  47. handler = handle_edge_irq;
  48. control |= CONTROL_TRIGGER_RISING;
  49. }
  50. gc->chip_types->handler = handler;
  51. fic->state = new_state;
  52. writel_relaxed(control, fic->base + AL_FIC_CONTROL);
  53. }
  54. static int al_fic_irq_set_type(struct irq_data *data, unsigned int flow_type)
  55. {
  56. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
  57. struct al_fic *fic = gc->private;
  58. enum al_fic_state new_state;
  59. int ret = 0;
  60. irq_gc_lock(gc);
  61. if (((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH) &&
  62. ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)) {
  63. pr_debug("fic doesn't support flow type %d\n", flow_type);
  64. ret = -EINVAL;
  65. goto err;
  66. }
  67. new_state = (flow_type & IRQ_TYPE_LEVEL_HIGH) ?
  68. AL_FIC_CONFIGURED_LEVEL : AL_FIC_CONFIGURED_RISING_EDGE;
  69. /*
  70. * A given FIC instance can be either all level or all edge triggered.
  71. * This is generally fixed depending on what pieces of HW it's wired up
  72. * to.
  73. *
  74. * We configure it based on the sensitivity of the first source
  75. * being setup, and reject any subsequent attempt at configuring it in a
  76. * different way.
  77. */
  78. if (fic->state == AL_FIC_UNCONFIGURED) {
  79. al_fic_set_trigger(fic, gc, new_state);
  80. } else if (fic->state != new_state) {
  81. pr_debug("fic %s state already configured to %d\n",
  82. fic->name, fic->state);
  83. ret = -EINVAL;
  84. goto err;
  85. }
  86. err:
  87. irq_gc_unlock(gc);
  88. return ret;
  89. }
  90. static void al_fic_irq_handler(struct irq_desc *desc)
  91. {
  92. struct al_fic *fic = irq_desc_get_handler_data(desc);
  93. struct irq_domain *domain = fic->domain;
  94. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  95. struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
  96. unsigned long pending;
  97. unsigned int irq;
  98. u32 hwirq;
  99. chained_irq_enter(irqchip, desc);
  100. pending = readl_relaxed(fic->base + AL_FIC_CAUSE);
  101. pending &= ~gc->mask_cache;
  102. for_each_set_bit(hwirq, &pending, NR_FIC_IRQS) {
  103. irq = irq_find_mapping(domain, hwirq);
  104. generic_handle_irq(irq);
  105. }
  106. chained_irq_exit(irqchip, desc);
  107. }
  108. static int al_fic_irq_retrigger(struct irq_data *data)
  109. {
  110. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
  111. struct al_fic *fic = gc->private;
  112. writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
  113. return 1;
  114. }
  115. static int al_fic_register(struct device_node *node,
  116. struct al_fic *fic)
  117. {
  118. struct irq_chip_generic *gc;
  119. int ret;
  120. fic->domain = irq_domain_add_linear(node,
  121. NR_FIC_IRQS,
  122. &irq_generic_chip_ops,
  123. fic);
  124. if (!fic->domain) {
  125. pr_err("fail to add irq domain\n");
  126. return -ENOMEM;
  127. }
  128. ret = irq_alloc_domain_generic_chips(fic->domain,
  129. NR_FIC_IRQS,
  130. 1, fic->name,
  131. handle_level_irq,
  132. 0, 0, IRQ_GC_INIT_MASK_CACHE);
  133. if (ret) {
  134. pr_err("fail to allocate generic chip (%d)\n", ret);
  135. goto err_domain_remove;
  136. }
  137. gc = irq_get_domain_generic_chip(fic->domain, 0);
  138. gc->reg_base = fic->base;
  139. gc->chip_types->regs.mask = AL_FIC_MASK;
  140. gc->chip_types->regs.ack = AL_FIC_CAUSE;
  141. gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit;
  142. gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit;
  143. gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit;
  144. gc->chip_types->chip.irq_set_type = al_fic_irq_set_type;
  145. gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger;
  146. gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE;
  147. gc->private = fic;
  148. irq_set_chained_handler_and_data(fic->parent_irq,
  149. al_fic_irq_handler,
  150. fic);
  151. return 0;
  152. err_domain_remove:
  153. irq_domain_remove(fic->domain);
  154. return ret;
  155. }
  156. /*
  157. * al_fic_wire_init() - initialize and configure fic in wire mode
  158. * @of_node: optional pointer to interrupt controller's device tree node.
  159. * @base: mmio to fic register
  160. * @name: name of the fic
  161. * @parent_irq: interrupt of parent
  162. *
  163. * This API will configure the fic hardware to to work in wire mode.
  164. * In wire mode, fic hardware is generating a wire ("wired") interrupt.
  165. * Interrupt can be generated based on positive edge or level - configuration is
  166. * to be determined based on connected hardware to this fic.
  167. */
  168. static struct al_fic *al_fic_wire_init(struct device_node *node,
  169. void __iomem *base,
  170. const char *name,
  171. unsigned int parent_irq)
  172. {
  173. struct al_fic *fic;
  174. int ret;
  175. u32 control = CONTROL_MASK_MSI_X;
  176. fic = kzalloc(sizeof(*fic), GFP_KERNEL);
  177. if (!fic)
  178. return ERR_PTR(-ENOMEM);
  179. fic->base = base;
  180. fic->parent_irq = parent_irq;
  181. fic->name = name;
  182. /* mask out all interrupts */
  183. writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK);
  184. /* clear any pending interrupt */
  185. writel_relaxed(0, fic->base + AL_FIC_CAUSE);
  186. writel_relaxed(control, fic->base + AL_FIC_CONTROL);
  187. ret = al_fic_register(node, fic);
  188. if (ret) {
  189. pr_err("fail to register irqchip\n");
  190. goto err_free;
  191. }
  192. pr_debug("%s initialized successfully in Legacy mode (parent-irq=%u)\n",
  193. fic->name, parent_irq);
  194. return fic;
  195. err_free:
  196. kfree(fic);
  197. return ERR_PTR(ret);
  198. }
  199. static int __init al_fic_init_dt(struct device_node *node,
  200. struct device_node *parent)
  201. {
  202. int ret;
  203. void __iomem *base;
  204. unsigned int parent_irq;
  205. struct al_fic *fic;
  206. if (!parent) {
  207. pr_err("%s: unsupported - device require a parent\n",
  208. node->name);
  209. return -EINVAL;
  210. }
  211. base = of_iomap(node, 0);
  212. if (!base) {
  213. pr_err("%s: fail to map memory\n", node->name);
  214. return -ENOMEM;
  215. }
  216. parent_irq = irq_of_parse_and_map(node, 0);
  217. if (!parent_irq) {
  218. pr_err("%s: fail to map irq\n", node->name);
  219. ret = -EINVAL;
  220. goto err_unmap;
  221. }
  222. fic = al_fic_wire_init(node,
  223. base,
  224. node->name,
  225. parent_irq);
  226. if (IS_ERR(fic)) {
  227. pr_err("%s: fail to initialize irqchip (%lu)\n",
  228. node->name,
  229. PTR_ERR(fic));
  230. ret = PTR_ERR(fic);
  231. goto err_irq_dispose;
  232. }
  233. return 0;
  234. err_irq_dispose:
  235. irq_dispose_mapping(parent_irq);
  236. err_unmap:
  237. iounmap(base);
  238. return ret;
  239. }
  240. IRQCHIP_DECLARE(al_fic, "amazon,al-fic", al_fic_init_dt);