Kconfig 13 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menu "IRQ chip support"
  3. config IRQCHIP
  4. def_bool y
  5. depends on OF_IRQ
  6. config ARM_GIC
  7. bool
  8. select IRQ_DOMAIN_HIERARCHY
  9. select GENERIC_IRQ_MULTI_HANDLER
  10. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  11. config ARM_GIC_PM
  12. bool
  13. depends on PM
  14. select ARM_GIC
  15. config ARM_GIC_MAX_NR
  16. int
  17. depends on ARM_GIC
  18. default 2 if ARCH_REALVIEW
  19. default 1
  20. config ARM_GIC_V2M
  21. bool
  22. depends on PCI
  23. select ARM_GIC
  24. select PCI_MSI
  25. config GIC_NON_BANKED
  26. bool
  27. config ARM_GIC_V3
  28. bool
  29. select GENERIC_IRQ_MULTI_HANDLER
  30. select IRQ_DOMAIN_HIERARCHY
  31. select PARTITION_PERCPU
  32. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  33. config ARM_GIC_V3_ITS
  34. bool
  35. select GENERIC_MSI_IRQ_DOMAIN
  36. default ARM_GIC_V3
  37. config ARM_GIC_V3_ITS_PCI
  38. bool
  39. depends on ARM_GIC_V3_ITS
  40. depends on PCI
  41. depends on PCI_MSI
  42. default ARM_GIC_V3_ITS
  43. config ARM_GIC_V3_ITS_FSL_MC
  44. bool
  45. depends on ARM_GIC_V3_ITS
  46. depends on FSL_MC_BUS
  47. default ARM_GIC_V3_ITS
  48. config ARM_NVIC
  49. bool
  50. select IRQ_DOMAIN_HIERARCHY
  51. select GENERIC_IRQ_CHIP
  52. config ARM_VIC
  53. bool
  54. select IRQ_DOMAIN
  55. select GENERIC_IRQ_MULTI_HANDLER
  56. config ARM_VIC_NR
  57. int
  58. default 4 if ARCH_S5PV210
  59. default 2
  60. depends on ARM_VIC
  61. help
  62. The maximum number of VICs available in the system, for
  63. power management.
  64. config ARMADA_370_XP_IRQ
  65. bool
  66. select GENERIC_IRQ_CHIP
  67. select PCI_MSI if PCI
  68. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  69. config ALPINE_MSI
  70. bool
  71. depends on PCI
  72. select PCI_MSI
  73. select GENERIC_IRQ_CHIP
  74. config AL_FIC
  75. bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
  76. depends on OF || COMPILE_TEST
  77. select GENERIC_IRQ_CHIP
  78. select IRQ_DOMAIN
  79. help
  80. Support Amazon's Annapurna Labs Fabric Interrupt Controller.
  81. config ATMEL_AIC_IRQ
  82. bool
  83. select GENERIC_IRQ_CHIP
  84. select IRQ_DOMAIN
  85. select GENERIC_IRQ_MULTI_HANDLER
  86. select SPARSE_IRQ
  87. config ATMEL_AIC5_IRQ
  88. bool
  89. select GENERIC_IRQ_CHIP
  90. select IRQ_DOMAIN
  91. select GENERIC_IRQ_MULTI_HANDLER
  92. select SPARSE_IRQ
  93. config I8259
  94. bool
  95. select IRQ_DOMAIN
  96. config BCM6345_L1_IRQ
  97. bool
  98. select GENERIC_IRQ_CHIP
  99. select IRQ_DOMAIN
  100. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  101. config BCM7038_L1_IRQ
  102. bool
  103. select GENERIC_IRQ_CHIP
  104. select IRQ_DOMAIN
  105. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  106. config BCM7120_L2_IRQ
  107. bool
  108. select GENERIC_IRQ_CHIP
  109. select IRQ_DOMAIN
  110. config BRCMSTB_L2_IRQ
  111. bool
  112. select GENERIC_IRQ_CHIP
  113. select IRQ_DOMAIN
  114. config DAVINCI_AINTC
  115. bool
  116. select GENERIC_IRQ_CHIP
  117. select IRQ_DOMAIN
  118. config DAVINCI_CP_INTC
  119. bool
  120. select GENERIC_IRQ_CHIP
  121. select IRQ_DOMAIN
  122. config DW_APB_ICTL
  123. bool
  124. select GENERIC_IRQ_CHIP
  125. select IRQ_DOMAIN_HIERARCHY
  126. config FARADAY_FTINTC010
  127. bool
  128. select IRQ_DOMAIN
  129. select GENERIC_IRQ_MULTI_HANDLER
  130. select SPARSE_IRQ
  131. config HISILICON_IRQ_MBIGEN
  132. bool
  133. select ARM_GIC_V3
  134. select ARM_GIC_V3_ITS
  135. config IMGPDC_IRQ
  136. bool
  137. select GENERIC_IRQ_CHIP
  138. select IRQ_DOMAIN
  139. config IXP4XX_IRQ
  140. bool
  141. select IRQ_DOMAIN
  142. select GENERIC_IRQ_MULTI_HANDLER
  143. select SPARSE_IRQ
  144. config MADERA_IRQ
  145. tristate
  146. config IRQ_MIPS_CPU
  147. bool
  148. select GENERIC_IRQ_CHIP
  149. select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
  150. select IRQ_DOMAIN
  151. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  152. config CLPS711X_IRQCHIP
  153. bool
  154. depends on ARCH_CLPS711X
  155. select IRQ_DOMAIN
  156. select GENERIC_IRQ_MULTI_HANDLER
  157. select SPARSE_IRQ
  158. default y
  159. config OMPIC
  160. bool
  161. config OR1K_PIC
  162. bool
  163. select IRQ_DOMAIN
  164. config OMAP_IRQCHIP
  165. bool
  166. select GENERIC_IRQ_CHIP
  167. select IRQ_DOMAIN
  168. config ORION_IRQCHIP
  169. bool
  170. select IRQ_DOMAIN
  171. select GENERIC_IRQ_MULTI_HANDLER
  172. config PIC32_EVIC
  173. bool
  174. select GENERIC_IRQ_CHIP
  175. select IRQ_DOMAIN
  176. config JCORE_AIC
  177. bool "J-Core integrated AIC" if COMPILE_TEST
  178. depends on OF
  179. select IRQ_DOMAIN
  180. help
  181. Support for the J-Core integrated AIC.
  182. config RDA_INTC
  183. bool
  184. select IRQ_DOMAIN
  185. config RENESAS_INTC_IRQPIN
  186. bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
  187. select IRQ_DOMAIN
  188. help
  189. Enable support for the Renesas Interrupt Controller for external
  190. interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
  191. config RENESAS_IRQC
  192. bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
  193. select GENERIC_IRQ_CHIP
  194. select IRQ_DOMAIN
  195. help
  196. Enable support for the Renesas Interrupt Controller for external
  197. devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
  198. config RENESAS_RZA1_IRQC
  199. bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
  200. select IRQ_DOMAIN_HIERARCHY
  201. help
  202. Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
  203. to 8 external interrupts with configurable sense select.
  204. config SL28CPLD_INTC
  205. bool "Kontron sl28cpld IRQ controller"
  206. depends on MFD_SL28CPLD=y || COMPILE_TEST
  207. select REGMAP_IRQ
  208. help
  209. Interrupt controller driver for the board management controller
  210. found on the Kontron sl28 CPLD.
  211. config ST_IRQCHIP
  212. bool
  213. select REGMAP
  214. select MFD_SYSCON
  215. help
  216. Enables SysCfg Controlled IRQs on STi based platforms.
  217. config TANGO_IRQ
  218. bool
  219. select IRQ_DOMAIN
  220. select GENERIC_IRQ_CHIP
  221. config TB10X_IRQC
  222. bool
  223. select IRQ_DOMAIN
  224. select GENERIC_IRQ_CHIP
  225. config TS4800_IRQ
  226. tristate "TS-4800 IRQ controller"
  227. select IRQ_DOMAIN
  228. depends on HAS_IOMEM
  229. depends on SOC_IMX51 || COMPILE_TEST
  230. help
  231. Support for the TS-4800 FPGA IRQ controller
  232. config VERSATILE_FPGA_IRQ
  233. bool
  234. select IRQ_DOMAIN
  235. config VERSATILE_FPGA_IRQ_NR
  236. int
  237. default 4
  238. depends on VERSATILE_FPGA_IRQ
  239. config XTENSA_MX
  240. bool
  241. select IRQ_DOMAIN
  242. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  243. config XILINX_INTC
  244. bool
  245. select IRQ_DOMAIN
  246. config IRQ_CROSSBAR
  247. bool
  248. help
  249. Support for a CROSSBAR ip that precedes the main interrupt controller.
  250. The primary irqchip invokes the crossbar's callback which inturn allocates
  251. a free irq and configures the IP. Thus the peripheral interrupts are
  252. routed to one of the free irqchip interrupt lines.
  253. config KEYSTONE_IRQ
  254. tristate "Keystone 2 IRQ controller IP"
  255. depends on ARCH_KEYSTONE
  256. help
  257. Support for Texas Instruments Keystone 2 IRQ controller IP which
  258. is part of the Keystone 2 IPC mechanism
  259. config MIPS_GIC
  260. bool
  261. select GENERIC_IRQ_IPI
  262. select MIPS_CM
  263. config INGENIC_IRQ
  264. bool
  265. depends on MACH_INGENIC
  266. default y
  267. config INGENIC_TCU_IRQ
  268. bool "Ingenic JZ47xx TCU interrupt controller"
  269. default MACH_INGENIC
  270. depends on MIPS || COMPILE_TEST
  271. select MFD_SYSCON
  272. select GENERIC_IRQ_CHIP
  273. help
  274. Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
  275. JZ47xx SoCs.
  276. If unsure, say N.
  277. config RENESAS_H8300H_INTC
  278. bool
  279. select IRQ_DOMAIN
  280. config RENESAS_H8S_INTC
  281. bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
  282. select IRQ_DOMAIN
  283. help
  284. Enable support for the Renesas H8/300 Interrupt Controller, as found
  285. on Renesas H8S SoCs.
  286. config IMX_GPCV2
  287. bool
  288. select IRQ_DOMAIN
  289. help
  290. Enables the wakeup IRQs for IMX platforms with GPCv2 block
  291. config IRQ_MXS
  292. def_bool y if MACH_ASM9260 || ARCH_MXS
  293. select IRQ_DOMAIN
  294. select STMP_DEVICE
  295. config MSCC_OCELOT_IRQ
  296. bool
  297. select IRQ_DOMAIN
  298. select GENERIC_IRQ_CHIP
  299. config MVEBU_GICP
  300. bool
  301. config MVEBU_ICU
  302. bool
  303. config MVEBU_ODMI
  304. bool
  305. select GENERIC_MSI_IRQ_DOMAIN
  306. config MVEBU_PIC
  307. bool
  308. config MVEBU_SEI
  309. bool
  310. config LS_EXTIRQ
  311. def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
  312. select MFD_SYSCON
  313. config LS_SCFG_MSI
  314. def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
  315. depends on PCI && PCI_MSI
  316. config PARTITION_PERCPU
  317. bool
  318. config EZNPS_GIC
  319. bool "NPS400 Global Interrupt Manager (GIM)"
  320. depends on ARC || (COMPILE_TEST && !64BIT)
  321. select IRQ_DOMAIN
  322. help
  323. Support the EZchip NPS400 global interrupt controller
  324. config STM32_EXTI
  325. bool
  326. select IRQ_DOMAIN
  327. select GENERIC_IRQ_CHIP
  328. config QCOM_IRQ_COMBINER
  329. bool "QCOM IRQ combiner support"
  330. depends on ARCH_QCOM && ACPI
  331. select IRQ_DOMAIN_HIERARCHY
  332. help
  333. Say yes here to add support for the IRQ combiner devices embedded
  334. in Qualcomm Technologies chips.
  335. config IRQ_UNIPHIER_AIDET
  336. bool "UniPhier AIDET support" if COMPILE_TEST
  337. depends on ARCH_UNIPHIER || COMPILE_TEST
  338. default ARCH_UNIPHIER
  339. select IRQ_DOMAIN_HIERARCHY
  340. help
  341. Support for the UniPhier AIDET (ARM Interrupt Detector).
  342. config MESON_IRQ_GPIO
  343. tristate "Meson GPIO Interrupt Multiplexer"
  344. depends on ARCH_MESON || COMPILE_TEST
  345. default ARCH_MESON
  346. select IRQ_DOMAIN_HIERARCHY
  347. help
  348. Support Meson SoC Family GPIO Interrupt Multiplexer
  349. config GOLDFISH_PIC
  350. bool "Goldfish programmable interrupt controller"
  351. depends on MIPS && (GOLDFISH || COMPILE_TEST)
  352. select GENERIC_IRQ_CHIP
  353. select IRQ_DOMAIN
  354. help
  355. Say yes here to enable Goldfish interrupt controller driver used
  356. for Goldfish based virtual platforms.
  357. config QCOM_PDC
  358. tristate "QCOM PDC"
  359. depends on ARCH_QCOM
  360. depends on QCOM_SCM || !QCOM_SCM
  361. select IRQ_DOMAIN_HIERARCHY
  362. help
  363. Power Domain Controller driver to manage and configure wakeup
  364. IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
  365. config CSKY_MPINTC
  366. bool "C-SKY Multi Processor Interrupt Controller"
  367. depends on CSKY
  368. help
  369. Say yes here to enable C-SKY SMP interrupt controller driver used
  370. for C-SKY SMP system.
  371. In fact it's not mmio map in hardware and it uses ld/st to visit the
  372. controller's register inside CPU.
  373. config CSKY_APB_INTC
  374. bool "C-SKY APB Interrupt Controller"
  375. depends on CSKY
  376. help
  377. Say yes here to enable C-SKY APB interrupt controller driver used
  378. by C-SKY single core SOC system. It uses mmio map apb-bus to visit
  379. the controller's register.
  380. config IMX_IRQSTEER
  381. bool "i.MX IRQSTEER support"
  382. depends on ARCH_MXC || COMPILE_TEST
  383. default ARCH_MXC
  384. select IRQ_DOMAIN
  385. help
  386. Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
  387. config IMX_INTMUX
  388. bool "i.MX INTMUX support" if COMPILE_TEST
  389. default y if ARCH_MXC
  390. select IRQ_DOMAIN
  391. help
  392. Support for the i.MX INTMUX interrupt multiplexer.
  393. config LS1X_IRQ
  394. bool "Loongson-1 Interrupt Controller"
  395. depends on MACH_LOONGSON32
  396. default y
  397. select IRQ_DOMAIN
  398. select GENERIC_IRQ_CHIP
  399. help
  400. Support for the Loongson-1 platform Interrupt Controller.
  401. config TI_SCI_INTR_IRQCHIP
  402. bool
  403. depends on TI_SCI_PROTOCOL
  404. select IRQ_DOMAIN_HIERARCHY
  405. help
  406. This enables the irqchip driver support for K3 Interrupt router
  407. over TI System Control Interface available on some new TI's SoCs.
  408. If you wish to use interrupt router irq resources managed by the
  409. TI System Controller, say Y here. Otherwise, say N.
  410. config TI_SCI_INTA_IRQCHIP
  411. bool
  412. depends on TI_SCI_PROTOCOL
  413. select IRQ_DOMAIN_HIERARCHY
  414. select TI_SCI_INTA_MSI_DOMAIN
  415. help
  416. This enables the irqchip driver support for K3 Interrupt aggregator
  417. over TI System Control Interface available on some new TI's SoCs.
  418. If you wish to use interrupt aggregator irq resources managed by the
  419. TI System Controller, say Y here. Otherwise, say N.
  420. config TI_PRUSS_INTC
  421. tristate "TI PRU-ICSS Interrupt Controller"
  422. depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3
  423. select IRQ_DOMAIN
  424. help
  425. This enables support for the PRU-ICSS Local Interrupt Controller
  426. present within a PRU-ICSS subsystem present on various TI SoCs.
  427. The PRUSS INTC enables various interrupts to be routed to multiple
  428. different processors within the SoC.
  429. config RISCV_INTC
  430. bool "RISC-V Local Interrupt Controller"
  431. depends on RISCV
  432. default y
  433. help
  434. This enables support for the per-HART local interrupt controller
  435. found in standard RISC-V systems. The per-HART local interrupt
  436. controller handles timer interrupts, software interrupts, and
  437. hardware interrupts. Without a per-HART local interrupt controller,
  438. a RISC-V system will be unable to handle any interrupts.
  439. If you don't know what to do here, say Y.
  440. config SIFIVE_PLIC
  441. bool "SiFive Platform-Level Interrupt Controller"
  442. depends on RISCV
  443. select IRQ_DOMAIN_HIERARCHY
  444. help
  445. This enables support for the PLIC chip found in SiFive (and
  446. potentially other) RISC-V systems. The PLIC controls devices
  447. interrupts and connects them to each core's local interrupt
  448. controller. Aside from timer and software interrupts, all other
  449. interrupt sources are subordinate to the PLIC.
  450. If you don't know what to do here, say Y.
  451. config EXYNOS_IRQ_COMBINER
  452. bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
  453. depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
  454. help
  455. Say yes here to add support for the IRQ combiner devices embedded
  456. in Samsung Exynos chips.
  457. config LOONGSON_LIOINTC
  458. bool "Loongson Local I/O Interrupt Controller"
  459. depends on MACH_LOONGSON64
  460. default y
  461. select IRQ_DOMAIN
  462. select GENERIC_IRQ_CHIP
  463. help
  464. Support for the Loongson Local I/O Interrupt Controller.
  465. config LOONGSON_HTPIC
  466. bool "Loongson3 HyperTransport PIC Controller"
  467. depends on MACH_LOONGSON64
  468. default y
  469. select IRQ_DOMAIN
  470. select GENERIC_IRQ_CHIP
  471. help
  472. Support for the Loongson-3 HyperTransport PIC Controller.
  473. config LOONGSON_HTVEC
  474. bool "Loongson3 HyperTransport Interrupt Vector Controller"
  475. depends on MACH_LOONGSON64
  476. default MACH_LOONGSON64
  477. select IRQ_DOMAIN_HIERARCHY
  478. help
  479. Support for the Loongson3 HyperTransport Interrupt Vector Controller.
  480. config LOONGSON_PCH_PIC
  481. bool "Loongson PCH PIC Controller"
  482. depends on MACH_LOONGSON64 || COMPILE_TEST
  483. default MACH_LOONGSON64
  484. select IRQ_DOMAIN_HIERARCHY
  485. select IRQ_FASTEOI_HIERARCHY_HANDLERS
  486. help
  487. Support for the Loongson PCH PIC Controller.
  488. config LOONGSON_PCH_MSI
  489. bool "Loongson PCH MSI Controller"
  490. depends on MACH_LOONGSON64 || COMPILE_TEST
  491. depends on PCI
  492. default MACH_LOONGSON64
  493. select IRQ_DOMAIN_HIERARCHY
  494. select PCI_MSI
  495. help
  496. Support for the Loongson PCH MSI Controller.
  497. config MST_IRQ
  498. bool "MStar Interrupt Controller"
  499. depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
  500. default ARCH_MEDIATEK
  501. select IRQ_DOMAIN
  502. select IRQ_DOMAIN_HIERARCHY
  503. help
  504. Support MStar Interrupt Controller.
  505. endmenu