omap-iommu.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * omap iommu: main structures
  4. *
  5. * Copyright (C) 2008-2009 Nokia Corporation
  6. *
  7. * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  8. */
  9. #ifndef _OMAP_IOMMU_H
  10. #define _OMAP_IOMMU_H
  11. #include <linux/bitops.h>
  12. #include <linux/iommu.h>
  13. #define for_each_iotlb_cr(obj, n, __i, cr) \
  14. for (__i = 0; \
  15. (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
  16. __i++)
  17. struct iotlb_entry {
  18. u32 da;
  19. u32 pa;
  20. u32 pgsz, prsvd, valid;
  21. u32 endian, elsz, mixed;
  22. };
  23. /**
  24. * struct omap_iommu_device - omap iommu device data
  25. * @pgtable: page table used by an omap iommu attached to a domain
  26. * @iommu_dev: pointer to store an omap iommu instance attached to a domain
  27. */
  28. struct omap_iommu_device {
  29. u32 *pgtable;
  30. struct omap_iommu *iommu_dev;
  31. };
  32. /**
  33. * struct omap_iommu_domain - omap iommu domain
  34. * @num_iommus: number of iommus in this domain
  35. * @iommus: omap iommu device data for all iommus in this domain
  36. * @dev: Device using this domain.
  37. * @lock: domain lock, should be taken when attaching/detaching
  38. * @domain: generic domain handle used by iommu core code
  39. */
  40. struct omap_iommu_domain {
  41. u32 num_iommus;
  42. struct omap_iommu_device *iommus;
  43. struct device *dev;
  44. spinlock_t lock;
  45. struct iommu_domain domain;
  46. };
  47. struct omap_iommu {
  48. const char *name;
  49. void __iomem *regbase;
  50. struct regmap *syscfg;
  51. struct device *dev;
  52. struct iommu_domain *domain;
  53. struct dentry *debug_dir;
  54. spinlock_t iommu_lock; /* global for this whole object */
  55. /*
  56. * We don't change iopgd for a situation like pgd for a task,
  57. * but share it globally for each iommu.
  58. */
  59. u32 *iopgd;
  60. spinlock_t page_table_lock; /* protect iopgd */
  61. dma_addr_t pd_dma;
  62. int nr_tlb_entries;
  63. void *ctx; /* iommu context: registres saved area */
  64. struct cr_regs *cr_ctx;
  65. u32 num_cr_ctx;
  66. int has_bus_err_back;
  67. u32 id;
  68. struct iommu_device iommu;
  69. struct iommu_group *group;
  70. u8 pwrst;
  71. };
  72. /**
  73. * struct omap_iommu_arch_data - omap iommu private data
  74. * @iommu_dev: handle of the OMAP iommu device
  75. * @dev: handle of the iommu device
  76. *
  77. * This is an omap iommu private data object, which binds an iommu user
  78. * to its iommu device. This object should be placed at the iommu user's
  79. * dev_archdata so generic IOMMU API can be used without having to
  80. * utilize omap-specific plumbing anymore.
  81. */
  82. struct omap_iommu_arch_data {
  83. struct omap_iommu *iommu_dev;
  84. struct device *dev;
  85. };
  86. struct cr_regs {
  87. u32 cam;
  88. u32 ram;
  89. };
  90. struct iotlb_lock {
  91. short base;
  92. short vict;
  93. };
  94. /*
  95. * MMU Register offsets
  96. */
  97. #define MMU_REVISION 0x00
  98. #define MMU_IRQSTATUS 0x18
  99. #define MMU_IRQENABLE 0x1c
  100. #define MMU_WALKING_ST 0x40
  101. #define MMU_CNTL 0x44
  102. #define MMU_FAULT_AD 0x48
  103. #define MMU_TTB 0x4c
  104. #define MMU_LOCK 0x50
  105. #define MMU_LD_TLB 0x54
  106. #define MMU_CAM 0x58
  107. #define MMU_RAM 0x5c
  108. #define MMU_GFLUSH 0x60
  109. #define MMU_FLUSH_ENTRY 0x64
  110. #define MMU_READ_CAM 0x68
  111. #define MMU_READ_RAM 0x6c
  112. #define MMU_EMU_FAULT_AD 0x70
  113. #define MMU_GP_REG 0x88
  114. #define MMU_REG_SIZE 256
  115. /*
  116. * MMU Register bit definitions
  117. */
  118. /* IRQSTATUS & IRQENABLE */
  119. #define MMU_IRQ_MULTIHITFAULT BIT(4)
  120. #define MMU_IRQ_TABLEWALKFAULT BIT(3)
  121. #define MMU_IRQ_EMUMISS BIT(2)
  122. #define MMU_IRQ_TRANSLATIONFAULT BIT(1)
  123. #define MMU_IRQ_TLBMISS BIT(0)
  124. #define __MMU_IRQ_FAULT \
  125. (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
  126. #define MMU_IRQ_MASK \
  127. (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
  128. #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
  129. #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
  130. /* MMU_CNTL */
  131. #define MMU_CNTL_SHIFT 1
  132. #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
  133. #define MMU_CNTL_EML_TLB BIT(3)
  134. #define MMU_CNTL_TWL_EN BIT(2)
  135. #define MMU_CNTL_MMU_EN BIT(1)
  136. /* CAM */
  137. #define MMU_CAM_VATAG_SHIFT 12
  138. #define MMU_CAM_VATAG_MASK \
  139. ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
  140. #define MMU_CAM_P BIT(3)
  141. #define MMU_CAM_V BIT(2)
  142. #define MMU_CAM_PGSZ_MASK 3
  143. #define MMU_CAM_PGSZ_1M (0 << 0)
  144. #define MMU_CAM_PGSZ_64K (1 << 0)
  145. #define MMU_CAM_PGSZ_4K (2 << 0)
  146. #define MMU_CAM_PGSZ_16M (3 << 0)
  147. /* RAM */
  148. #define MMU_RAM_PADDR_SHIFT 12
  149. #define MMU_RAM_PADDR_MASK \
  150. ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
  151. #define MMU_RAM_ENDIAN_SHIFT 9
  152. #define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
  153. #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
  154. #define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT)
  155. #define MMU_RAM_ELSZ_SHIFT 7
  156. #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
  157. #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
  158. #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
  159. #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
  160. #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
  161. #define MMU_RAM_MIXED_SHIFT 6
  162. #define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT)
  163. #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
  164. #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
  165. #define get_cam_va_mask(pgsz) \
  166. (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
  167. ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
  168. ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
  169. ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
  170. /*
  171. * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
  172. */
  173. #define DSP_SYS_REVISION 0x00
  174. #define DSP_SYS_MMU_CONFIG 0x18
  175. #define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
  176. /*
  177. * utilities for super page(16MB, 1MB, 64KB and 4KB)
  178. */
  179. #define iopgsz_max(bytes) \
  180. (((bytes) >= SZ_16M) ? SZ_16M : \
  181. ((bytes) >= SZ_1M) ? SZ_1M : \
  182. ((bytes) >= SZ_64K) ? SZ_64K : \
  183. ((bytes) >= SZ_4K) ? SZ_4K : 0)
  184. #define bytes_to_iopgsz(bytes) \
  185. (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
  186. ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
  187. ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
  188. ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
  189. #define iopgsz_to_bytes(iopgsz) \
  190. (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
  191. ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
  192. ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
  193. ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
  194. #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
  195. /*
  196. * global functions
  197. */
  198. struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
  199. void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
  200. void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
  201. #ifdef CONFIG_OMAP_IOMMU_DEBUG
  202. void omap_iommu_debugfs_init(void);
  203. void omap_iommu_debugfs_exit(void);
  204. void omap_iommu_debugfs_add(struct omap_iommu *obj);
  205. void omap_iommu_debugfs_remove(struct omap_iommu *obj);
  206. #else
  207. static inline void omap_iommu_debugfs_init(void) { }
  208. static inline void omap_iommu_debugfs_exit(void) { }
  209. static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
  210. static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
  211. #endif
  212. /*
  213. * register accessors
  214. */
  215. static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
  216. {
  217. return __raw_readl(obj->regbase + offs);
  218. }
  219. static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
  220. {
  221. __raw_writel(val, obj->regbase + offs);
  222. }
  223. static inline int iotlb_cr_valid(struct cr_regs *cr)
  224. {
  225. if (!cr)
  226. return -EINVAL;
  227. return cr->cam & MMU_CAM_V;
  228. }
  229. #endif /* _OMAP_IOMMU_H */