mtk_iommu_v1.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * IOMMU API for MTK architected m4u v1 implementations
  4. *
  5. * Copyright (c) 2015-2016 MediaTek Inc.
  6. * Author: Honghui Zhang <honghui.zhang@mediatek.com>
  7. *
  8. * Based on driver/iommu/mtk_iommu.c
  9. */
  10. #include <linux/memblock.h>
  11. #include <linux/bug.h>
  12. #include <linux/clk.h>
  13. #include <linux/component.h>
  14. #include <linux/device.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/dma-iommu.h>
  17. #include <linux/err.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/iommu.h>
  21. #include <linux/iopoll.h>
  22. #include <linux/list.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_iommu.h>
  25. #include <linux/of_irq.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/slab.h>
  29. #include <linux/spinlock.h>
  30. #include <asm/barrier.h>
  31. #include <asm/dma-iommu.h>
  32. #include <linux/init.h>
  33. #include <dt-bindings/memory/mt2701-larb-port.h>
  34. #include <soc/mediatek/smi.h>
  35. #include "mtk_iommu.h"
  36. #define REG_MMU_PT_BASE_ADDR 0x000
  37. #define F_ALL_INVLD 0x2
  38. #define F_MMU_INV_RANGE 0x1
  39. #define F_INVLD_EN0 BIT(0)
  40. #define F_INVLD_EN1 BIT(1)
  41. #define F_MMU_FAULT_VA_MSK 0xfffff000
  42. #define MTK_PROTECT_PA_ALIGN 128
  43. #define REG_MMU_CTRL_REG 0x210
  44. #define F_MMU_CTRL_COHERENT_EN BIT(8)
  45. #define REG_MMU_IVRP_PADDR 0x214
  46. #define REG_MMU_INT_CONTROL 0x220
  47. #define F_INT_TRANSLATION_FAULT BIT(0)
  48. #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
  49. #define F_INT_INVALID_PA_FAULT BIT(2)
  50. #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
  51. #define F_INT_TABLE_WALK_FAULT BIT(4)
  52. #define F_INT_TLB_MISS_FAULT BIT(5)
  53. #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6)
  54. #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7)
  55. #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
  56. #define F_INT_CLR_BIT BIT(12)
  57. #define REG_MMU_FAULT_ST 0x224
  58. #define REG_MMU_FAULT_VA 0x228
  59. #define REG_MMU_INVLD_PA 0x22C
  60. #define REG_MMU_INT_ID 0x388
  61. #define REG_MMU_INVALIDATE 0x5c0
  62. #define REG_MMU_INVLD_START_A 0x5c4
  63. #define REG_MMU_INVLD_END_A 0x5c8
  64. #define REG_MMU_INV_SEL 0x5d8
  65. #define REG_MMU_STANDARD_AXI_MODE 0x5e8
  66. #define REG_MMU_DCM 0x5f0
  67. #define F_MMU_DCM_ON BIT(1)
  68. #define REG_MMU_CPE_DONE 0x60c
  69. #define F_DESC_VALID 0x2
  70. #define F_DESC_NONSEC BIT(3)
  71. #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
  72. #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF)
  73. /* MTK generation one iommu HW only support 4K size mapping */
  74. #define MT2701_IOMMU_PAGE_SHIFT 12
  75. #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT)
  76. /*
  77. * MTK m4u support 4GB iova address space, and only support 4K page
  78. * mapping. So the pagetable size should be exactly as 4M.
  79. */
  80. #define M2701_IOMMU_PGT_SIZE SZ_4M
  81. struct mtk_iommu_domain {
  82. spinlock_t pgtlock; /* lock for page table */
  83. struct iommu_domain domain;
  84. u32 *pgt_va;
  85. dma_addr_t pgt_pa;
  86. struct mtk_iommu_data *data;
  87. };
  88. static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
  89. {
  90. return container_of(dom, struct mtk_iommu_domain, domain);
  91. }
  92. static const int mt2701_m4u_in_larb[] = {
  93. LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
  94. LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
  95. };
  96. static inline int mt2701_m4u_to_larb(int id)
  97. {
  98. int i;
  99. for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
  100. if ((id) >= mt2701_m4u_in_larb[i])
  101. return i;
  102. return 0;
  103. }
  104. static inline int mt2701_m4u_to_port(int id)
  105. {
  106. int larb = mt2701_m4u_to_larb(id);
  107. return id - mt2701_m4u_in_larb[larb];
  108. }
  109. static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
  110. {
  111. writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
  112. data->base + REG_MMU_INV_SEL);
  113. writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
  114. wmb(); /* Make sure the tlb flush all done */
  115. }
  116. static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
  117. unsigned long iova, size_t size)
  118. {
  119. int ret;
  120. u32 tmp;
  121. writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
  122. data->base + REG_MMU_INV_SEL);
  123. writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
  124. data->base + REG_MMU_INVLD_START_A);
  125. writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
  126. data->base + REG_MMU_INVLD_END_A);
  127. writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
  128. ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
  129. tmp, tmp != 0, 10, 100000);
  130. if (ret) {
  131. dev_warn(data->dev,
  132. "Partial TLB flush timed out, falling back to full flush\n");
  133. mtk_iommu_tlb_flush_all(data);
  134. }
  135. /* Clear the CPE status */
  136. writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
  137. }
  138. static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
  139. {
  140. struct mtk_iommu_data *data = dev_id;
  141. struct mtk_iommu_domain *dom = data->m4u_dom;
  142. u32 int_state, regval, fault_iova, fault_pa;
  143. unsigned int fault_larb, fault_port;
  144. /* Read error information from registers */
  145. int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
  146. fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
  147. fault_iova &= F_MMU_FAULT_VA_MSK;
  148. fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
  149. regval = readl_relaxed(data->base + REG_MMU_INT_ID);
  150. fault_larb = MT2701_M4U_TF_LARB(regval);
  151. fault_port = MT2701_M4U_TF_PORT(regval);
  152. /*
  153. * MTK v1 iommu HW could not determine whether the fault is read or
  154. * write fault, report as read fault.
  155. */
  156. if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
  157. IOMMU_FAULT_READ))
  158. dev_err_ratelimited(data->dev,
  159. "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
  160. int_state, fault_iova, fault_pa,
  161. fault_larb, fault_port);
  162. /* Interrupt clear */
  163. regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
  164. regval |= F_INT_CLR_BIT;
  165. writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
  166. mtk_iommu_tlb_flush_all(data);
  167. return IRQ_HANDLED;
  168. }
  169. static void mtk_iommu_config(struct mtk_iommu_data *data,
  170. struct device *dev, bool enable)
  171. {
  172. struct mtk_smi_larb_iommu *larb_mmu;
  173. unsigned int larbid, portid;
  174. struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
  175. int i;
  176. for (i = 0; i < fwspec->num_ids; ++i) {
  177. larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
  178. portid = mt2701_m4u_to_port(fwspec->ids[i]);
  179. larb_mmu = &data->larb_imu[larbid];
  180. dev_dbg(dev, "%s iommu port: %d\n",
  181. enable ? "enable" : "disable", portid);
  182. if (enable)
  183. larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
  184. else
  185. larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
  186. }
  187. }
  188. static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
  189. {
  190. struct mtk_iommu_domain *dom = data->m4u_dom;
  191. spin_lock_init(&dom->pgtlock);
  192. dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
  193. &dom->pgt_pa, GFP_KERNEL);
  194. if (!dom->pgt_va)
  195. return -ENOMEM;
  196. writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
  197. dom->data = data;
  198. return 0;
  199. }
  200. static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
  201. {
  202. struct mtk_iommu_domain *dom;
  203. if (type != IOMMU_DOMAIN_UNMANAGED)
  204. return NULL;
  205. dom = kzalloc(sizeof(*dom), GFP_KERNEL);
  206. if (!dom)
  207. return NULL;
  208. return &dom->domain;
  209. }
  210. static void mtk_iommu_domain_free(struct iommu_domain *domain)
  211. {
  212. struct mtk_iommu_domain *dom = to_mtk_domain(domain);
  213. struct mtk_iommu_data *data = dom->data;
  214. dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
  215. dom->pgt_va, dom->pgt_pa);
  216. kfree(to_mtk_domain(domain));
  217. }
  218. static int mtk_iommu_attach_device(struct iommu_domain *domain,
  219. struct device *dev)
  220. {
  221. struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
  222. struct mtk_iommu_domain *dom = to_mtk_domain(domain);
  223. struct dma_iommu_mapping *mtk_mapping;
  224. int ret;
  225. /* Only allow the domain created internally. */
  226. mtk_mapping = data->mapping;
  227. if (mtk_mapping->domain != domain)
  228. return 0;
  229. if (!data->m4u_dom) {
  230. data->m4u_dom = dom;
  231. ret = mtk_iommu_domain_finalise(data);
  232. if (ret) {
  233. data->m4u_dom = NULL;
  234. return ret;
  235. }
  236. }
  237. mtk_iommu_config(data, dev, true);
  238. return 0;
  239. }
  240. static void mtk_iommu_detach_device(struct iommu_domain *domain,
  241. struct device *dev)
  242. {
  243. struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
  244. mtk_iommu_config(data, dev, false);
  245. }
  246. static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
  247. phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
  248. {
  249. struct mtk_iommu_domain *dom = to_mtk_domain(domain);
  250. unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
  251. unsigned long flags;
  252. unsigned int i;
  253. u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
  254. u32 pabase = (u32)paddr;
  255. int map_size = 0;
  256. spin_lock_irqsave(&dom->pgtlock, flags);
  257. for (i = 0; i < page_num; i++) {
  258. if (pgt_base_iova[i]) {
  259. memset(pgt_base_iova, 0, i * sizeof(u32));
  260. break;
  261. }
  262. pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
  263. pabase += MT2701_IOMMU_PAGE_SIZE;
  264. map_size += MT2701_IOMMU_PAGE_SIZE;
  265. }
  266. spin_unlock_irqrestore(&dom->pgtlock, flags);
  267. mtk_iommu_tlb_flush_range(dom->data, iova, size);
  268. return map_size == size ? 0 : -EEXIST;
  269. }
  270. static size_t mtk_iommu_unmap(struct iommu_domain *domain,
  271. unsigned long iova, size_t size,
  272. struct iommu_iotlb_gather *gather)
  273. {
  274. struct mtk_iommu_domain *dom = to_mtk_domain(domain);
  275. unsigned long flags;
  276. u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
  277. unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
  278. spin_lock_irqsave(&dom->pgtlock, flags);
  279. memset(pgt_base_iova, 0, page_num * sizeof(u32));
  280. spin_unlock_irqrestore(&dom->pgtlock, flags);
  281. mtk_iommu_tlb_flush_range(dom->data, iova, size);
  282. return size;
  283. }
  284. static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
  285. dma_addr_t iova)
  286. {
  287. struct mtk_iommu_domain *dom = to_mtk_domain(domain);
  288. unsigned long flags;
  289. phys_addr_t pa;
  290. spin_lock_irqsave(&dom->pgtlock, flags);
  291. pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
  292. pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
  293. spin_unlock_irqrestore(&dom->pgtlock, flags);
  294. return pa;
  295. }
  296. static const struct iommu_ops mtk_iommu_ops;
  297. /*
  298. * MTK generation one iommu HW only support one iommu domain, and all the client
  299. * sharing the same iova address space.
  300. */
  301. static int mtk_iommu_create_mapping(struct device *dev,
  302. struct of_phandle_args *args)
  303. {
  304. struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
  305. struct mtk_iommu_data *data;
  306. struct platform_device *m4updev;
  307. struct dma_iommu_mapping *mtk_mapping;
  308. int ret;
  309. if (args->args_count != 1) {
  310. dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
  311. args->args_count);
  312. return -EINVAL;
  313. }
  314. if (!fwspec) {
  315. ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops);
  316. if (ret)
  317. return ret;
  318. fwspec = dev_iommu_fwspec_get(dev);
  319. } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
  320. return -EINVAL;
  321. }
  322. if (!dev_iommu_priv_get(dev)) {
  323. /* Get the m4u device */
  324. m4updev = of_find_device_by_node(args->np);
  325. if (WARN_ON(!m4updev))
  326. return -EINVAL;
  327. dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
  328. }
  329. ret = iommu_fwspec_add_ids(dev, args->args, 1);
  330. if (ret)
  331. return ret;
  332. data = dev_iommu_priv_get(dev);
  333. mtk_mapping = data->mapping;
  334. if (!mtk_mapping) {
  335. /* MTK iommu support 4GB iova address space. */
  336. mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
  337. 0, 1ULL << 32);
  338. if (IS_ERR(mtk_mapping))
  339. return PTR_ERR(mtk_mapping);
  340. data->mapping = mtk_mapping;
  341. }
  342. return 0;
  343. }
  344. static int mtk_iommu_def_domain_type(struct device *dev)
  345. {
  346. return IOMMU_DOMAIN_UNMANAGED;
  347. }
  348. static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
  349. {
  350. struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
  351. struct of_phandle_args iommu_spec;
  352. struct of_phandle_iterator it;
  353. struct mtk_iommu_data *data;
  354. int err;
  355. of_for_each_phandle(&it, err, dev->of_node, "iommus",
  356. "#iommu-cells", -1) {
  357. int count = of_phandle_iterator_args(&it, iommu_spec.args,
  358. MAX_PHANDLE_ARGS);
  359. iommu_spec.np = of_node_get(it.node);
  360. iommu_spec.args_count = count;
  361. mtk_iommu_create_mapping(dev, &iommu_spec);
  362. /* dev->iommu_fwspec might have changed */
  363. fwspec = dev_iommu_fwspec_get(dev);
  364. of_node_put(iommu_spec.np);
  365. }
  366. if (!fwspec || fwspec->ops != &mtk_iommu_ops)
  367. return ERR_PTR(-ENODEV); /* Not a iommu client device */
  368. data = dev_iommu_priv_get(dev);
  369. return &data->iommu;
  370. }
  371. static void mtk_iommu_probe_finalize(struct device *dev)
  372. {
  373. struct dma_iommu_mapping *mtk_mapping;
  374. struct mtk_iommu_data *data;
  375. int err;
  376. data = dev_iommu_priv_get(dev);
  377. mtk_mapping = data->mapping;
  378. err = arm_iommu_attach_device(dev, mtk_mapping);
  379. if (err)
  380. dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
  381. }
  382. static void mtk_iommu_release_device(struct device *dev)
  383. {
  384. struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
  385. if (!fwspec || fwspec->ops != &mtk_iommu_ops)
  386. return;
  387. iommu_fwspec_free(dev);
  388. }
  389. static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
  390. {
  391. u32 regval;
  392. int ret;
  393. ret = clk_prepare_enable(data->bclk);
  394. if (ret) {
  395. dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
  396. return ret;
  397. }
  398. regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
  399. writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
  400. regval = F_INT_TRANSLATION_FAULT |
  401. F_INT_MAIN_MULTI_HIT_FAULT |
  402. F_INT_INVALID_PA_FAULT |
  403. F_INT_ENTRY_REPLACEMENT_FAULT |
  404. F_INT_TABLE_WALK_FAULT |
  405. F_INT_TLB_MISS_FAULT |
  406. F_INT_PFH_DMA_FIFO_OVERFLOW |
  407. F_INT_MISS_DMA_FIFO_OVERFLOW;
  408. writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
  409. /* protect memory,hw will write here while translation fault */
  410. writel_relaxed(data->protect_base,
  411. data->base + REG_MMU_IVRP_PADDR);
  412. writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
  413. if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
  414. dev_name(data->dev), (void *)data)) {
  415. writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
  416. clk_disable_unprepare(data->bclk);
  417. dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
  418. return -ENODEV;
  419. }
  420. return 0;
  421. }
  422. static const struct iommu_ops mtk_iommu_ops = {
  423. .domain_alloc = mtk_iommu_domain_alloc,
  424. .domain_free = mtk_iommu_domain_free,
  425. .attach_dev = mtk_iommu_attach_device,
  426. .detach_dev = mtk_iommu_detach_device,
  427. .map = mtk_iommu_map,
  428. .unmap = mtk_iommu_unmap,
  429. .iova_to_phys = mtk_iommu_iova_to_phys,
  430. .probe_device = mtk_iommu_probe_device,
  431. .probe_finalize = mtk_iommu_probe_finalize,
  432. .release_device = mtk_iommu_release_device,
  433. .def_domain_type = mtk_iommu_def_domain_type,
  434. .device_group = generic_device_group,
  435. .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT,
  436. };
  437. static const struct of_device_id mtk_iommu_of_ids[] = {
  438. { .compatible = "mediatek,mt2701-m4u", },
  439. {}
  440. };
  441. static const struct component_master_ops mtk_iommu_com_ops = {
  442. .bind = mtk_iommu_bind,
  443. .unbind = mtk_iommu_unbind,
  444. };
  445. static int mtk_iommu_probe(struct platform_device *pdev)
  446. {
  447. struct mtk_iommu_data *data;
  448. struct device *dev = &pdev->dev;
  449. struct resource *res;
  450. struct component_match *match = NULL;
  451. struct of_phandle_args larb_spec;
  452. struct of_phandle_iterator it;
  453. void *protect;
  454. int larb_nr, ret, err;
  455. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  456. if (!data)
  457. return -ENOMEM;
  458. data->dev = dev;
  459. /* Protect memory. HW will access here while translation fault.*/
  460. protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
  461. GFP_KERNEL | GFP_DMA);
  462. if (!protect)
  463. return -ENOMEM;
  464. data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
  465. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  466. data->base = devm_ioremap_resource(dev, res);
  467. if (IS_ERR(data->base))
  468. return PTR_ERR(data->base);
  469. data->irq = platform_get_irq(pdev, 0);
  470. if (data->irq < 0)
  471. return data->irq;
  472. data->bclk = devm_clk_get(dev, "bclk");
  473. if (IS_ERR(data->bclk))
  474. return PTR_ERR(data->bclk);
  475. larb_nr = 0;
  476. of_for_each_phandle(&it, err, dev->of_node,
  477. "mediatek,larbs", NULL, 0) {
  478. struct platform_device *plarbdev;
  479. int count = of_phandle_iterator_args(&it, larb_spec.args,
  480. MAX_PHANDLE_ARGS);
  481. if (count)
  482. continue;
  483. larb_spec.np = of_node_get(it.node);
  484. if (!of_device_is_available(larb_spec.np))
  485. continue;
  486. plarbdev = of_find_device_by_node(larb_spec.np);
  487. if (!plarbdev) {
  488. plarbdev = of_platform_device_create(
  489. larb_spec.np, NULL,
  490. platform_bus_type.dev_root);
  491. if (!plarbdev) {
  492. of_node_put(larb_spec.np);
  493. return -EPROBE_DEFER;
  494. }
  495. }
  496. data->larb_imu[larb_nr].dev = &plarbdev->dev;
  497. component_match_add_release(dev, &match, release_of,
  498. compare_of, larb_spec.np);
  499. larb_nr++;
  500. }
  501. platform_set_drvdata(pdev, data);
  502. ret = mtk_iommu_hw_init(data);
  503. if (ret)
  504. return ret;
  505. ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
  506. dev_name(&pdev->dev));
  507. if (ret)
  508. return ret;
  509. iommu_device_set_ops(&data->iommu, &mtk_iommu_ops);
  510. ret = iommu_device_register(&data->iommu);
  511. if (ret)
  512. return ret;
  513. if (!iommu_present(&platform_bus_type))
  514. bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
  515. return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
  516. }
  517. static int mtk_iommu_remove(struct platform_device *pdev)
  518. {
  519. struct mtk_iommu_data *data = platform_get_drvdata(pdev);
  520. iommu_device_sysfs_remove(&data->iommu);
  521. iommu_device_unregister(&data->iommu);
  522. if (iommu_present(&platform_bus_type))
  523. bus_set_iommu(&platform_bus_type, NULL);
  524. clk_disable_unprepare(data->bclk);
  525. devm_free_irq(&pdev->dev, data->irq, data);
  526. component_master_del(&pdev->dev, &mtk_iommu_com_ops);
  527. return 0;
  528. }
  529. static int __maybe_unused mtk_iommu_suspend(struct device *dev)
  530. {
  531. struct mtk_iommu_data *data = dev_get_drvdata(dev);
  532. struct mtk_iommu_suspend_reg *reg = &data->reg;
  533. void __iomem *base = data->base;
  534. reg->standard_axi_mode = readl_relaxed(base +
  535. REG_MMU_STANDARD_AXI_MODE);
  536. reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
  537. reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
  538. reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
  539. return 0;
  540. }
  541. static int __maybe_unused mtk_iommu_resume(struct device *dev)
  542. {
  543. struct mtk_iommu_data *data = dev_get_drvdata(dev);
  544. struct mtk_iommu_suspend_reg *reg = &data->reg;
  545. void __iomem *base = data->base;
  546. writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
  547. writel_relaxed(reg->standard_axi_mode,
  548. base + REG_MMU_STANDARD_AXI_MODE);
  549. writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
  550. writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
  551. writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
  552. writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
  553. return 0;
  554. }
  555. static const struct dev_pm_ops mtk_iommu_pm_ops = {
  556. SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
  557. };
  558. static struct platform_driver mtk_iommu_driver = {
  559. .probe = mtk_iommu_probe,
  560. .remove = mtk_iommu_remove,
  561. .driver = {
  562. .name = "mtk-iommu-v1",
  563. .of_match_table = mtk_iommu_of_ids,
  564. .pm = &mtk_iommu_pm_ops,
  565. }
  566. };
  567. static int __init m4u_init(void)
  568. {
  569. return platform_driver_register(&mtk_iommu_driver);
  570. }
  571. subsys_initcall(m4u_init);