msm_iommu.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  3. */
  4. #ifndef MSM_IOMMU_H
  5. #define MSM_IOMMU_H
  6. #include <linux/interrupt.h>
  7. #include <linux/iommu.h>
  8. #include <linux/clk.h>
  9. /* Sharability attributes of MSM IOMMU mappings */
  10. #define MSM_IOMMU_ATTR_NON_SH 0x0
  11. #define MSM_IOMMU_ATTR_SH 0x4
  12. /* Cacheability attributes of MSM IOMMU mappings */
  13. #define MSM_IOMMU_ATTR_NONCACHED 0x0
  14. #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
  15. #define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
  16. #define MSM_IOMMU_ATTR_CACHED_WT 0x3
  17. /* Mask for the cache policy attribute */
  18. #define MSM_IOMMU_CP_MASK 0x03
  19. /* Maximum number of Machine IDs that we are allowing to be mapped to the same
  20. * context bank. The number of MIDs mapped to the same CB does not affect
  21. * performance, but there is a practical limit on how many distinct MIDs may
  22. * be present. These mappings are typically determined at design time and are
  23. * not expected to change at run time.
  24. */
  25. #define MAX_NUM_MIDS 32
  26. /* Maximum number of context banks that can be present in IOMMU */
  27. #define IOMMU_MAX_CBS 128
  28. /**
  29. * struct msm_iommu_dev - a single IOMMU hardware instance
  30. * ncb Number of context banks present on this IOMMU HW instance
  31. * dev: IOMMU device
  32. * irq: Interrupt number
  33. * clk: The bus clock for this IOMMU hardware instance
  34. * pclk: The clock for the IOMMU bus interconnect
  35. * dev_node: list head in qcom_iommu_device_list
  36. * dom_node: list head for domain
  37. * ctx_list: list of 'struct msm_iommu_ctx_dev'
  38. * context_map: Bitmap to track allocated context banks
  39. */
  40. struct msm_iommu_dev {
  41. void __iomem *base;
  42. int ncb;
  43. struct device *dev;
  44. int irq;
  45. struct clk *clk;
  46. struct clk *pclk;
  47. struct list_head dev_node;
  48. struct list_head dom_node;
  49. struct list_head ctx_list;
  50. DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);
  51. struct iommu_device iommu;
  52. };
  53. /**
  54. * struct msm_iommu_ctx_dev - an IOMMU context bank instance
  55. * of_node node ptr of client device
  56. * num Index of this context bank within the hardware
  57. * mids List of Machine IDs that are to be mapped into this context
  58. * bank, terminated by -1. The MID is a set of signals on the
  59. * AXI bus that identifies the function associated with a specific
  60. * memory request. (See ARM spec).
  61. * num_mids Total number of mids
  62. * node list head in ctx_list
  63. */
  64. struct msm_iommu_ctx_dev {
  65. struct device_node *of_node;
  66. int num;
  67. int mids[MAX_NUM_MIDS];
  68. int num_mids;
  69. struct list_head list;
  70. };
  71. /*
  72. * Interrupt handler for the IOMMU context fault interrupt. Hooking the
  73. * interrupt is not supported in the API yet, but this will print an error
  74. * message and dump useful IOMMU registers.
  75. */
  76. irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
  77. #endif