fsl_pamu.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  5. */
  6. #define pr_fmt(fmt) "fsl-pamu: %s: " fmt, __func__
  7. #include "fsl_pamu.h"
  8. #include <linux/fsl/guts.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/genalloc.h>
  11. #include <asm/mpc85xx.h>
  12. /* define indexes for each operation mapping scenario */
  13. #define OMI_QMAN 0x00
  14. #define OMI_FMAN 0x01
  15. #define OMI_QMAN_PRIV 0x02
  16. #define OMI_CAAM 0x03
  17. #define make64(high, low) (((u64)(high) << 32) | (low))
  18. struct pamu_isr_data {
  19. void __iomem *pamu_reg_base; /* Base address of PAMU regs */
  20. unsigned int count; /* The number of PAMUs */
  21. };
  22. static struct paace *ppaact;
  23. static struct paace *spaact;
  24. static bool probed; /* Has PAMU been probed? */
  25. /*
  26. * Table for matching compatible strings, for device tree
  27. * guts node, for QorIQ SOCs.
  28. * "fsl,qoriq-device-config-2.0" corresponds to T4 & B4
  29. * SOCs. For the older SOCs "fsl,qoriq-device-config-1.0"
  30. * string would be used.
  31. */
  32. static const struct of_device_id guts_device_ids[] = {
  33. { .compatible = "fsl,qoriq-device-config-1.0", },
  34. { .compatible = "fsl,qoriq-device-config-2.0", },
  35. {}
  36. };
  37. /*
  38. * Table for matching compatible strings, for device tree
  39. * L3 cache controller node.
  40. * "fsl,t4240-l3-cache-controller" corresponds to T4,
  41. * "fsl,b4860-l3-cache-controller" corresponds to B4 &
  42. * "fsl,p4080-l3-cache-controller" corresponds to other,
  43. * SOCs.
  44. */
  45. static const struct of_device_id l3_device_ids[] = {
  46. { .compatible = "fsl,t4240-l3-cache-controller", },
  47. { .compatible = "fsl,b4860-l3-cache-controller", },
  48. { .compatible = "fsl,p4080-l3-cache-controller", },
  49. {}
  50. };
  51. /* maximum subwindows permitted per liodn */
  52. static u32 max_subwindow_count;
  53. /* Pool for fspi allocation */
  54. static struct gen_pool *spaace_pool;
  55. /**
  56. * pamu_get_max_subwin_cnt() - Return the maximum supported
  57. * subwindow count per liodn.
  58. *
  59. */
  60. u32 pamu_get_max_subwin_cnt(void)
  61. {
  62. return max_subwindow_count;
  63. }
  64. /**
  65. * pamu_get_ppaace() - Return the primary PACCE
  66. * @liodn: liodn PAACT index for desired PAACE
  67. *
  68. * Returns the ppace pointer upon success else return
  69. * null.
  70. */
  71. static struct paace *pamu_get_ppaace(int liodn)
  72. {
  73. if (!ppaact || liodn >= PAACE_NUMBER_ENTRIES) {
  74. pr_debug("PPAACT doesn't exist\n");
  75. return NULL;
  76. }
  77. return &ppaact[liodn];
  78. }
  79. /**
  80. * pamu_enable_liodn() - Set valid bit of PACCE
  81. * @liodn: liodn PAACT index for desired PAACE
  82. *
  83. * Returns 0 upon success else error code < 0 returned
  84. */
  85. int pamu_enable_liodn(int liodn)
  86. {
  87. struct paace *ppaace;
  88. ppaace = pamu_get_ppaace(liodn);
  89. if (!ppaace) {
  90. pr_debug("Invalid primary paace entry\n");
  91. return -ENOENT;
  92. }
  93. if (!get_bf(ppaace->addr_bitfields, PPAACE_AF_WSE)) {
  94. pr_debug("liodn %d not configured\n", liodn);
  95. return -EINVAL;
  96. }
  97. /* Ensure that all other stores to the ppaace complete first */
  98. mb();
  99. set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_VALID);
  100. mb();
  101. return 0;
  102. }
  103. /**
  104. * pamu_disable_liodn() - Clears valid bit of PACCE
  105. * @liodn: liodn PAACT index for desired PAACE
  106. *
  107. * Returns 0 upon success else error code < 0 returned
  108. */
  109. int pamu_disable_liodn(int liodn)
  110. {
  111. struct paace *ppaace;
  112. ppaace = pamu_get_ppaace(liodn);
  113. if (!ppaace) {
  114. pr_debug("Invalid primary paace entry\n");
  115. return -ENOENT;
  116. }
  117. set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID);
  118. mb();
  119. return 0;
  120. }
  121. /* Derive the window size encoding for a particular PAACE entry */
  122. static unsigned int map_addrspace_size_to_wse(phys_addr_t addrspace_size)
  123. {
  124. /* Bug if not a power of 2 */
  125. BUG_ON(addrspace_size & (addrspace_size - 1));
  126. /* window size is 2^(WSE+1) bytes */
  127. return fls64(addrspace_size) - 2;
  128. }
  129. /* Derive the PAACE window count encoding for the subwindow count */
  130. static unsigned int map_subwindow_cnt_to_wce(u32 subwindow_cnt)
  131. {
  132. /* window count is 2^(WCE+1) bytes */
  133. return __ffs(subwindow_cnt) - 1;
  134. }
  135. /*
  136. * Set the PAACE type as primary and set the coherency required domain
  137. * attribute
  138. */
  139. static void pamu_init_ppaace(struct paace *ppaace)
  140. {
  141. set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
  142. set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
  143. PAACE_M_COHERENCE_REQ);
  144. }
  145. /*
  146. * Set the PAACE type as secondary and set the coherency required domain
  147. * attribute.
  148. */
  149. static void pamu_init_spaace(struct paace *spaace)
  150. {
  151. set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
  152. set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
  153. PAACE_M_COHERENCE_REQ);
  154. }
  155. /*
  156. * Return the spaace (corresponding to the secondary window index)
  157. * for a particular ppaace.
  158. */
  159. static struct paace *pamu_get_spaace(struct paace *paace, u32 wnum)
  160. {
  161. u32 subwin_cnt;
  162. struct paace *spaace = NULL;
  163. subwin_cnt = 1UL << (get_bf(paace->impl_attr, PAACE_IA_WCE) + 1);
  164. if (wnum < subwin_cnt)
  165. spaace = &spaact[paace->fspi + wnum];
  166. else
  167. pr_debug("secondary paace out of bounds\n");
  168. return spaace;
  169. }
  170. /**
  171. * pamu_get_fspi_and_allocate() - Allocates fspi index and reserves subwindows
  172. * required for primary PAACE in the secondary
  173. * PAACE table.
  174. * @subwin_cnt: Number of subwindows to be reserved.
  175. *
  176. * A PPAACE entry may have a number of associated subwindows. A subwindow
  177. * corresponds to a SPAACE entry in the SPAACT table. Each PAACE entry stores
  178. * the index (fspi) of the first SPAACE entry in the SPAACT table. This
  179. * function returns the index of the first SPAACE entry. The remaining
  180. * SPAACE entries are reserved contiguously from that index.
  181. *
  182. * Returns a valid fspi index in the range of 0 - SPAACE_NUMBER_ENTRIES on success.
  183. * If no SPAACE entry is available or the allocator can not reserve the required
  184. * number of contiguous entries function returns ULONG_MAX indicating a failure.
  185. *
  186. */
  187. static unsigned long pamu_get_fspi_and_allocate(u32 subwin_cnt)
  188. {
  189. unsigned long spaace_addr;
  190. spaace_addr = gen_pool_alloc(spaace_pool, subwin_cnt * sizeof(struct paace));
  191. if (!spaace_addr)
  192. return ULONG_MAX;
  193. return (spaace_addr - (unsigned long)spaact) / (sizeof(struct paace));
  194. }
  195. /* Release the subwindows reserved for a particular LIODN */
  196. void pamu_free_subwins(int liodn)
  197. {
  198. struct paace *ppaace;
  199. u32 subwin_cnt, size;
  200. ppaace = pamu_get_ppaace(liodn);
  201. if (!ppaace) {
  202. pr_debug("Invalid liodn entry\n");
  203. return;
  204. }
  205. if (get_bf(ppaace->addr_bitfields, PPAACE_AF_MW)) {
  206. subwin_cnt = 1UL << (get_bf(ppaace->impl_attr, PAACE_IA_WCE) + 1);
  207. size = (subwin_cnt - 1) * sizeof(struct paace);
  208. gen_pool_free(spaace_pool, (unsigned long)&spaact[ppaace->fspi], size);
  209. set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);
  210. }
  211. }
  212. /*
  213. * Function used for updating stash destination for the coressponding
  214. * LIODN.
  215. */
  216. int pamu_update_paace_stash(int liodn, u32 subwin, u32 value)
  217. {
  218. struct paace *paace;
  219. paace = pamu_get_ppaace(liodn);
  220. if (!paace) {
  221. pr_debug("Invalid liodn entry\n");
  222. return -ENOENT;
  223. }
  224. if (subwin) {
  225. paace = pamu_get_spaace(paace, subwin - 1);
  226. if (!paace)
  227. return -ENOENT;
  228. }
  229. set_bf(paace->impl_attr, PAACE_IA_CID, value);
  230. mb();
  231. return 0;
  232. }
  233. /* Disable a subwindow corresponding to the LIODN */
  234. int pamu_disable_spaace(int liodn, u32 subwin)
  235. {
  236. struct paace *paace;
  237. paace = pamu_get_ppaace(liodn);
  238. if (!paace) {
  239. pr_debug("Invalid liodn entry\n");
  240. return -ENOENT;
  241. }
  242. if (subwin) {
  243. paace = pamu_get_spaace(paace, subwin - 1);
  244. if (!paace)
  245. return -ENOENT;
  246. set_bf(paace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID);
  247. } else {
  248. set_bf(paace->addr_bitfields, PAACE_AF_AP,
  249. PAACE_AP_PERMS_DENIED);
  250. }
  251. mb();
  252. return 0;
  253. }
  254. /**
  255. * pamu_config_paace() - Sets up PPAACE entry for specified liodn
  256. *
  257. * @liodn: Logical IO device number
  258. * @win_addr: starting address of DSA window
  259. * @win-size: size of DSA window
  260. * @omi: Operation mapping index -- if ~omi == 0 then omi not defined
  261. * @rpn: real (true physical) page number
  262. * @stashid: cache stash id for associated cpu -- if ~stashid == 0 then
  263. * stashid not defined
  264. * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then
  265. * snoopid not defined
  266. * @subwin_cnt: number of sub-windows
  267. * @prot: window permissions
  268. *
  269. * Returns 0 upon success else error code < 0 returned
  270. */
  271. int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size,
  272. u32 omi, unsigned long rpn, u32 snoopid, u32 stashid,
  273. u32 subwin_cnt, int prot)
  274. {
  275. struct paace *ppaace;
  276. unsigned long fspi;
  277. if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE) {
  278. pr_debug("window size too small or not a power of two %pa\n",
  279. &win_size);
  280. return -EINVAL;
  281. }
  282. if (win_addr & (win_size - 1)) {
  283. pr_debug("window address is not aligned with window size\n");
  284. return -EINVAL;
  285. }
  286. ppaace = pamu_get_ppaace(liodn);
  287. if (!ppaace)
  288. return -ENOENT;
  289. /* window size is 2^(WSE+1) bytes */
  290. set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE,
  291. map_addrspace_size_to_wse(win_size));
  292. pamu_init_ppaace(ppaace);
  293. ppaace->wbah = win_addr >> (PAMU_PAGE_SHIFT + 20);
  294. set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL,
  295. (win_addr >> PAMU_PAGE_SHIFT));
  296. /* set up operation mapping if it's configured */
  297. if (omi < OME_NUMBER_ENTRIES) {
  298. set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
  299. ppaace->op_encode.index_ot.omi = omi;
  300. } else if (~omi != 0) {
  301. pr_debug("bad operation mapping index: %d\n", omi);
  302. return -EINVAL;
  303. }
  304. /* configure stash id */
  305. if (~stashid != 0)
  306. set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid);
  307. /* configure snoop id */
  308. if (~snoopid != 0)
  309. ppaace->domain_attr.to_host.snpid = snoopid;
  310. if (subwin_cnt) {
  311. /* The first entry is in the primary PAACE instead */
  312. fspi = pamu_get_fspi_and_allocate(subwin_cnt - 1);
  313. if (fspi == ULONG_MAX) {
  314. pr_debug("spaace indexes exhausted\n");
  315. return -EINVAL;
  316. }
  317. /* window count is 2^(WCE+1) bytes */
  318. set_bf(ppaace->impl_attr, PAACE_IA_WCE,
  319. map_subwindow_cnt_to_wce(subwin_cnt));
  320. set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1);
  321. ppaace->fspi = fspi;
  322. } else {
  323. set_bf(ppaace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
  324. ppaace->twbah = rpn >> 20;
  325. set_bf(ppaace->win_bitfields, PAACE_WIN_TWBAL, rpn);
  326. set_bf(ppaace->addr_bitfields, PAACE_AF_AP, prot);
  327. set_bf(ppaace->impl_attr, PAACE_IA_WCE, 0);
  328. set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);
  329. }
  330. mb();
  331. return 0;
  332. }
  333. /**
  334. * pamu_config_spaace() - Sets up SPAACE entry for specified subwindow
  335. *
  336. * @liodn: Logical IO device number
  337. * @subwin_cnt: number of sub-windows associated with dma-window
  338. * @subwin: subwindow index
  339. * @subwin_size: size of subwindow
  340. * @omi: Operation mapping index
  341. * @rpn: real (true physical) page number
  342. * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then
  343. * snoopid not defined
  344. * @stashid: cache stash id for associated cpu
  345. * @enable: enable/disable subwindow after reconfiguration
  346. * @prot: sub window permissions
  347. *
  348. * Returns 0 upon success else error code < 0 returned
  349. */
  350. int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin,
  351. phys_addr_t subwin_size, u32 omi, unsigned long rpn,
  352. u32 snoopid, u32 stashid, int enable, int prot)
  353. {
  354. struct paace *paace;
  355. /* setup sub-windows */
  356. if (!subwin_cnt) {
  357. pr_debug("Invalid subwindow count\n");
  358. return -EINVAL;
  359. }
  360. paace = pamu_get_ppaace(liodn);
  361. if (subwin > 0 && subwin < subwin_cnt && paace) {
  362. paace = pamu_get_spaace(paace, subwin - 1);
  363. if (paace && !(paace->addr_bitfields & PAACE_V_VALID)) {
  364. pamu_init_spaace(paace);
  365. set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn);
  366. }
  367. }
  368. if (!paace) {
  369. pr_debug("Invalid liodn entry\n");
  370. return -ENOENT;
  371. }
  372. if ((subwin_size & (subwin_size - 1)) || subwin_size < PAMU_PAGE_SIZE) {
  373. pr_debug("subwindow size out of range, or not a power of 2\n");
  374. return -EINVAL;
  375. }
  376. if (rpn == ULONG_MAX) {
  377. pr_debug("real page number out of range\n");
  378. return -EINVAL;
  379. }
  380. /* window size is 2^(WSE+1) bytes */
  381. set_bf(paace->win_bitfields, PAACE_WIN_SWSE,
  382. map_addrspace_size_to_wse(subwin_size));
  383. set_bf(paace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
  384. paace->twbah = rpn >> 20;
  385. set_bf(paace->win_bitfields, PAACE_WIN_TWBAL, rpn);
  386. set_bf(paace->addr_bitfields, PAACE_AF_AP, prot);
  387. /* configure snoop id */
  388. if (~snoopid != 0)
  389. paace->domain_attr.to_host.snpid = snoopid;
  390. /* set up operation mapping if it's configured */
  391. if (omi < OME_NUMBER_ENTRIES) {
  392. set_bf(paace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
  393. paace->op_encode.index_ot.omi = omi;
  394. } else if (~omi != 0) {
  395. pr_debug("bad operation mapping index: %d\n", omi);
  396. return -EINVAL;
  397. }
  398. if (~stashid != 0)
  399. set_bf(paace->impl_attr, PAACE_IA_CID, stashid);
  400. smp_wmb();
  401. if (enable)
  402. set_bf(paace->addr_bitfields, PAACE_AF_V, PAACE_V_VALID);
  403. mb();
  404. return 0;
  405. }
  406. /**
  407. * get_ome_index() - Returns the index in the operation mapping table
  408. * for device.
  409. * @*omi_index: pointer for storing the index value
  410. *
  411. */
  412. void get_ome_index(u32 *omi_index, struct device *dev)
  413. {
  414. if (of_device_is_compatible(dev->of_node, "fsl,qman-portal"))
  415. *omi_index = OMI_QMAN;
  416. if (of_device_is_compatible(dev->of_node, "fsl,qman"))
  417. *omi_index = OMI_QMAN_PRIV;
  418. }
  419. /**
  420. * get_stash_id - Returns stash destination id corresponding to a
  421. * cache type and vcpu.
  422. * @stash_dest_hint: L1, L2 or L3
  423. * @vcpu: vpcu target for a particular cache type.
  424. *
  425. * Returs stash on success or ~(u32)0 on failure.
  426. *
  427. */
  428. u32 get_stash_id(u32 stash_dest_hint, u32 vcpu)
  429. {
  430. const u32 *prop;
  431. struct device_node *node;
  432. u32 cache_level;
  433. int len, found = 0;
  434. int i;
  435. /* Fastpath, exit early if L3/CPC cache is target for stashing */
  436. if (stash_dest_hint == PAMU_ATTR_CACHE_L3) {
  437. node = of_find_matching_node(NULL, l3_device_ids);
  438. if (node) {
  439. prop = of_get_property(node, "cache-stash-id", NULL);
  440. if (!prop) {
  441. pr_debug("missing cache-stash-id at %pOF\n",
  442. node);
  443. of_node_put(node);
  444. return ~(u32)0;
  445. }
  446. of_node_put(node);
  447. return be32_to_cpup(prop);
  448. }
  449. return ~(u32)0;
  450. }
  451. for_each_of_cpu_node(node) {
  452. prop = of_get_property(node, "reg", &len);
  453. for (i = 0; i < len / sizeof(u32); i++) {
  454. if (be32_to_cpup(&prop[i]) == vcpu) {
  455. found = 1;
  456. goto found_cpu_node;
  457. }
  458. }
  459. }
  460. found_cpu_node:
  461. /* find the hwnode that represents the cache */
  462. for (cache_level = PAMU_ATTR_CACHE_L1; (cache_level < PAMU_ATTR_CACHE_L3) && found; cache_level++) {
  463. if (stash_dest_hint == cache_level) {
  464. prop = of_get_property(node, "cache-stash-id", NULL);
  465. if (!prop) {
  466. pr_debug("missing cache-stash-id at %pOF\n",
  467. node);
  468. of_node_put(node);
  469. return ~(u32)0;
  470. }
  471. of_node_put(node);
  472. return be32_to_cpup(prop);
  473. }
  474. prop = of_get_property(node, "next-level-cache", NULL);
  475. if (!prop) {
  476. pr_debug("can't find next-level-cache at %pOF\n", node);
  477. of_node_put(node);
  478. return ~(u32)0; /* can't traverse any further */
  479. }
  480. of_node_put(node);
  481. /* advance to next node in cache hierarchy */
  482. node = of_find_node_by_phandle(*prop);
  483. if (!node) {
  484. pr_debug("Invalid node for cache hierarchy\n");
  485. return ~(u32)0;
  486. }
  487. }
  488. pr_debug("stash dest not found for %d on vcpu %d\n",
  489. stash_dest_hint, vcpu);
  490. return ~(u32)0;
  491. }
  492. /* Identify if the PAACT table entry belongs to QMAN, BMAN or QMAN Portal */
  493. #define QMAN_PAACE 1
  494. #define QMAN_PORTAL_PAACE 2
  495. #define BMAN_PAACE 3
  496. /**
  497. * Setup operation mapping and stash destinations for QMAN and QMAN portal.
  498. * Memory accesses to QMAN and BMAN private memory need not be coherent, so
  499. * clear the PAACE entry coherency attribute for them.
  500. */
  501. static void setup_qbman_paace(struct paace *ppaace, int paace_type)
  502. {
  503. switch (paace_type) {
  504. case QMAN_PAACE:
  505. set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
  506. ppaace->op_encode.index_ot.omi = OMI_QMAN_PRIV;
  507. /* setup QMAN Private data stashing for the L3 cache */
  508. set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(PAMU_ATTR_CACHE_L3, 0));
  509. set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
  510. 0);
  511. break;
  512. case QMAN_PORTAL_PAACE:
  513. set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
  514. ppaace->op_encode.index_ot.omi = OMI_QMAN;
  515. /* Set DQRR and Frame stashing for the L3 cache */
  516. set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(PAMU_ATTR_CACHE_L3, 0));
  517. break;
  518. case BMAN_PAACE:
  519. set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
  520. 0);
  521. break;
  522. }
  523. }
  524. /**
  525. * Setup the operation mapping table for various devices. This is a static
  526. * table where each table index corresponds to a particular device. PAMU uses
  527. * this table to translate device transaction to appropriate corenet
  528. * transaction.
  529. */
  530. static void setup_omt(struct ome *omt)
  531. {
  532. struct ome *ome;
  533. /* Configure OMI_QMAN */
  534. ome = &omt[OMI_QMAN];
  535. ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READ;
  536. ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
  537. ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
  538. ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSAO;
  539. ome->moe[IOE_DIRECT0_IDX] = EOE_VALID | EOE_LDEC;
  540. ome->moe[IOE_DIRECT1_IDX] = EOE_VALID | EOE_LDECPE;
  541. /* Configure OMI_FMAN */
  542. ome = &omt[OMI_FMAN];
  543. ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READI;
  544. ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
  545. /* Configure OMI_QMAN private */
  546. ome = &omt[OMI_QMAN_PRIV];
  547. ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READ;
  548. ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
  549. ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
  550. ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
  551. /* Configure OMI_CAAM */
  552. ome = &omt[OMI_CAAM];
  553. ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READI;
  554. ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
  555. }
  556. /*
  557. * Get the maximum number of PAACT table entries
  558. * and subwindows supported by PAMU
  559. */
  560. static void get_pamu_cap_values(unsigned long pamu_reg_base)
  561. {
  562. u32 pc_val;
  563. pc_val = in_be32((u32 *)(pamu_reg_base + PAMU_PC3));
  564. /* Maximum number of subwindows per liodn */
  565. max_subwindow_count = 1 << (1 + PAMU_PC3_MWCE(pc_val));
  566. }
  567. /* Setup PAMU registers pointing to PAACT, SPAACT and OMT */
  568. static int setup_one_pamu(unsigned long pamu_reg_base, unsigned long pamu_reg_size,
  569. phys_addr_t ppaact_phys, phys_addr_t spaact_phys,
  570. phys_addr_t omt_phys)
  571. {
  572. u32 *pc;
  573. struct pamu_mmap_regs *pamu_regs;
  574. pc = (u32 *) (pamu_reg_base + PAMU_PC);
  575. pamu_regs = (struct pamu_mmap_regs *)
  576. (pamu_reg_base + PAMU_MMAP_REGS_BASE);
  577. /* set up pointers to corenet control blocks */
  578. out_be32(&pamu_regs->ppbah, upper_32_bits(ppaact_phys));
  579. out_be32(&pamu_regs->ppbal, lower_32_bits(ppaact_phys));
  580. ppaact_phys = ppaact_phys + PAACT_SIZE;
  581. out_be32(&pamu_regs->pplah, upper_32_bits(ppaact_phys));
  582. out_be32(&pamu_regs->pplal, lower_32_bits(ppaact_phys));
  583. out_be32(&pamu_regs->spbah, upper_32_bits(spaact_phys));
  584. out_be32(&pamu_regs->spbal, lower_32_bits(spaact_phys));
  585. spaact_phys = spaact_phys + SPAACT_SIZE;
  586. out_be32(&pamu_regs->splah, upper_32_bits(spaact_phys));
  587. out_be32(&pamu_regs->splal, lower_32_bits(spaact_phys));
  588. out_be32(&pamu_regs->obah, upper_32_bits(omt_phys));
  589. out_be32(&pamu_regs->obal, lower_32_bits(omt_phys));
  590. omt_phys = omt_phys + OMT_SIZE;
  591. out_be32(&pamu_regs->olah, upper_32_bits(omt_phys));
  592. out_be32(&pamu_regs->olal, lower_32_bits(omt_phys));
  593. /*
  594. * set PAMU enable bit,
  595. * allow ppaact & omt to be cached
  596. * & enable PAMU access violation interrupts.
  597. */
  598. out_be32((u32 *)(pamu_reg_base + PAMU_PICS),
  599. PAMU_ACCESS_VIOLATION_ENABLE);
  600. out_be32(pc, PAMU_PC_PE | PAMU_PC_OCE | PAMU_PC_SPCC | PAMU_PC_PPCC);
  601. return 0;
  602. }
  603. /* Enable all device LIODNS */
  604. static void setup_liodns(void)
  605. {
  606. int i, len;
  607. struct paace *ppaace;
  608. struct device_node *node = NULL;
  609. const u32 *prop;
  610. for_each_node_with_property(node, "fsl,liodn") {
  611. prop = of_get_property(node, "fsl,liodn", &len);
  612. for (i = 0; i < len / sizeof(u32); i++) {
  613. int liodn;
  614. liodn = be32_to_cpup(&prop[i]);
  615. if (liodn >= PAACE_NUMBER_ENTRIES) {
  616. pr_debug("Invalid LIODN value %d\n", liodn);
  617. continue;
  618. }
  619. ppaace = pamu_get_ppaace(liodn);
  620. pamu_init_ppaace(ppaace);
  621. /* window size is 2^(WSE+1) bytes */
  622. set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, 35);
  623. ppaace->wbah = 0;
  624. set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, 0);
  625. set_bf(ppaace->impl_attr, PAACE_IA_ATM,
  626. PAACE_ATM_NO_XLATE);
  627. set_bf(ppaace->addr_bitfields, PAACE_AF_AP,
  628. PAACE_AP_PERMS_ALL);
  629. if (of_device_is_compatible(node, "fsl,qman-portal"))
  630. setup_qbman_paace(ppaace, QMAN_PORTAL_PAACE);
  631. if (of_device_is_compatible(node, "fsl,qman"))
  632. setup_qbman_paace(ppaace, QMAN_PAACE);
  633. if (of_device_is_compatible(node, "fsl,bman"))
  634. setup_qbman_paace(ppaace, BMAN_PAACE);
  635. mb();
  636. pamu_enable_liodn(liodn);
  637. }
  638. }
  639. }
  640. static irqreturn_t pamu_av_isr(int irq, void *arg)
  641. {
  642. struct pamu_isr_data *data = arg;
  643. phys_addr_t phys;
  644. unsigned int i, j, ret;
  645. pr_emerg("access violation interrupt\n");
  646. for (i = 0; i < data->count; i++) {
  647. void __iomem *p = data->pamu_reg_base + i * PAMU_OFFSET;
  648. u32 pics = in_be32(p + PAMU_PICS);
  649. if (pics & PAMU_ACCESS_VIOLATION_STAT) {
  650. u32 avs1 = in_be32(p + PAMU_AVS1);
  651. struct paace *paace;
  652. pr_emerg("POES1=%08x\n", in_be32(p + PAMU_POES1));
  653. pr_emerg("POES2=%08x\n", in_be32(p + PAMU_POES2));
  654. pr_emerg("AVS1=%08x\n", avs1);
  655. pr_emerg("AVS2=%08x\n", in_be32(p + PAMU_AVS2));
  656. pr_emerg("AVA=%016llx\n",
  657. make64(in_be32(p + PAMU_AVAH),
  658. in_be32(p + PAMU_AVAL)));
  659. pr_emerg("UDAD=%08x\n", in_be32(p + PAMU_UDAD));
  660. pr_emerg("POEA=%016llx\n",
  661. make64(in_be32(p + PAMU_POEAH),
  662. in_be32(p + PAMU_POEAL)));
  663. phys = make64(in_be32(p + PAMU_POEAH),
  664. in_be32(p + PAMU_POEAL));
  665. /* Assume that POEA points to a PAACE */
  666. if (phys) {
  667. u32 *paace = phys_to_virt(phys);
  668. /* Only the first four words are relevant */
  669. for (j = 0; j < 4; j++)
  670. pr_emerg("PAACE[%u]=%08x\n",
  671. j, in_be32(paace + j));
  672. }
  673. /* clear access violation condition */
  674. out_be32(p + PAMU_AVS1, avs1 & PAMU_AV_MASK);
  675. paace = pamu_get_ppaace(avs1 >> PAMU_AVS1_LIODN_SHIFT);
  676. BUG_ON(!paace);
  677. /* check if we got a violation for a disabled LIODN */
  678. if (!get_bf(paace->addr_bitfields, PAACE_AF_V)) {
  679. /*
  680. * As per hardware erratum A-003638, access
  681. * violation can be reported for a disabled
  682. * LIODN. If we hit that condition, disable
  683. * access violation reporting.
  684. */
  685. pics &= ~PAMU_ACCESS_VIOLATION_ENABLE;
  686. } else {
  687. /* Disable the LIODN */
  688. ret = pamu_disable_liodn(avs1 >> PAMU_AVS1_LIODN_SHIFT);
  689. BUG_ON(ret);
  690. pr_emerg("Disabling liodn %x\n",
  691. avs1 >> PAMU_AVS1_LIODN_SHIFT);
  692. }
  693. out_be32((p + PAMU_PICS), pics);
  694. }
  695. }
  696. return IRQ_HANDLED;
  697. }
  698. #define LAWAR_EN 0x80000000
  699. #define LAWAR_TARGET_MASK 0x0FF00000
  700. #define LAWAR_TARGET_SHIFT 20
  701. #define LAWAR_SIZE_MASK 0x0000003F
  702. #define LAWAR_CSDID_MASK 0x000FF000
  703. #define LAWAR_CSDID_SHIFT 12
  704. #define LAW_SIZE_4K 0xb
  705. struct ccsr_law {
  706. u32 lawbarh; /* LAWn base address high */
  707. u32 lawbarl; /* LAWn base address low */
  708. u32 lawar; /* LAWn attributes */
  709. u32 reserved;
  710. };
  711. /*
  712. * Create a coherence subdomain for a given memory block.
  713. */
  714. static int create_csd(phys_addr_t phys, size_t size, u32 csd_port_id)
  715. {
  716. struct device_node *np;
  717. const __be32 *iprop;
  718. void __iomem *lac = NULL; /* Local Access Control registers */
  719. struct ccsr_law __iomem *law;
  720. void __iomem *ccm = NULL;
  721. u32 __iomem *csdids;
  722. unsigned int i, num_laws, num_csds;
  723. u32 law_target = 0;
  724. u32 csd_id = 0;
  725. int ret = 0;
  726. np = of_find_compatible_node(NULL, NULL, "fsl,corenet-law");
  727. if (!np)
  728. return -ENODEV;
  729. iprop = of_get_property(np, "fsl,num-laws", NULL);
  730. if (!iprop) {
  731. ret = -ENODEV;
  732. goto error;
  733. }
  734. num_laws = be32_to_cpup(iprop);
  735. if (!num_laws) {
  736. ret = -ENODEV;
  737. goto error;
  738. }
  739. lac = of_iomap(np, 0);
  740. if (!lac) {
  741. ret = -ENODEV;
  742. goto error;
  743. }
  744. /* LAW registers are at offset 0xC00 */
  745. law = lac + 0xC00;
  746. of_node_put(np);
  747. np = of_find_compatible_node(NULL, NULL, "fsl,corenet-cf");
  748. if (!np) {
  749. ret = -ENODEV;
  750. goto error;
  751. }
  752. iprop = of_get_property(np, "fsl,ccf-num-csdids", NULL);
  753. if (!iprop) {
  754. ret = -ENODEV;
  755. goto error;
  756. }
  757. num_csds = be32_to_cpup(iprop);
  758. if (!num_csds) {
  759. ret = -ENODEV;
  760. goto error;
  761. }
  762. ccm = of_iomap(np, 0);
  763. if (!ccm) {
  764. ret = -ENOMEM;
  765. goto error;
  766. }
  767. /* The undocumented CSDID registers are at offset 0x600 */
  768. csdids = ccm + 0x600;
  769. of_node_put(np);
  770. np = NULL;
  771. /* Find an unused coherence subdomain ID */
  772. for (csd_id = 0; csd_id < num_csds; csd_id++) {
  773. if (!csdids[csd_id])
  774. break;
  775. }
  776. /* Store the Port ID in the (undocumented) proper CIDMRxx register */
  777. csdids[csd_id] = csd_port_id;
  778. /* Find the DDR LAW that maps to our buffer. */
  779. for (i = 0; i < num_laws; i++) {
  780. if (law[i].lawar & LAWAR_EN) {
  781. phys_addr_t law_start, law_end;
  782. law_start = make64(law[i].lawbarh, law[i].lawbarl);
  783. law_end = law_start +
  784. (2ULL << (law[i].lawar & LAWAR_SIZE_MASK));
  785. if (law_start <= phys && phys < law_end) {
  786. law_target = law[i].lawar & LAWAR_TARGET_MASK;
  787. break;
  788. }
  789. }
  790. }
  791. if (i == 0 || i == num_laws) {
  792. /* This should never happen */
  793. ret = -ENOENT;
  794. goto error;
  795. }
  796. /* Find a free LAW entry */
  797. while (law[--i].lawar & LAWAR_EN) {
  798. if (i == 0) {
  799. /* No higher priority LAW slots available */
  800. ret = -ENOENT;
  801. goto error;
  802. }
  803. }
  804. law[i].lawbarh = upper_32_bits(phys);
  805. law[i].lawbarl = lower_32_bits(phys);
  806. wmb();
  807. law[i].lawar = LAWAR_EN | law_target | (csd_id << LAWAR_CSDID_SHIFT) |
  808. (LAW_SIZE_4K + get_order(size));
  809. wmb();
  810. error:
  811. if (ccm)
  812. iounmap(ccm);
  813. if (lac)
  814. iounmap(lac);
  815. if (np)
  816. of_node_put(np);
  817. return ret;
  818. }
  819. /*
  820. * Table of SVRs and the corresponding PORT_ID values. Port ID corresponds to a
  821. * bit map of snoopers for a given range of memory mapped by a LAW.
  822. *
  823. * All future CoreNet-enabled SOCs will have this erratum(A-004510) fixed, so this
  824. * table should never need to be updated. SVRs are guaranteed to be unique, so
  825. * there is no worry that a future SOC will inadvertently have one of these
  826. * values.
  827. */
  828. static const struct {
  829. u32 svr;
  830. u32 port_id;
  831. } port_id_map[] = {
  832. {(SVR_P2040 << 8) | 0x10, 0xFF000000}, /* P2040 1.0 */
  833. {(SVR_P2040 << 8) | 0x11, 0xFF000000}, /* P2040 1.1 */
  834. {(SVR_P2041 << 8) | 0x10, 0xFF000000}, /* P2041 1.0 */
  835. {(SVR_P2041 << 8) | 0x11, 0xFF000000}, /* P2041 1.1 */
  836. {(SVR_P3041 << 8) | 0x10, 0xFF000000}, /* P3041 1.0 */
  837. {(SVR_P3041 << 8) | 0x11, 0xFF000000}, /* P3041 1.1 */
  838. {(SVR_P4040 << 8) | 0x20, 0xFFF80000}, /* P4040 2.0 */
  839. {(SVR_P4080 << 8) | 0x20, 0xFFF80000}, /* P4080 2.0 */
  840. {(SVR_P5010 << 8) | 0x10, 0xFC000000}, /* P5010 1.0 */
  841. {(SVR_P5010 << 8) | 0x20, 0xFC000000}, /* P5010 2.0 */
  842. {(SVR_P5020 << 8) | 0x10, 0xFC000000}, /* P5020 1.0 */
  843. {(SVR_P5021 << 8) | 0x10, 0xFF800000}, /* P5021 1.0 */
  844. {(SVR_P5040 << 8) | 0x10, 0xFF800000}, /* P5040 1.0 */
  845. };
  846. #define SVR_SECURITY 0x80000 /* The Security (E) bit */
  847. static int fsl_pamu_probe(struct platform_device *pdev)
  848. {
  849. struct device *dev = &pdev->dev;
  850. void __iomem *pamu_regs = NULL;
  851. struct ccsr_guts __iomem *guts_regs = NULL;
  852. u32 pamubypenr, pamu_counter;
  853. unsigned long pamu_reg_off;
  854. unsigned long pamu_reg_base;
  855. struct pamu_isr_data *data = NULL;
  856. struct device_node *guts_node;
  857. u64 size;
  858. struct page *p;
  859. int ret = 0;
  860. int irq;
  861. phys_addr_t ppaact_phys;
  862. phys_addr_t spaact_phys;
  863. struct ome *omt;
  864. phys_addr_t omt_phys;
  865. size_t mem_size = 0;
  866. unsigned int order = 0;
  867. u32 csd_port_id = 0;
  868. unsigned i;
  869. /*
  870. * enumerate all PAMUs and allocate and setup PAMU tables
  871. * for each of them,
  872. * NOTE : All PAMUs share the same LIODN tables.
  873. */
  874. if (WARN_ON(probed))
  875. return -EBUSY;
  876. pamu_regs = of_iomap(dev->of_node, 0);
  877. if (!pamu_regs) {
  878. dev_err(dev, "ioremap of PAMU node failed\n");
  879. return -ENOMEM;
  880. }
  881. of_get_address(dev->of_node, 0, &size, NULL);
  882. irq = irq_of_parse_and_map(dev->of_node, 0);
  883. if (irq == NO_IRQ) {
  884. dev_warn(dev, "no interrupts listed in PAMU node\n");
  885. goto error;
  886. }
  887. data = kzalloc(sizeof(*data), GFP_KERNEL);
  888. if (!data) {
  889. ret = -ENOMEM;
  890. goto error;
  891. }
  892. data->pamu_reg_base = pamu_regs;
  893. data->count = size / PAMU_OFFSET;
  894. /* The ISR needs access to the regs, so we won't iounmap them */
  895. ret = request_irq(irq, pamu_av_isr, 0, "pamu", data);
  896. if (ret < 0) {
  897. dev_err(dev, "error %i installing ISR for irq %i\n", ret, irq);
  898. goto error;
  899. }
  900. guts_node = of_find_matching_node(NULL, guts_device_ids);
  901. if (!guts_node) {
  902. dev_err(dev, "could not find GUTS node %pOF\n", dev->of_node);
  903. ret = -ENODEV;
  904. goto error;
  905. }
  906. guts_regs = of_iomap(guts_node, 0);
  907. of_node_put(guts_node);
  908. if (!guts_regs) {
  909. dev_err(dev, "ioremap of GUTS node failed\n");
  910. ret = -ENODEV;
  911. goto error;
  912. }
  913. /* read in the PAMU capability registers */
  914. get_pamu_cap_values((unsigned long)pamu_regs);
  915. /*
  916. * To simplify the allocation of a coherency domain, we allocate the
  917. * PAACT and the OMT in the same memory buffer. Unfortunately, this
  918. * wastes more memory compared to allocating the buffers separately.
  919. */
  920. /* Determine how much memory we need */
  921. mem_size = (PAGE_SIZE << get_order(PAACT_SIZE)) +
  922. (PAGE_SIZE << get_order(SPAACT_SIZE)) +
  923. (PAGE_SIZE << get_order(OMT_SIZE));
  924. order = get_order(mem_size);
  925. p = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  926. if (!p) {
  927. dev_err(dev, "unable to allocate PAACT/SPAACT/OMT block\n");
  928. ret = -ENOMEM;
  929. goto error;
  930. }
  931. ppaact = page_address(p);
  932. ppaact_phys = page_to_phys(p);
  933. /* Make sure the memory is naturally aligned */
  934. if (ppaact_phys & ((PAGE_SIZE << order) - 1)) {
  935. dev_err(dev, "PAACT/OMT block is unaligned\n");
  936. ret = -ENOMEM;
  937. goto error;
  938. }
  939. spaact = (void *)ppaact + (PAGE_SIZE << get_order(PAACT_SIZE));
  940. omt = (void *)spaact + (PAGE_SIZE << get_order(SPAACT_SIZE));
  941. dev_dbg(dev, "ppaact virt=%p phys=%pa\n", ppaact, &ppaact_phys);
  942. /* Check to see if we need to implement the work-around on this SOC */
  943. /* Determine the Port ID for our coherence subdomain */
  944. for (i = 0; i < ARRAY_SIZE(port_id_map); i++) {
  945. if (port_id_map[i].svr == (mfspr(SPRN_SVR) & ~SVR_SECURITY)) {
  946. csd_port_id = port_id_map[i].port_id;
  947. dev_dbg(dev, "found matching SVR %08x\n",
  948. port_id_map[i].svr);
  949. break;
  950. }
  951. }
  952. if (csd_port_id) {
  953. dev_dbg(dev, "creating coherency subdomain at address %pa, size %zu, port id 0x%08x",
  954. &ppaact_phys, mem_size, csd_port_id);
  955. ret = create_csd(ppaact_phys, mem_size, csd_port_id);
  956. if (ret) {
  957. dev_err(dev, "could not create coherence subdomain\n");
  958. return ret;
  959. }
  960. }
  961. spaact_phys = virt_to_phys(spaact);
  962. omt_phys = virt_to_phys(omt);
  963. spaace_pool = gen_pool_create(ilog2(sizeof(struct paace)), -1);
  964. if (!spaace_pool) {
  965. ret = -ENOMEM;
  966. dev_err(dev, "Failed to allocate spaace gen pool\n");
  967. goto error;
  968. }
  969. ret = gen_pool_add(spaace_pool, (unsigned long)spaact, SPAACT_SIZE, -1);
  970. if (ret)
  971. goto error_genpool;
  972. pamubypenr = in_be32(&guts_regs->pamubypenr);
  973. for (pamu_reg_off = 0, pamu_counter = 0x80000000; pamu_reg_off < size;
  974. pamu_reg_off += PAMU_OFFSET, pamu_counter >>= 1) {
  975. pamu_reg_base = (unsigned long)pamu_regs + pamu_reg_off;
  976. setup_one_pamu(pamu_reg_base, pamu_reg_off, ppaact_phys,
  977. spaact_phys, omt_phys);
  978. /* Disable PAMU bypass for this PAMU */
  979. pamubypenr &= ~pamu_counter;
  980. }
  981. setup_omt(omt);
  982. /* Enable all relevant PAMU(s) */
  983. out_be32(&guts_regs->pamubypenr, pamubypenr);
  984. iounmap(guts_regs);
  985. /* Enable DMA for the LIODNs in the device tree */
  986. setup_liodns();
  987. probed = true;
  988. return 0;
  989. error_genpool:
  990. gen_pool_destroy(spaace_pool);
  991. error:
  992. if (irq != NO_IRQ)
  993. free_irq(irq, data);
  994. kfree_sensitive(data);
  995. if (pamu_regs)
  996. iounmap(pamu_regs);
  997. if (guts_regs)
  998. iounmap(guts_regs);
  999. if (ppaact)
  1000. free_pages((unsigned long)ppaact, order);
  1001. ppaact = NULL;
  1002. return ret;
  1003. }
  1004. static struct platform_driver fsl_of_pamu_driver = {
  1005. .driver = {
  1006. .name = "fsl-of-pamu",
  1007. },
  1008. .probe = fsl_pamu_probe,
  1009. };
  1010. static __init int fsl_pamu_init(void)
  1011. {
  1012. struct platform_device *pdev = NULL;
  1013. struct device_node *np;
  1014. int ret;
  1015. /*
  1016. * The normal OF process calls the probe function at some
  1017. * indeterminate later time, after most drivers have loaded. This is
  1018. * too late for us, because PAMU clients (like the Qman driver)
  1019. * depend on PAMU being initialized early.
  1020. *
  1021. * So instead, we "manually" call our probe function by creating the
  1022. * platform devices ourselves.
  1023. */
  1024. /*
  1025. * We assume that there is only one PAMU node in the device tree. A
  1026. * single PAMU node represents all of the PAMU devices in the SOC
  1027. * already. Everything else already makes that assumption, and the
  1028. * binding for the PAMU nodes doesn't allow for any parent-child
  1029. * relationships anyway. In other words, support for more than one
  1030. * PAMU node would require significant changes to a lot of code.
  1031. */
  1032. np = of_find_compatible_node(NULL, NULL, "fsl,pamu");
  1033. if (!np) {
  1034. pr_err("could not find a PAMU node\n");
  1035. return -ENODEV;
  1036. }
  1037. ret = platform_driver_register(&fsl_of_pamu_driver);
  1038. if (ret) {
  1039. pr_err("could not register driver (err=%i)\n", ret);
  1040. goto error_driver_register;
  1041. }
  1042. pdev = platform_device_alloc("fsl-of-pamu", 0);
  1043. if (!pdev) {
  1044. pr_err("could not allocate device %pOF\n", np);
  1045. ret = -ENOMEM;
  1046. goto error_device_alloc;
  1047. }
  1048. pdev->dev.of_node = of_node_get(np);
  1049. ret = pamu_domain_init();
  1050. if (ret)
  1051. goto error_device_add;
  1052. ret = platform_device_add(pdev);
  1053. if (ret) {
  1054. pr_err("could not add device %pOF (err=%i)\n", np, ret);
  1055. goto error_device_add;
  1056. }
  1057. return 0;
  1058. error_device_add:
  1059. of_node_put(pdev->dev.of_node);
  1060. pdev->dev.of_node = NULL;
  1061. platform_device_put(pdev);
  1062. error_device_alloc:
  1063. platform_driver_unregister(&fsl_of_pamu_driver);
  1064. error_driver_register:
  1065. of_node_put(np);
  1066. return ret;
  1067. }
  1068. arch_initcall(fsl_pamu_init);