adis16475.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ADIS16475 IMU driver
  4. *
  5. * Copyright 2019 Analog Devices Inc.
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/bitops.h>
  9. #include <linux/clk.h>
  10. #include <linux/debugfs.h>
  11. #include <linux/delay.h>
  12. #include <linux/device.h>
  13. #include <linux/kernel.h>
  14. #include <linux/iio/buffer.h>
  15. #include <linux/iio/iio.h>
  16. #include <linux/iio/imu/adis.h>
  17. #include <linux/iio/sysfs.h>
  18. #include <linux/iio/trigger_consumer.h>
  19. #include <linux/irq.h>
  20. #include <linux/module.h>
  21. #include <linux/mod_devicetable.h>
  22. #include <linux/property.h>
  23. #include <linux/spi/spi.h>
  24. #define ADIS16475_REG_DIAG_STAT 0x02
  25. #define ADIS16475_REG_X_GYRO_L 0x04
  26. #define ADIS16475_REG_Y_GYRO_L 0x08
  27. #define ADIS16475_REG_Z_GYRO_L 0x0C
  28. #define ADIS16475_REG_X_ACCEL_L 0x10
  29. #define ADIS16475_REG_Y_ACCEL_L 0x14
  30. #define ADIS16475_REG_Z_ACCEL_L 0x18
  31. #define ADIS16475_REG_TEMP_OUT 0x1c
  32. #define ADIS16475_REG_X_GYRO_BIAS_L 0x40
  33. #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44
  34. #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48
  35. #define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c
  36. #define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50
  37. #define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54
  38. #define ADIS16475_REG_FILT_CTRL 0x5c
  39. #define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0)
  40. #define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x)
  41. #define ADIS16475_REG_MSG_CTRL 0x60
  42. #define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0)
  43. #define ADIS16475_MSG_CTRL_DR_POL(x) \
  44. FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x)
  45. #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2)
  46. #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x)
  47. #define ADIS16475_REG_UP_SCALE 0x62
  48. #define ADIS16475_REG_DEC_RATE 0x64
  49. #define ADIS16475_REG_GLOB_CMD 0x68
  50. #define ADIS16475_REG_FIRM_REV 0x6c
  51. #define ADIS16475_REG_FIRM_DM 0x6e
  52. #define ADIS16475_REG_FIRM_Y 0x70
  53. #define ADIS16475_REG_PROD_ID 0x72
  54. #define ADIS16475_REG_SERIAL_NUM 0x74
  55. #define ADIS16475_REG_FLASH_CNT 0x7c
  56. #define ADIS16500_BURST32_MASK BIT(9)
  57. #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x)
  58. /* number of data elements in burst mode */
  59. #define ADIS16475_BURST32_MAX_DATA 32
  60. #define ADIS16475_BURST_MAX_DATA 20
  61. #define ADIS16475_MAX_SCAN_DATA 20
  62. /* spi max speed in brust mode */
  63. #define ADIS16475_BURST_MAX_SPEED 1000000
  64. #define ADIS16475_LSB_DEC_MASK BIT(0)
  65. #define ADIS16475_LSB_FIR_MASK BIT(1)
  66. enum {
  67. ADIS16475_SYNC_DIRECT = 1,
  68. ADIS16475_SYNC_SCALED,
  69. ADIS16475_SYNC_OUTPUT,
  70. ADIS16475_SYNC_PULSE = 5,
  71. };
  72. struct adis16475_sync {
  73. u16 sync_mode;
  74. u16 min_rate;
  75. u16 max_rate;
  76. };
  77. struct adis16475_chip_info {
  78. const struct iio_chan_spec *channels;
  79. const struct adis16475_sync *sync;
  80. const struct adis_data adis_data;
  81. const char *name;
  82. u32 num_channels;
  83. u32 gyro_max_val;
  84. u32 gyro_max_scale;
  85. u32 accel_max_val;
  86. u32 accel_max_scale;
  87. u32 temp_scale;
  88. u32 int_clk;
  89. u16 max_dec;
  90. u8 num_sync;
  91. bool has_burst32;
  92. };
  93. struct adis16475 {
  94. const struct adis16475_chip_info *info;
  95. struct adis adis;
  96. u32 clk_freq;
  97. bool burst32;
  98. unsigned long lsb_flag;
  99. /* Alignment needed for the timestamp */
  100. __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8);
  101. };
  102. enum {
  103. ADIS16475_SCAN_GYRO_X,
  104. ADIS16475_SCAN_GYRO_Y,
  105. ADIS16475_SCAN_GYRO_Z,
  106. ADIS16475_SCAN_ACCEL_X,
  107. ADIS16475_SCAN_ACCEL_Y,
  108. ADIS16475_SCAN_ACCEL_Z,
  109. ADIS16475_SCAN_TEMP,
  110. ADIS16475_SCAN_DIAG_S_FLAGS,
  111. ADIS16475_SCAN_CRC_FAILURE,
  112. };
  113. #ifdef CONFIG_DEBUG_FS
  114. static ssize_t adis16475_show_firmware_revision(struct file *file,
  115. char __user *userbuf,
  116. size_t count, loff_t *ppos)
  117. {
  118. struct adis16475 *st = file->private_data;
  119. char buf[7];
  120. size_t len;
  121. u16 rev;
  122. int ret;
  123. ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev);
  124. if (ret)
  125. return ret;
  126. len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
  127. return simple_read_from_buffer(userbuf, count, ppos, buf, len);
  128. }
  129. static const struct file_operations adis16475_firmware_revision_fops = {
  130. .open = simple_open,
  131. .read = adis16475_show_firmware_revision,
  132. .llseek = default_llseek,
  133. .owner = THIS_MODULE,
  134. };
  135. static ssize_t adis16475_show_firmware_date(struct file *file,
  136. char __user *userbuf,
  137. size_t count, loff_t *ppos)
  138. {
  139. struct adis16475 *st = file->private_data;
  140. u16 md, year;
  141. char buf[12];
  142. size_t len;
  143. int ret;
  144. ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year);
  145. if (ret)
  146. return ret;
  147. ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md);
  148. if (ret)
  149. return ret;
  150. len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff,
  151. year);
  152. return simple_read_from_buffer(userbuf, count, ppos, buf, len);
  153. }
  154. static const struct file_operations adis16475_firmware_date_fops = {
  155. .open = simple_open,
  156. .read = adis16475_show_firmware_date,
  157. .llseek = default_llseek,
  158. .owner = THIS_MODULE,
  159. };
  160. static int adis16475_show_serial_number(void *arg, u64 *val)
  161. {
  162. struct adis16475 *st = arg;
  163. u16 serial;
  164. int ret;
  165. ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial);
  166. if (ret)
  167. return ret;
  168. *val = serial;
  169. return 0;
  170. }
  171. DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops,
  172. adis16475_show_serial_number, NULL, "0x%.4llx\n");
  173. static int adis16475_show_product_id(void *arg, u64 *val)
  174. {
  175. struct adis16475 *st = arg;
  176. u16 prod_id;
  177. int ret;
  178. ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id);
  179. if (ret)
  180. return ret;
  181. *val = prod_id;
  182. return 0;
  183. }
  184. DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops,
  185. adis16475_show_product_id, NULL, "%llu\n");
  186. static int adis16475_show_flash_count(void *arg, u64 *val)
  187. {
  188. struct adis16475 *st = arg;
  189. u32 flash_count;
  190. int ret;
  191. ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT,
  192. &flash_count);
  193. if (ret)
  194. return ret;
  195. *val = flash_count;
  196. return 0;
  197. }
  198. DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops,
  199. adis16475_show_flash_count, NULL, "%lld\n");
  200. static void adis16475_debugfs_init(struct iio_dev *indio_dev)
  201. {
  202. struct adis16475 *st = iio_priv(indio_dev);
  203. struct dentry *d = iio_get_debugfs_dentry(indio_dev);
  204. debugfs_create_file_unsafe("serial_number", 0400,
  205. d, st, &adis16475_serial_number_fops);
  206. debugfs_create_file_unsafe("product_id", 0400,
  207. d, st, &adis16475_product_id_fops);
  208. debugfs_create_file_unsafe("flash_count", 0400,
  209. d, st, &adis16475_flash_count_fops);
  210. debugfs_create_file("firmware_revision", 0400,
  211. d, st, &adis16475_firmware_revision_fops);
  212. debugfs_create_file("firmware_date", 0400, d,
  213. st, &adis16475_firmware_date_fops);
  214. }
  215. #else
  216. static void adis16475_debugfs_init(struct iio_dev *indio_dev)
  217. {
  218. }
  219. #endif
  220. static int adis16475_get_freq(struct adis16475 *st, u32 *freq)
  221. {
  222. int ret;
  223. u16 dec;
  224. ret = adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec);
  225. if (ret)
  226. return -EINVAL;
  227. *freq = DIV_ROUND_CLOSEST(st->clk_freq, dec + 1);
  228. return 0;
  229. }
  230. static int adis16475_set_freq(struct adis16475 *st, const u32 freq)
  231. {
  232. u16 dec;
  233. int ret;
  234. if (!freq)
  235. return -EINVAL;
  236. dec = DIV_ROUND_CLOSEST(st->clk_freq, freq);
  237. if (dec)
  238. dec--;
  239. if (dec > st->info->max_dec)
  240. dec = st->info->max_dec;
  241. ret = adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec);
  242. if (ret)
  243. return ret;
  244. /*
  245. * If decimation is used, then gyro and accel data will have meaningful
  246. * bits on the LSB registers. This info is used on the trigger handler.
  247. */
  248. assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec);
  249. return 0;
  250. }
  251. /* The values are approximated. */
  252. static const u32 adis16475_3db_freqs[] = {
  253. [0] = 720, /* Filter disabled, full BW (~720Hz) */
  254. [1] = 360,
  255. [2] = 164,
  256. [3] = 80,
  257. [4] = 40,
  258. [5] = 20,
  259. [6] = 10,
  260. };
  261. static int adis16475_get_filter(struct adis16475 *st, u32 *filter)
  262. {
  263. u16 filter_sz;
  264. int ret;
  265. const int mask = ADIS16475_FILT_CTRL_MASK;
  266. ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz);
  267. if (ret)
  268. return ret;
  269. *filter = adis16475_3db_freqs[filter_sz & mask];
  270. return 0;
  271. }
  272. static int adis16475_set_filter(struct adis16475 *st, const u32 filter)
  273. {
  274. int i = ARRAY_SIZE(adis16475_3db_freqs);
  275. int ret;
  276. while (--i) {
  277. if (adis16475_3db_freqs[i] >= filter)
  278. break;
  279. }
  280. ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL,
  281. ADIS16475_FILT_CTRL(i));
  282. if (ret)
  283. return ret;
  284. /*
  285. * If FIR is used, then gyro and accel data will have meaningful
  286. * bits on the LSB registers. This info is used on the trigger handler.
  287. */
  288. assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i);
  289. return 0;
  290. }
  291. static const u32 adis16475_calib_regs[] = {
  292. [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L,
  293. [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L,
  294. [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L,
  295. [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L,
  296. [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L,
  297. [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L,
  298. };
  299. static int adis16475_read_raw(struct iio_dev *indio_dev,
  300. const struct iio_chan_spec *chan,
  301. int *val, int *val2, long info)
  302. {
  303. struct adis16475 *st = iio_priv(indio_dev);
  304. int ret;
  305. u32 tmp;
  306. switch (info) {
  307. case IIO_CHAN_INFO_RAW:
  308. return adis_single_conversion(indio_dev, chan, 0, val);
  309. case IIO_CHAN_INFO_SCALE:
  310. switch (chan->type) {
  311. case IIO_ANGL_VEL:
  312. *val = st->info->gyro_max_val;
  313. *val2 = st->info->gyro_max_scale;
  314. return IIO_VAL_FRACTIONAL;
  315. case IIO_ACCEL:
  316. *val = st->info->accel_max_val;
  317. *val2 = st->info->accel_max_scale;
  318. return IIO_VAL_FRACTIONAL;
  319. case IIO_TEMP:
  320. *val = st->info->temp_scale;
  321. return IIO_VAL_INT;
  322. default:
  323. return -EINVAL;
  324. }
  325. case IIO_CHAN_INFO_CALIBBIAS:
  326. ret = adis_read_reg_32(&st->adis,
  327. adis16475_calib_regs[chan->scan_index],
  328. val);
  329. if (ret)
  330. return ret;
  331. return IIO_VAL_INT;
  332. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  333. ret = adis16475_get_filter(st, val);
  334. if (ret)
  335. return ret;
  336. return IIO_VAL_INT;
  337. case IIO_CHAN_INFO_SAMP_FREQ:
  338. ret = adis16475_get_freq(st, &tmp);
  339. if (ret)
  340. return ret;
  341. *val = tmp / 1000;
  342. *val2 = (tmp % 1000) * 1000;
  343. return IIO_VAL_INT_PLUS_MICRO;
  344. default:
  345. return -EINVAL;
  346. }
  347. }
  348. static int adis16475_write_raw(struct iio_dev *indio_dev,
  349. const struct iio_chan_spec *chan,
  350. int val, int val2, long info)
  351. {
  352. struct adis16475 *st = iio_priv(indio_dev);
  353. u32 tmp;
  354. switch (info) {
  355. case IIO_CHAN_INFO_SAMP_FREQ:
  356. tmp = val * 1000 + val2 / 1000;
  357. return adis16475_set_freq(st, tmp);
  358. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  359. return adis16475_set_filter(st, val);
  360. case IIO_CHAN_INFO_CALIBBIAS:
  361. return adis_write_reg_32(&st->adis,
  362. adis16475_calib_regs[chan->scan_index],
  363. val);
  364. default:
  365. return -EINVAL;
  366. }
  367. }
  368. #define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \
  369. { \
  370. .type = (_type), \
  371. .modified = 1, \
  372. .channel2 = (_mod), \
  373. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  374. BIT(IIO_CHAN_INFO_CALIBBIAS), \
  375. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  376. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  377. BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
  378. .address = (_address), \
  379. .scan_index = (_si), \
  380. .scan_type = { \
  381. .sign = 's', \
  382. .realbits = (_r_bits), \
  383. .storagebits = (_s_bits), \
  384. .endianness = IIO_BE, \
  385. }, \
  386. }
  387. #define ADIS16475_GYRO_CHANNEL(_mod) \
  388. ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
  389. ADIS16475_REG_ ## _mod ## _GYRO_L, \
  390. ADIS16475_SCAN_GYRO_ ## _mod, 32, 32)
  391. #define ADIS16475_ACCEL_CHANNEL(_mod) \
  392. ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \
  393. ADIS16475_REG_ ## _mod ## _ACCEL_L, \
  394. ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32)
  395. #define ADIS16475_TEMP_CHANNEL() { \
  396. .type = IIO_TEMP, \
  397. .indexed = 1, \
  398. .channel = 0, \
  399. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  400. BIT(IIO_CHAN_INFO_SCALE), \
  401. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  402. BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
  403. .address = ADIS16475_REG_TEMP_OUT, \
  404. .scan_index = ADIS16475_SCAN_TEMP, \
  405. .scan_type = { \
  406. .sign = 's', \
  407. .realbits = 16, \
  408. .storagebits = 16, \
  409. .endianness = IIO_BE, \
  410. }, \
  411. }
  412. static const struct iio_chan_spec adis16475_channels[] = {
  413. ADIS16475_GYRO_CHANNEL(X),
  414. ADIS16475_GYRO_CHANNEL(Y),
  415. ADIS16475_GYRO_CHANNEL(Z),
  416. ADIS16475_ACCEL_CHANNEL(X),
  417. ADIS16475_ACCEL_CHANNEL(Y),
  418. ADIS16475_ACCEL_CHANNEL(Z),
  419. ADIS16475_TEMP_CHANNEL(),
  420. IIO_CHAN_SOFT_TIMESTAMP(7)
  421. };
  422. enum adis16475_variant {
  423. ADIS16470,
  424. ADIS16475_1,
  425. ADIS16475_2,
  426. ADIS16475_3,
  427. ADIS16477_1,
  428. ADIS16477_2,
  429. ADIS16477_3,
  430. ADIS16465_1,
  431. ADIS16465_2,
  432. ADIS16465_3,
  433. ADIS16467_1,
  434. ADIS16467_2,
  435. ADIS16467_3,
  436. ADIS16500,
  437. ADIS16505_1,
  438. ADIS16505_2,
  439. ADIS16505_3,
  440. ADIS16507_1,
  441. ADIS16507_2,
  442. ADIS16507_3,
  443. };
  444. enum {
  445. ADIS16475_DIAG_STAT_DATA_PATH = 1,
  446. ADIS16475_DIAG_STAT_FLASH_MEM,
  447. ADIS16475_DIAG_STAT_SPI,
  448. ADIS16475_DIAG_STAT_STANDBY,
  449. ADIS16475_DIAG_STAT_SENSOR,
  450. ADIS16475_DIAG_STAT_MEMORY,
  451. ADIS16475_DIAG_STAT_CLK,
  452. };
  453. static const char * const adis16475_status_error_msgs[] = {
  454. [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun",
  455. [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure",
  456. [ADIS16475_DIAG_STAT_SPI] = "SPI communication error",
  457. [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode",
  458. [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure",
  459. [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure",
  460. [ADIS16475_DIAG_STAT_CLK] = "Clock error",
  461. };
  462. static int adis16475_enable_irq(struct adis *adis, bool enable)
  463. {
  464. /*
  465. * There is no way to gate the data-ready signal internally inside the
  466. * ADIS16475. We can only control it's polarity...
  467. */
  468. if (enable)
  469. enable_irq(adis->spi->irq);
  470. else
  471. disable_irq(adis->spi->irq);
  472. return 0;
  473. }
  474. #define ADIS16475_DATA(_prod_id, _timeouts) \
  475. { \
  476. .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \
  477. .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \
  478. .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \
  479. .prod_id_reg = ADIS16475_REG_PROD_ID, \
  480. .prod_id = (_prod_id), \
  481. .self_test_mask = BIT(2), \
  482. .self_test_reg = ADIS16475_REG_GLOB_CMD, \
  483. .cs_change_delay = 16, \
  484. .read_delay = 5, \
  485. .write_delay = 5, \
  486. .status_error_msgs = adis16475_status_error_msgs, \
  487. .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \
  488. BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \
  489. BIT(ADIS16475_DIAG_STAT_SPI) | \
  490. BIT(ADIS16475_DIAG_STAT_STANDBY) | \
  491. BIT(ADIS16475_DIAG_STAT_SENSOR) | \
  492. BIT(ADIS16475_DIAG_STAT_MEMORY) | \
  493. BIT(ADIS16475_DIAG_STAT_CLK), \
  494. .enable_irq = adis16475_enable_irq, \
  495. .timeouts = (_timeouts), \
  496. .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \
  497. .burst_len = ADIS16475_BURST_MAX_DATA, \
  498. .burst_max_len = ADIS16475_BURST32_MAX_DATA \
  499. }
  500. static const struct adis16475_sync adis16475_sync_mode[] = {
  501. { ADIS16475_SYNC_OUTPUT },
  502. { ADIS16475_SYNC_DIRECT, 1900, 2100 },
  503. { ADIS16475_SYNC_SCALED, 1, 128 },
  504. { ADIS16475_SYNC_PULSE, 1000, 2100 },
  505. };
  506. static const struct adis_timeout adis16475_timeouts = {
  507. .reset_ms = 200,
  508. .sw_reset_ms = 200,
  509. .self_test_ms = 20,
  510. };
  511. static const struct adis_timeout adis1650x_timeouts = {
  512. .reset_ms = 260,
  513. .sw_reset_ms = 260,
  514. .self_test_ms = 30,
  515. };
  516. static const struct adis16475_chip_info adis16475_chip_info[] = {
  517. [ADIS16470] = {
  518. .name = "adis16470",
  519. .num_channels = ARRAY_SIZE(adis16475_channels),
  520. .channels = adis16475_channels,
  521. .gyro_max_val = 1,
  522. .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
  523. .accel_max_val = 1,
  524. .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
  525. .temp_scale = 100,
  526. .int_clk = 2000,
  527. .max_dec = 1999,
  528. .sync = adis16475_sync_mode,
  529. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  530. .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts),
  531. },
  532. [ADIS16475_1] = {
  533. .name = "adis16475-1",
  534. .num_channels = ARRAY_SIZE(adis16475_channels),
  535. .channels = adis16475_channels,
  536. .gyro_max_val = 1,
  537. .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
  538. .accel_max_val = 1,
  539. .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
  540. .temp_scale = 100,
  541. .int_clk = 2000,
  542. .max_dec = 1999,
  543. .sync = adis16475_sync_mode,
  544. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  545. .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
  546. },
  547. [ADIS16475_2] = {
  548. .name = "adis16475-2",
  549. .num_channels = ARRAY_SIZE(adis16475_channels),
  550. .channels = adis16475_channels,
  551. .gyro_max_val = 1,
  552. .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
  553. .accel_max_val = 1,
  554. .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
  555. .temp_scale = 100,
  556. .int_clk = 2000,
  557. .max_dec = 1999,
  558. .sync = adis16475_sync_mode,
  559. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  560. .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
  561. },
  562. [ADIS16475_3] = {
  563. .name = "adis16475-3",
  564. .num_channels = ARRAY_SIZE(adis16475_channels),
  565. .channels = adis16475_channels,
  566. .gyro_max_val = 1,
  567. .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
  568. .accel_max_val = 1,
  569. .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
  570. .temp_scale = 100,
  571. .int_clk = 2000,
  572. .max_dec = 1999,
  573. .sync = adis16475_sync_mode,
  574. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  575. .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
  576. },
  577. [ADIS16477_1] = {
  578. .name = "adis16477-1",
  579. .num_channels = ARRAY_SIZE(adis16475_channels),
  580. .channels = adis16475_channels,
  581. .gyro_max_val = 1,
  582. .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
  583. .accel_max_val = 1,
  584. .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
  585. .temp_scale = 100,
  586. .int_clk = 2000,
  587. .max_dec = 1999,
  588. .sync = adis16475_sync_mode,
  589. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  590. .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
  591. },
  592. [ADIS16477_2] = {
  593. .name = "adis16477-2",
  594. .num_channels = ARRAY_SIZE(adis16475_channels),
  595. .channels = adis16475_channels,
  596. .gyro_max_val = 1,
  597. .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
  598. .accel_max_val = 1,
  599. .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
  600. .temp_scale = 100,
  601. .int_clk = 2000,
  602. .max_dec = 1999,
  603. .sync = adis16475_sync_mode,
  604. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  605. .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
  606. },
  607. [ADIS16477_3] = {
  608. .name = "adis16477-3",
  609. .num_channels = ARRAY_SIZE(adis16475_channels),
  610. .channels = adis16475_channels,
  611. .gyro_max_val = 1,
  612. .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
  613. .accel_max_val = 1,
  614. .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
  615. .temp_scale = 100,
  616. .int_clk = 2000,
  617. .max_dec = 1999,
  618. .sync = adis16475_sync_mode,
  619. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  620. .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
  621. },
  622. [ADIS16465_1] = {
  623. .name = "adis16465-1",
  624. .num_channels = ARRAY_SIZE(adis16475_channels),
  625. .channels = adis16475_channels,
  626. .gyro_max_val = 1,
  627. .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
  628. .accel_max_val = 1,
  629. .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
  630. .temp_scale = 100,
  631. .int_clk = 2000,
  632. .max_dec = 1999,
  633. .sync = adis16475_sync_mode,
  634. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  635. .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
  636. },
  637. [ADIS16465_2] = {
  638. .name = "adis16465-2",
  639. .num_channels = ARRAY_SIZE(adis16475_channels),
  640. .channels = adis16475_channels,
  641. .gyro_max_val = 1,
  642. .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
  643. .accel_max_val = 1,
  644. .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
  645. .temp_scale = 100,
  646. .int_clk = 2000,
  647. .max_dec = 1999,
  648. .sync = adis16475_sync_mode,
  649. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  650. .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
  651. },
  652. [ADIS16465_3] = {
  653. .name = "adis16465-3",
  654. .num_channels = ARRAY_SIZE(adis16475_channels),
  655. .channels = adis16475_channels,
  656. .gyro_max_val = 1,
  657. .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
  658. .accel_max_val = 1,
  659. .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
  660. .temp_scale = 100,
  661. .int_clk = 2000,
  662. .max_dec = 1999,
  663. .sync = adis16475_sync_mode,
  664. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  665. .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
  666. },
  667. [ADIS16467_1] = {
  668. .name = "adis16467-1",
  669. .num_channels = ARRAY_SIZE(adis16475_channels),
  670. .channels = adis16475_channels,
  671. .gyro_max_val = 1,
  672. .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
  673. .accel_max_val = 1,
  674. .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
  675. .temp_scale = 100,
  676. .int_clk = 2000,
  677. .max_dec = 1999,
  678. .sync = adis16475_sync_mode,
  679. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  680. .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
  681. },
  682. [ADIS16467_2] = {
  683. .name = "adis16467-2",
  684. .num_channels = ARRAY_SIZE(adis16475_channels),
  685. .channels = adis16475_channels,
  686. .gyro_max_val = 1,
  687. .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
  688. .accel_max_val = 1,
  689. .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
  690. .temp_scale = 100,
  691. .int_clk = 2000,
  692. .max_dec = 1999,
  693. .sync = adis16475_sync_mode,
  694. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  695. .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
  696. },
  697. [ADIS16467_3] = {
  698. .name = "adis16467-3",
  699. .num_channels = ARRAY_SIZE(adis16475_channels),
  700. .channels = adis16475_channels,
  701. .gyro_max_val = 1,
  702. .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
  703. .accel_max_val = 1,
  704. .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
  705. .temp_scale = 100,
  706. .int_clk = 2000,
  707. .max_dec = 1999,
  708. .sync = adis16475_sync_mode,
  709. .num_sync = ARRAY_SIZE(adis16475_sync_mode),
  710. .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
  711. },
  712. [ADIS16500] = {
  713. .name = "adis16500",
  714. .num_channels = ARRAY_SIZE(adis16475_channels),
  715. .channels = adis16475_channels,
  716. .gyro_max_val = 1,
  717. .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
  718. .accel_max_val = 392,
  719. .accel_max_scale = 32000 << 16,
  720. .temp_scale = 100,
  721. .int_clk = 2000,
  722. .max_dec = 1999,
  723. .sync = adis16475_sync_mode,
  724. /* pulse sync not supported */
  725. .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
  726. .has_burst32 = true,
  727. .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts),
  728. },
  729. [ADIS16505_1] = {
  730. .name = "adis16505-1",
  731. .num_channels = ARRAY_SIZE(adis16475_channels),
  732. .channels = adis16475_channels,
  733. .gyro_max_val = 1,
  734. .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
  735. .accel_max_val = 78,
  736. .accel_max_scale = 32000 << 16,
  737. .temp_scale = 100,
  738. .int_clk = 2000,
  739. .max_dec = 1999,
  740. .sync = adis16475_sync_mode,
  741. /* pulse sync not supported */
  742. .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
  743. .has_burst32 = true,
  744. .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
  745. },
  746. [ADIS16505_2] = {
  747. .name = "adis16505-2",
  748. .num_channels = ARRAY_SIZE(adis16475_channels),
  749. .channels = adis16475_channels,
  750. .gyro_max_val = 1,
  751. .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
  752. .accel_max_val = 78,
  753. .accel_max_scale = 32000 << 16,
  754. .temp_scale = 100,
  755. .int_clk = 2000,
  756. .max_dec = 1999,
  757. .sync = adis16475_sync_mode,
  758. /* pulse sync not supported */
  759. .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
  760. .has_burst32 = true,
  761. .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
  762. },
  763. [ADIS16505_3] = {
  764. .name = "adis16505-3",
  765. .num_channels = ARRAY_SIZE(adis16475_channels),
  766. .channels = adis16475_channels,
  767. .gyro_max_val = 1,
  768. .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
  769. .accel_max_val = 78,
  770. .accel_max_scale = 32000 << 16,
  771. .temp_scale = 100,
  772. .int_clk = 2000,
  773. .max_dec = 1999,
  774. .sync = adis16475_sync_mode,
  775. /* pulse sync not supported */
  776. .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
  777. .has_burst32 = true,
  778. .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
  779. },
  780. [ADIS16507_1] = {
  781. .name = "adis16507-1",
  782. .num_channels = ARRAY_SIZE(adis16475_channels),
  783. .channels = adis16475_channels,
  784. .gyro_max_val = 1,
  785. .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
  786. .accel_max_val = 392,
  787. .accel_max_scale = 32000 << 16,
  788. .temp_scale = 100,
  789. .int_clk = 2000,
  790. .max_dec = 1999,
  791. .sync = adis16475_sync_mode,
  792. /* pulse sync not supported */
  793. .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
  794. .has_burst32 = true,
  795. .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
  796. },
  797. [ADIS16507_2] = {
  798. .name = "adis16507-2",
  799. .num_channels = ARRAY_SIZE(adis16475_channels),
  800. .channels = adis16475_channels,
  801. .gyro_max_val = 1,
  802. .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
  803. .accel_max_val = 392,
  804. .accel_max_scale = 32000 << 16,
  805. .temp_scale = 100,
  806. .int_clk = 2000,
  807. .max_dec = 1999,
  808. .sync = adis16475_sync_mode,
  809. /* pulse sync not supported */
  810. .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
  811. .has_burst32 = true,
  812. .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
  813. },
  814. [ADIS16507_3] = {
  815. .name = "adis16507-3",
  816. .num_channels = ARRAY_SIZE(adis16475_channels),
  817. .channels = adis16475_channels,
  818. .gyro_max_val = 1,
  819. .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
  820. .accel_max_val = 392,
  821. .accel_max_scale = 32000 << 16,
  822. .temp_scale = 100,
  823. .int_clk = 2000,
  824. .max_dec = 1999,
  825. .sync = adis16475_sync_mode,
  826. /* pulse sync not supported */
  827. .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
  828. .has_burst32 = true,
  829. .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
  830. },
  831. };
  832. static const struct iio_info adis16475_info = {
  833. .read_raw = &adis16475_read_raw,
  834. .write_raw = &adis16475_write_raw,
  835. .update_scan_mode = adis_update_scan_mode,
  836. .debugfs_reg_access = adis_debugfs_reg_access,
  837. };
  838. static bool adis16475_validate_crc(const u8 *buffer, u16 crc,
  839. const bool burst32)
  840. {
  841. int i;
  842. /* extra 6 elements for low gyro and accel */
  843. const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA :
  844. ADIS16475_BURST_MAX_DATA;
  845. for (i = 0; i < sz - 2; i++)
  846. crc -= buffer[i];
  847. return crc == 0;
  848. }
  849. static void adis16475_burst32_check(struct adis16475 *st)
  850. {
  851. int ret;
  852. struct adis *adis = &st->adis;
  853. if (!st->info->has_burst32)
  854. return;
  855. if (st->lsb_flag && !st->burst32) {
  856. const u16 en = ADIS16500_BURST32(1);
  857. ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
  858. ADIS16500_BURST32_MASK, en);
  859. if (ret)
  860. return;
  861. st->burst32 = true;
  862. /*
  863. * In 32-bit mode we need extra 2 bytes for all gyro
  864. * and accel channels.
  865. */
  866. adis->burst_extra_len = 6 * sizeof(u16);
  867. adis->xfer[1].len += 6 * sizeof(u16);
  868. dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d",
  869. adis->xfer[1].len);
  870. } else if (!st->lsb_flag && st->burst32) {
  871. const u16 en = ADIS16500_BURST32(0);
  872. ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
  873. ADIS16500_BURST32_MASK, en);
  874. if (ret)
  875. return;
  876. st->burst32 = false;
  877. /* Remove the extra bits */
  878. adis->burst_extra_len = 0;
  879. adis->xfer[1].len -= 6 * sizeof(u16);
  880. dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n",
  881. adis->xfer[1].len);
  882. }
  883. }
  884. static irqreturn_t adis16475_trigger_handler(int irq, void *p)
  885. {
  886. struct iio_poll_func *pf = p;
  887. struct iio_dev *indio_dev = pf->indio_dev;
  888. struct adis16475 *st = iio_priv(indio_dev);
  889. struct adis *adis = &st->adis;
  890. int ret, bit, i = 0;
  891. __be16 *buffer;
  892. u16 crc;
  893. bool valid;
  894. /* offset until the first element after gyro and accel */
  895. const u8 offset = st->burst32 ? 13 : 7;
  896. const u32 cached_spi_speed_hz = adis->spi->max_speed_hz;
  897. adis->spi->max_speed_hz = ADIS16475_BURST_MAX_SPEED;
  898. ret = spi_sync(adis->spi, &adis->msg);
  899. if (ret)
  900. goto check_burst32;
  901. adis->spi->max_speed_hz = cached_spi_speed_hz;
  902. buffer = adis->buffer;
  903. crc = be16_to_cpu(buffer[offset + 2]);
  904. valid = adis16475_validate_crc(adis->buffer, crc, st->burst32);
  905. if (!valid) {
  906. dev_err(&adis->spi->dev, "Invalid crc\n");
  907. goto check_burst32;
  908. }
  909. for_each_set_bit(bit, indio_dev->active_scan_mask,
  910. indio_dev->masklength) {
  911. /*
  912. * When burst mode is used, system flags is the first data
  913. * channel in the sequence, but the scan index is 7.
  914. */
  915. switch (bit) {
  916. case ADIS16475_SCAN_TEMP:
  917. st->data[i++] = buffer[offset];
  918. break;
  919. case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z:
  920. /*
  921. * The first 2 bytes on the received data are the
  922. * DIAG_STAT reg, hence the +1 offset here...
  923. */
  924. if (st->burst32) {
  925. /* upper 16 */
  926. st->data[i++] = buffer[bit * 2 + 2];
  927. /* lower 16 */
  928. st->data[i++] = buffer[bit * 2 + 1];
  929. } else {
  930. st->data[i++] = buffer[bit + 1];
  931. /*
  932. * Don't bother in doing the manual read if the
  933. * device supports burst32. burst32 will be
  934. * enabled in the next call to
  935. * adis16475_burst32_check()...
  936. */
  937. if (st->lsb_flag && !st->info->has_burst32) {
  938. u16 val = 0;
  939. const u32 reg = ADIS16475_REG_X_GYRO_L +
  940. bit * 4;
  941. adis_read_reg_16(adis, reg, &val);
  942. st->data[i++] = cpu_to_be16(val);
  943. } else {
  944. /* lower not used */
  945. st->data[i++] = 0;
  946. }
  947. }
  948. break;
  949. }
  950. }
  951. iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
  952. check_burst32:
  953. /*
  954. * We only check the burst mode at the end of the current capture since
  955. * it takes a full data ready cycle for the device to update the burst
  956. * array.
  957. */
  958. adis16475_burst32_check(st);
  959. iio_trigger_notify_done(indio_dev->trig);
  960. return IRQ_HANDLED;
  961. }
  962. static void adis16475_disable_clk(void *data)
  963. {
  964. clk_disable_unprepare((struct clk *)data);
  965. }
  966. static int adis16475_config_sync_mode(struct adis16475 *st)
  967. {
  968. int ret;
  969. struct device *dev = &st->adis.spi->dev;
  970. const struct adis16475_sync *sync;
  971. u32 sync_mode;
  972. /* default to internal clk */
  973. st->clk_freq = st->info->int_clk * 1000;
  974. ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode);
  975. if (ret)
  976. return 0;
  977. if (sync_mode >= st->info->num_sync) {
  978. dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode,
  979. st->info->name);
  980. return -EINVAL;
  981. }
  982. sync = &st->info->sync[sync_mode];
  983. /* All the other modes require external input signal */
  984. if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) {
  985. struct clk *clk = devm_clk_get(dev, NULL);
  986. if (IS_ERR(clk))
  987. return PTR_ERR(clk);
  988. ret = clk_prepare_enable(clk);
  989. if (ret)
  990. return ret;
  991. ret = devm_add_action_or_reset(dev, adis16475_disable_clk, clk);
  992. if (ret)
  993. return ret;
  994. st->clk_freq = clk_get_rate(clk);
  995. if (st->clk_freq < sync->min_rate ||
  996. st->clk_freq > sync->max_rate) {
  997. dev_err(dev,
  998. "Clk rate:%u not in a valid range:[%u %u]\n",
  999. st->clk_freq, sync->min_rate, sync->max_rate);
  1000. return -EINVAL;
  1001. }
  1002. if (sync->sync_mode == ADIS16475_SYNC_SCALED) {
  1003. u16 up_scale;
  1004. u32 scaled_out_freq = 0;
  1005. /*
  1006. * If we are in scaled mode, we must have an up_scale.
  1007. * In scaled mode the allowable input clock range is
  1008. * 1 Hz to 128 Hz, and the allowable output range is
  1009. * 1900 to 2100 Hz. Hence, a scale must be given to
  1010. * get the allowable output.
  1011. */
  1012. ret = device_property_read_u32(dev,
  1013. "adi,scaled-output-hz",
  1014. &scaled_out_freq);
  1015. if (ret) {
  1016. dev_err(dev, "adi,scaled-output-hz must be given when in scaled sync mode");
  1017. return -EINVAL;
  1018. } else if (scaled_out_freq < 1900 ||
  1019. scaled_out_freq > 2100) {
  1020. dev_err(dev, "Invalid value: %u for adi,scaled-output-hz",
  1021. scaled_out_freq);
  1022. return -EINVAL;
  1023. }
  1024. up_scale = DIV_ROUND_CLOSEST(scaled_out_freq,
  1025. st->clk_freq);
  1026. ret = __adis_write_reg_16(&st->adis,
  1027. ADIS16475_REG_UP_SCALE,
  1028. up_scale);
  1029. if (ret)
  1030. return ret;
  1031. st->clk_freq = scaled_out_freq;
  1032. }
  1033. st->clk_freq *= 1000;
  1034. }
  1035. /*
  1036. * Keep in mind that the mask for the clk modes in adis1650*
  1037. * chips is different (1100 instead of 11100). However, we
  1038. * are not configuring BIT(4) in these chips and the default
  1039. * value is 0, so we are fine in doing the below operations.
  1040. * I'm keeping this for simplicity and avoiding extra variables
  1041. * in chip_info.
  1042. */
  1043. ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
  1044. ADIS16475_SYNC_MODE_MASK, sync->sync_mode);
  1045. if (ret)
  1046. return ret;
  1047. usleep_range(250, 260);
  1048. return 0;
  1049. }
  1050. static int adis16475_config_irq_pin(struct adis16475 *st)
  1051. {
  1052. int ret;
  1053. struct irq_data *desc;
  1054. u32 irq_type;
  1055. u16 val = 0;
  1056. u8 polarity;
  1057. struct spi_device *spi = st->adis.spi;
  1058. desc = irq_get_irq_data(spi->irq);
  1059. if (!desc) {
  1060. dev_err(&spi->dev, "Could not find IRQ %d\n", spi->irq);
  1061. return -EINVAL;
  1062. }
  1063. /*
  1064. * It is possible to configure the data ready polarity. Furthermore, we
  1065. * need to update the adis struct if we want data ready as active low.
  1066. */
  1067. irq_type = irqd_get_trigger_type(desc);
  1068. if (irq_type == IRQ_TYPE_EDGE_RISING) {
  1069. polarity = 1;
  1070. st->adis.irq_flag = IRQF_TRIGGER_RISING;
  1071. } else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
  1072. polarity = 0;
  1073. st->adis.irq_flag = IRQF_TRIGGER_FALLING;
  1074. } else {
  1075. dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n",
  1076. irq_type);
  1077. return -EINVAL;
  1078. }
  1079. val = ADIS16475_MSG_CTRL_DR_POL(polarity);
  1080. ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
  1081. ADIS16475_MSG_CTRL_DR_POL_MASK, val);
  1082. if (ret)
  1083. return ret;
  1084. /*
  1085. * There is a delay writing to any bits written to the MSC_CTRL
  1086. * register. It should not be bigger than 200us, so 250 should be more
  1087. * than enough!
  1088. */
  1089. usleep_range(250, 260);
  1090. return 0;
  1091. }
  1092. static const struct of_device_id adis16475_of_match[] = {
  1093. { .compatible = "adi,adis16470",
  1094. .data = &adis16475_chip_info[ADIS16470] },
  1095. { .compatible = "adi,adis16475-1",
  1096. .data = &adis16475_chip_info[ADIS16475_1] },
  1097. { .compatible = "adi,adis16475-2",
  1098. .data = &adis16475_chip_info[ADIS16475_2] },
  1099. { .compatible = "adi,adis16475-3",
  1100. .data = &adis16475_chip_info[ADIS16475_3] },
  1101. { .compatible = "adi,adis16477-1",
  1102. .data = &adis16475_chip_info[ADIS16477_1] },
  1103. { .compatible = "adi,adis16477-2",
  1104. .data = &adis16475_chip_info[ADIS16477_2] },
  1105. { .compatible = "adi,adis16477-3",
  1106. .data = &adis16475_chip_info[ADIS16477_3] },
  1107. { .compatible = "adi,adis16465-1",
  1108. .data = &adis16475_chip_info[ADIS16465_1] },
  1109. { .compatible = "adi,adis16465-2",
  1110. .data = &adis16475_chip_info[ADIS16465_2] },
  1111. { .compatible = "adi,adis16465-3",
  1112. .data = &adis16475_chip_info[ADIS16465_3] },
  1113. { .compatible = "adi,adis16467-1",
  1114. .data = &adis16475_chip_info[ADIS16467_1] },
  1115. { .compatible = "adi,adis16467-2",
  1116. .data = &adis16475_chip_info[ADIS16467_2] },
  1117. { .compatible = "adi,adis16467-3",
  1118. .data = &adis16475_chip_info[ADIS16467_3] },
  1119. { .compatible = "adi,adis16500",
  1120. .data = &adis16475_chip_info[ADIS16500] },
  1121. { .compatible = "adi,adis16505-1",
  1122. .data = &adis16475_chip_info[ADIS16505_1] },
  1123. { .compatible = "adi,adis16505-2",
  1124. .data = &adis16475_chip_info[ADIS16505_2] },
  1125. { .compatible = "adi,adis16505-3",
  1126. .data = &adis16475_chip_info[ADIS16505_3] },
  1127. { .compatible = "adi,adis16507-1",
  1128. .data = &adis16475_chip_info[ADIS16507_1] },
  1129. { .compatible = "adi,adis16507-2",
  1130. .data = &adis16475_chip_info[ADIS16507_2] },
  1131. { .compatible = "adi,adis16507-3",
  1132. .data = &adis16475_chip_info[ADIS16507_3] },
  1133. { },
  1134. };
  1135. MODULE_DEVICE_TABLE(of, adis16475_of_match);
  1136. static int adis16475_probe(struct spi_device *spi)
  1137. {
  1138. struct iio_dev *indio_dev;
  1139. struct adis16475 *st;
  1140. int ret;
  1141. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  1142. if (!indio_dev)
  1143. return -ENOMEM;
  1144. st = iio_priv(indio_dev);
  1145. spi_set_drvdata(spi, indio_dev);
  1146. st->info = device_get_match_data(&spi->dev);
  1147. if (!st->info)
  1148. return -EINVAL;
  1149. ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data);
  1150. if (ret)
  1151. return ret;
  1152. indio_dev->name = st->info->name;
  1153. indio_dev->channels = st->info->channels;
  1154. indio_dev->num_channels = st->info->num_channels;
  1155. indio_dev->info = &adis16475_info;
  1156. indio_dev->modes = INDIO_DIRECT_MODE;
  1157. ret = __adis_initial_startup(&st->adis);
  1158. if (ret)
  1159. return ret;
  1160. ret = adis16475_config_irq_pin(st);
  1161. if (ret)
  1162. return ret;
  1163. ret = adis16475_config_sync_mode(st);
  1164. if (ret)
  1165. return ret;
  1166. ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
  1167. adis16475_trigger_handler);
  1168. if (ret)
  1169. return ret;
  1170. adis16475_enable_irq(&st->adis, false);
  1171. ret = devm_iio_device_register(&spi->dev, indio_dev);
  1172. if (ret)
  1173. return ret;
  1174. adis16475_debugfs_init(indio_dev);
  1175. return 0;
  1176. }
  1177. static struct spi_driver adis16475_driver = {
  1178. .driver = {
  1179. .name = "adis16475",
  1180. .of_match_table = adis16475_of_match,
  1181. },
  1182. .probe = adis16475_probe,
  1183. };
  1184. module_spi_driver(adis16475_driver);
  1185. MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
  1186. MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver");
  1187. MODULE_LICENSE("GPL");