adf4371.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Analog Devices ADF4371 SPI Wideband Synthesizer driver
  4. *
  5. * Copyright 2019 Analog Devices Inc.
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/clk.h>
  9. #include <linux/device.h>
  10. #include <linux/err.h>
  11. #include <linux/gcd.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/regmap.h>
  15. #include <linux/sysfs.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/iio/iio.h>
  18. /* Registers address macro */
  19. #define ADF4371_REG(x) (x)
  20. /* ADF4371_REG0 */
  21. #define ADF4371_ADDR_ASC_MSK BIT(2)
  22. #define ADF4371_ADDR_ASC(x) FIELD_PREP(ADF4371_ADDR_ASC_MSK, x)
  23. #define ADF4371_ADDR_ASC_R_MSK BIT(5)
  24. #define ADF4371_ADDR_ASC_R(x) FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x)
  25. #define ADF4371_RESET_CMD 0x81
  26. /* ADF4371_REG17 */
  27. #define ADF4371_FRAC2WORD_L_MSK GENMASK(7, 1)
  28. #define ADF4371_FRAC2WORD_L(x) FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x)
  29. #define ADF4371_FRAC1WORD_MSK BIT(0)
  30. #define ADF4371_FRAC1WORD(x) FIELD_PREP(ADF4371_FRAC1WORD_MSK, x)
  31. /* ADF4371_REG18 */
  32. #define ADF4371_FRAC2WORD_H_MSK GENMASK(6, 0)
  33. #define ADF4371_FRAC2WORD_H(x) FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x)
  34. /* ADF4371_REG1A */
  35. #define ADF4371_MOD2WORD_MSK GENMASK(5, 0)
  36. #define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x)
  37. /* ADF4371_REG24 */
  38. #define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4)
  39. #define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x)
  40. /* ADF4371_REG25 */
  41. #define ADF4371_MUTE_LD_MSK BIT(7)
  42. #define ADF4371_MUTE_LD(x) FIELD_PREP(ADF4371_MUTE_LD_MSK, x)
  43. /* ADF4371_REG32 */
  44. #define ADF4371_TIMEOUT_MSK GENMASK(1, 0)
  45. #define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x)
  46. /* ADF4371_REG34 */
  47. #define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0)
  48. #define ADF4371_VCO_ALC_TOUT(x) FIELD_PREP(ADF4371_VCO_ALC_TOUT_MSK, x)
  49. /* Specifications */
  50. #define ADF4371_MIN_VCO_FREQ 4000000000ULL /* 4000 MHz */
  51. #define ADF4371_MAX_VCO_FREQ 8000000000ULL /* 8000 MHz */
  52. #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
  53. #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
  54. #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
  55. #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
  56. #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
  57. #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
  58. #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
  59. #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
  60. /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
  61. #define ADF4371_MODULUS1 33554432ULL
  62. /* MOD2 is the programmable, 14-bit auxiliary fractional modulus */
  63. #define ADF4371_MAX_MODULUS2 BIT(14)
  64. #define ADF4371_CHECK_RANGE(freq, range) \
  65. ((freq > ADF4371_MAX_ ## range) || (freq < ADF4371_MIN_ ## range))
  66. enum {
  67. ADF4371_FREQ,
  68. ADF4371_POWER_DOWN,
  69. ADF4371_CHANNEL_NAME
  70. };
  71. enum {
  72. ADF4371_CH_RF8,
  73. ADF4371_CH_RFAUX8,
  74. ADF4371_CH_RF16,
  75. ADF4371_CH_RF32
  76. };
  77. enum adf4371_variant {
  78. ADF4371,
  79. ADF4372
  80. };
  81. struct adf4371_pwrdown {
  82. unsigned int reg;
  83. unsigned int bit;
  84. };
  85. static const char * const adf4371_ch_names[] = {
  86. "RF8x", "RFAUX8x", "RF16x", "RF32x"
  87. };
  88. static const struct adf4371_pwrdown adf4371_pwrdown_ch[4] = {
  89. [ADF4371_CH_RF8] = { ADF4371_REG(0x25), 2 },
  90. [ADF4371_CH_RFAUX8] = { ADF4371_REG(0x72), 3 },
  91. [ADF4371_CH_RF16] = { ADF4371_REG(0x25), 3 },
  92. [ADF4371_CH_RF32] = { ADF4371_REG(0x25), 4 },
  93. };
  94. static const struct reg_sequence adf4371_reg_defaults[] = {
  95. { ADF4371_REG(0x0), 0x18 },
  96. { ADF4371_REG(0x12), 0x40 },
  97. { ADF4371_REG(0x1E), 0x48 },
  98. { ADF4371_REG(0x20), 0x14 },
  99. { ADF4371_REG(0x22), 0x00 },
  100. { ADF4371_REG(0x23), 0x00 },
  101. { ADF4371_REG(0x24), 0x80 },
  102. { ADF4371_REG(0x25), 0x07 },
  103. { ADF4371_REG(0x27), 0xC5 },
  104. { ADF4371_REG(0x28), 0x83 },
  105. { ADF4371_REG(0x2C), 0x44 },
  106. { ADF4371_REG(0x2D), 0x11 },
  107. { ADF4371_REG(0x2E), 0x12 },
  108. { ADF4371_REG(0x2F), 0x94 },
  109. { ADF4371_REG(0x32), 0x04 },
  110. { ADF4371_REG(0x35), 0xFA },
  111. { ADF4371_REG(0x36), 0x30 },
  112. { ADF4371_REG(0x39), 0x07 },
  113. { ADF4371_REG(0x3A), 0x55 },
  114. { ADF4371_REG(0x3E), 0x0C },
  115. { ADF4371_REG(0x3F), 0x80 },
  116. { ADF4371_REG(0x40), 0x50 },
  117. { ADF4371_REG(0x41), 0x28 },
  118. { ADF4371_REG(0x47), 0xC0 },
  119. { ADF4371_REG(0x52), 0xF4 },
  120. { ADF4371_REG(0x70), 0x03 },
  121. { ADF4371_REG(0x71), 0x60 },
  122. { ADF4371_REG(0x72), 0x32 },
  123. };
  124. static const struct regmap_config adf4371_regmap_config = {
  125. .reg_bits = 16,
  126. .val_bits = 8,
  127. .read_flag_mask = BIT(7),
  128. };
  129. struct adf4371_chip_info {
  130. unsigned int num_channels;
  131. const struct iio_chan_spec *channels;
  132. };
  133. struct adf4371_state {
  134. struct spi_device *spi;
  135. struct regmap *regmap;
  136. struct clk *clkin;
  137. /*
  138. * Lock for accessing device registers. Some operations require
  139. * multiple consecutive R/W operations, during which the device
  140. * shouldn't be interrupted. The buffers are also shared across
  141. * all operations so need to be protected on stand alone reads and
  142. * writes.
  143. */
  144. struct mutex lock;
  145. const struct adf4371_chip_info *chip_info;
  146. unsigned long clkin_freq;
  147. unsigned long fpfd;
  148. unsigned int integer;
  149. unsigned int fract1;
  150. unsigned int fract2;
  151. unsigned int mod2;
  152. unsigned int rf_div_sel;
  153. unsigned int ref_div_factor;
  154. u8 buf[10] ____cacheline_aligned;
  155. };
  156. static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st,
  157. u32 channel)
  158. {
  159. unsigned long long val, tmp;
  160. unsigned int ref_div_sel;
  161. val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd;
  162. tmp = (u64)st->fract2 * st->fpfd;
  163. do_div(tmp, st->mod2);
  164. val += tmp + ADF4371_MODULUS1 / 2;
  165. if (channel == ADF4371_CH_RF8 || channel == ADF4371_CH_RFAUX8)
  166. ref_div_sel = st->rf_div_sel;
  167. else
  168. ref_div_sel = 0;
  169. do_div(val, ADF4371_MODULUS1 * (1 << ref_div_sel));
  170. if (channel == ADF4371_CH_RF16)
  171. val <<= 1;
  172. else if (channel == ADF4371_CH_RF32)
  173. val <<= 2;
  174. return val;
  175. }
  176. static void adf4371_pll_fract_n_compute(unsigned long long vco,
  177. unsigned long long pfd,
  178. unsigned int *integer,
  179. unsigned int *fract1,
  180. unsigned int *fract2,
  181. unsigned int *mod2)
  182. {
  183. unsigned long long tmp;
  184. u32 gcd_div;
  185. tmp = do_div(vco, pfd);
  186. tmp = tmp * ADF4371_MODULUS1;
  187. *fract2 = do_div(tmp, pfd);
  188. *integer = vco;
  189. *fract1 = tmp;
  190. *mod2 = pfd;
  191. while (*mod2 > ADF4371_MAX_MODULUS2) {
  192. *mod2 >>= 1;
  193. *fract2 >>= 1;
  194. }
  195. gcd_div = gcd(*fract2, *mod2);
  196. *mod2 /= gcd_div;
  197. *fract2 /= gcd_div;
  198. }
  199. static int adf4371_set_freq(struct adf4371_state *st, unsigned long long freq,
  200. unsigned int channel)
  201. {
  202. u32 cp_bleed;
  203. u8 int_mode = 0;
  204. int ret;
  205. switch (channel) {
  206. case ADF4371_CH_RF8:
  207. case ADF4371_CH_RFAUX8:
  208. if (ADF4371_CHECK_RANGE(freq, OUT_RF8_FREQ))
  209. return -EINVAL;
  210. st->rf_div_sel = 0;
  211. while (freq < ADF4371_MIN_VCO_FREQ) {
  212. freq <<= 1;
  213. st->rf_div_sel++;
  214. }
  215. break;
  216. case ADF4371_CH_RF16:
  217. /* ADF4371 RF16 8000...16000 MHz */
  218. if (ADF4371_CHECK_RANGE(freq, OUT_RF16_FREQ))
  219. return -EINVAL;
  220. freq >>= 1;
  221. break;
  222. case ADF4371_CH_RF32:
  223. /* ADF4371 RF32 16000...32000 MHz */
  224. if (ADF4371_CHECK_RANGE(freq, OUT_RF32_FREQ))
  225. return -EINVAL;
  226. freq >>= 2;
  227. break;
  228. default:
  229. return -EINVAL;
  230. }
  231. adf4371_pll_fract_n_compute(freq, st->fpfd, &st->integer, &st->fract1,
  232. &st->fract2, &st->mod2);
  233. st->buf[0] = st->integer >> 8;
  234. st->buf[1] = 0x40; /* REG12 default */
  235. st->buf[2] = 0x00;
  236. st->buf[3] = st->fract1 & 0xFF;
  237. st->buf[4] = st->fract1 >> 8;
  238. st->buf[5] = st->fract1 >> 16;
  239. st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) |
  240. ADF4371_FRAC1WORD(st->fract1 >> 24);
  241. st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7);
  242. st->buf[8] = st->mod2 & 0xFF;
  243. st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8);
  244. ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10);
  245. if (ret < 0)
  246. return ret;
  247. /*
  248. * The R counter allows the input reference frequency to be
  249. * divided down to produce the reference clock to the PFD
  250. */
  251. ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor);
  252. if (ret < 0)
  253. return ret;
  254. ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24),
  255. ADF4371_RF_DIV_SEL_MSK,
  256. ADF4371_RF_DIV_SEL(st->rf_div_sel));
  257. if (ret < 0)
  258. return ret;
  259. cp_bleed = DIV_ROUND_UP(400 * 1750, st->integer * 375);
  260. cp_bleed = clamp(cp_bleed, 1U, 255U);
  261. ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed);
  262. if (ret < 0)
  263. return ret;
  264. /*
  265. * Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0),
  266. * and set to 0 when in FRAC mode.
  267. */
  268. if (st->fract1 == 0 && st->fract2 == 0)
  269. int_mode = 0x01;
  270. ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode);
  271. if (ret < 0)
  272. return ret;
  273. return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF);
  274. }
  275. static ssize_t adf4371_read(struct iio_dev *indio_dev,
  276. uintptr_t private,
  277. const struct iio_chan_spec *chan,
  278. char *buf)
  279. {
  280. struct adf4371_state *st = iio_priv(indio_dev);
  281. unsigned long long val = 0;
  282. unsigned int readval, reg, bit;
  283. int ret;
  284. switch ((u32)private) {
  285. case ADF4371_FREQ:
  286. val = adf4371_pll_fract_n_get_rate(st, chan->channel);
  287. ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval);
  288. if (ret < 0)
  289. break;
  290. if (readval == 0x00) {
  291. dev_dbg(&st->spi->dev, "PLL un-locked\n");
  292. ret = -EBUSY;
  293. }
  294. break;
  295. case ADF4371_POWER_DOWN:
  296. reg = adf4371_pwrdown_ch[chan->channel].reg;
  297. bit = adf4371_pwrdown_ch[chan->channel].bit;
  298. ret = regmap_read(st->regmap, reg, &readval);
  299. if (ret < 0)
  300. break;
  301. val = !(readval & BIT(bit));
  302. break;
  303. case ADF4371_CHANNEL_NAME:
  304. return sprintf(buf, "%s\n", adf4371_ch_names[chan->channel]);
  305. default:
  306. ret = -EINVAL;
  307. val = 0;
  308. break;
  309. }
  310. return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
  311. }
  312. static ssize_t adf4371_write(struct iio_dev *indio_dev,
  313. uintptr_t private,
  314. const struct iio_chan_spec *chan,
  315. const char *buf, size_t len)
  316. {
  317. struct adf4371_state *st = iio_priv(indio_dev);
  318. unsigned long long freq;
  319. bool power_down;
  320. unsigned int bit, readval, reg;
  321. int ret;
  322. mutex_lock(&st->lock);
  323. switch ((u32)private) {
  324. case ADF4371_FREQ:
  325. ret = kstrtoull(buf, 10, &freq);
  326. if (ret)
  327. break;
  328. ret = adf4371_set_freq(st, freq, chan->channel);
  329. break;
  330. case ADF4371_POWER_DOWN:
  331. ret = kstrtobool(buf, &power_down);
  332. if (ret)
  333. break;
  334. reg = adf4371_pwrdown_ch[chan->channel].reg;
  335. bit = adf4371_pwrdown_ch[chan->channel].bit;
  336. ret = regmap_read(st->regmap, reg, &readval);
  337. if (ret < 0)
  338. break;
  339. readval &= ~BIT(bit);
  340. readval |= (!power_down << bit);
  341. ret = regmap_write(st->regmap, reg, readval);
  342. break;
  343. default:
  344. ret = -EINVAL;
  345. break;
  346. }
  347. mutex_unlock(&st->lock);
  348. return ret ? ret : len;
  349. }
  350. #define _ADF4371_EXT_INFO(_name, _ident) { \
  351. .name = _name, \
  352. .read = adf4371_read, \
  353. .write = adf4371_write, \
  354. .private = _ident, \
  355. .shared = IIO_SEPARATE, \
  356. }
  357. static const struct iio_chan_spec_ext_info adf4371_ext_info[] = {
  358. /*
  359. * Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
  360. * values > 2^32 in order to support the entire frequency range
  361. * in Hz. Using scale is a bit ugly.
  362. */
  363. _ADF4371_EXT_INFO("frequency", ADF4371_FREQ),
  364. _ADF4371_EXT_INFO("powerdown", ADF4371_POWER_DOWN),
  365. _ADF4371_EXT_INFO("name", ADF4371_CHANNEL_NAME),
  366. { },
  367. };
  368. #define ADF4371_CHANNEL(index) { \
  369. .type = IIO_ALTVOLTAGE, \
  370. .output = 1, \
  371. .channel = index, \
  372. .ext_info = adf4371_ext_info, \
  373. .indexed = 1, \
  374. }
  375. static const struct iio_chan_spec adf4371_chan[] = {
  376. ADF4371_CHANNEL(ADF4371_CH_RF8),
  377. ADF4371_CHANNEL(ADF4371_CH_RFAUX8),
  378. ADF4371_CHANNEL(ADF4371_CH_RF16),
  379. ADF4371_CHANNEL(ADF4371_CH_RF32),
  380. };
  381. static const struct adf4371_chip_info adf4371_chip_info[] = {
  382. [ADF4371] = {
  383. .channels = adf4371_chan,
  384. .num_channels = 4,
  385. },
  386. [ADF4372] = {
  387. .channels = adf4371_chan,
  388. .num_channels = 3,
  389. }
  390. };
  391. static int adf4371_reg_access(struct iio_dev *indio_dev,
  392. unsigned int reg,
  393. unsigned int writeval,
  394. unsigned int *readval)
  395. {
  396. struct adf4371_state *st = iio_priv(indio_dev);
  397. if (readval)
  398. return regmap_read(st->regmap, reg, readval);
  399. else
  400. return regmap_write(st->regmap, reg, writeval);
  401. }
  402. static const struct iio_info adf4371_info = {
  403. .debugfs_reg_access = &adf4371_reg_access,
  404. };
  405. static int adf4371_setup(struct adf4371_state *st)
  406. {
  407. unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1;
  408. unsigned int vco_band_div, tmp;
  409. int ret;
  410. /* Perform a software reset */
  411. ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD);
  412. if (ret < 0)
  413. return ret;
  414. ret = regmap_multi_reg_write(st->regmap, adf4371_reg_defaults,
  415. ARRAY_SIZE(adf4371_reg_defaults));
  416. if (ret < 0)
  417. return ret;
  418. /* Mute to Lock Detect */
  419. if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) {
  420. ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25),
  421. ADF4371_MUTE_LD_MSK,
  422. ADF4371_MUTE_LD(1));
  423. if (ret < 0)
  424. return ret;
  425. }
  426. /* Set address in ascending order, so the bulk_write() will work */
  427. ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
  428. ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK,
  429. ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1));
  430. if (ret < 0)
  431. return ret;
  432. /*
  433. * Calculate and maximize PFD frequency
  434. * fPFD = REFIN × ((1 + D)/(R × (1 + T)))
  435. * Where D is the REFIN doubler bit, T is the reference divide by 2,
  436. * R is the reference division factor
  437. * TODO: it is assumed D and T equal 0.
  438. */
  439. do {
  440. st->ref_div_factor++;
  441. st->fpfd = st->clkin_freq / st->ref_div_factor;
  442. } while (st->fpfd > ADF4371_MAX_FREQ_PFD);
  443. /* Calculate Timeouts */
  444. vco_band_div = DIV_ROUND_UP(st->fpfd, 2400000U);
  445. tmp = DIV_ROUND_CLOSEST(st->fpfd, 1000000U);
  446. do {
  447. timeout++;
  448. if (timeout > 1023) {
  449. timeout = 2;
  450. synth_timeout++;
  451. }
  452. } while (synth_timeout * 1024 + timeout <= 20 * tmp);
  453. do {
  454. vco_alc_timeout++;
  455. } while (vco_alc_timeout * 1024 - timeout <= 50 * tmp);
  456. st->buf[0] = vco_band_div;
  457. st->buf[1] = timeout & 0xFF;
  458. st->buf[2] = ADF4371_TIMEOUT(timeout >> 8) | 0x04;
  459. st->buf[3] = synth_timeout;
  460. st->buf[4] = ADF4371_VCO_ALC_TOUT(vco_alc_timeout);
  461. return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5);
  462. }
  463. static void adf4371_clk_disable(void *data)
  464. {
  465. struct adf4371_state *st = data;
  466. clk_disable_unprepare(st->clkin);
  467. }
  468. static int adf4371_probe(struct spi_device *spi)
  469. {
  470. const struct spi_device_id *id = spi_get_device_id(spi);
  471. struct iio_dev *indio_dev;
  472. struct adf4371_state *st;
  473. struct regmap *regmap;
  474. int ret;
  475. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  476. if (!indio_dev)
  477. return -ENOMEM;
  478. regmap = devm_regmap_init_spi(spi, &adf4371_regmap_config);
  479. if (IS_ERR(regmap)) {
  480. dev_err(&spi->dev, "Error initializing spi regmap: %ld\n",
  481. PTR_ERR(regmap));
  482. return PTR_ERR(regmap);
  483. }
  484. st = iio_priv(indio_dev);
  485. spi_set_drvdata(spi, indio_dev);
  486. st->spi = spi;
  487. st->regmap = regmap;
  488. mutex_init(&st->lock);
  489. st->chip_info = &adf4371_chip_info[id->driver_data];
  490. indio_dev->name = id->name;
  491. indio_dev->info = &adf4371_info;
  492. indio_dev->modes = INDIO_DIRECT_MODE;
  493. indio_dev->channels = st->chip_info->channels;
  494. indio_dev->num_channels = st->chip_info->num_channels;
  495. st->clkin = devm_clk_get(&spi->dev, "clkin");
  496. if (IS_ERR(st->clkin))
  497. return PTR_ERR(st->clkin);
  498. ret = clk_prepare_enable(st->clkin);
  499. if (ret < 0)
  500. return ret;
  501. ret = devm_add_action_or_reset(&spi->dev, adf4371_clk_disable, st);
  502. if (ret)
  503. return ret;
  504. st->clkin_freq = clk_get_rate(st->clkin);
  505. ret = adf4371_setup(st);
  506. if (ret < 0) {
  507. dev_err(&spi->dev, "ADF4371 setup failed\n");
  508. return ret;
  509. }
  510. return devm_iio_device_register(&spi->dev, indio_dev);
  511. }
  512. static const struct spi_device_id adf4371_id_table[] = {
  513. { "adf4371", ADF4371 },
  514. { "adf4372", ADF4372 },
  515. {}
  516. };
  517. MODULE_DEVICE_TABLE(spi, adf4371_id_table);
  518. static const struct of_device_id adf4371_of_match[] = {
  519. { .compatible = "adi,adf4371" },
  520. { .compatible = "adi,adf4372" },
  521. { },
  522. };
  523. MODULE_DEVICE_TABLE(of, adf4371_of_match);
  524. static struct spi_driver adf4371_driver = {
  525. .driver = {
  526. .name = "adf4371",
  527. .of_match_table = adf4371_of_match,
  528. },
  529. .probe = adf4371_probe,
  530. .id_table = adf4371_id_table,
  531. };
  532. module_spi_driver(adf4371_driver);
  533. MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
  534. MODULE_DESCRIPTION("Analog Devices ADF4371 SPI PLL");
  535. MODULE_LICENSE("GPL");