ad5758.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * AD5758 Digital to analog converters driver
  4. *
  5. * Copyright 2018 Analog Devices Inc.
  6. *
  7. * TODO: Currently CRC is not supported in this driver
  8. */
  9. #include <linux/bsearch.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/property.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/gpio/consumer.h>
  18. #include <linux/iio/iio.h>
  19. #include <linux/iio/sysfs.h>
  20. /* AD5758 registers definition */
  21. #define AD5758_NOP 0x00
  22. #define AD5758_DAC_INPUT 0x01
  23. #define AD5758_DAC_OUTPUT 0x02
  24. #define AD5758_CLEAR_CODE 0x03
  25. #define AD5758_USER_GAIN 0x04
  26. #define AD5758_USER_OFFSET 0x05
  27. #define AD5758_DAC_CONFIG 0x06
  28. #define AD5758_SW_LDAC 0x07
  29. #define AD5758_KEY 0x08
  30. #define AD5758_GP_CONFIG1 0x09
  31. #define AD5758_GP_CONFIG2 0x0A
  32. #define AD5758_DCDC_CONFIG1 0x0B
  33. #define AD5758_DCDC_CONFIG2 0x0C
  34. #define AD5758_WDT_CONFIG 0x0F
  35. #define AD5758_DIGITAL_DIAG_CONFIG 0x10
  36. #define AD5758_ADC_CONFIG 0x11
  37. #define AD5758_FAULT_PIN_CONFIG 0x12
  38. #define AD5758_TWO_STAGE_READBACK_SELECT 0x13
  39. #define AD5758_DIGITAL_DIAG_RESULTS 0x14
  40. #define AD5758_ANALOG_DIAG_RESULTS 0x15
  41. #define AD5758_STATUS 0x16
  42. #define AD5758_CHIP_ID 0x17
  43. #define AD5758_FREQ_MONITOR 0x18
  44. #define AD5758_DEVICE_ID_0 0x19
  45. #define AD5758_DEVICE_ID_1 0x1A
  46. #define AD5758_DEVICE_ID_2 0x1B
  47. #define AD5758_DEVICE_ID_3 0x1C
  48. /* AD5758_DAC_CONFIG */
  49. #define AD5758_DAC_CONFIG_RANGE_MSK GENMASK(3, 0)
  50. #define AD5758_DAC_CONFIG_RANGE_MODE(x) (((x) & 0xF) << 0)
  51. #define AD5758_DAC_CONFIG_INT_EN_MSK BIT(5)
  52. #define AD5758_DAC_CONFIG_INT_EN_MODE(x) (((x) & 0x1) << 5)
  53. #define AD5758_DAC_CONFIG_OUT_EN_MSK BIT(6)
  54. #define AD5758_DAC_CONFIG_OUT_EN_MODE(x) (((x) & 0x1) << 6)
  55. #define AD5758_DAC_CONFIG_SR_EN_MSK BIT(8)
  56. #define AD5758_DAC_CONFIG_SR_EN_MODE(x) (((x) & 0x1) << 8)
  57. #define AD5758_DAC_CONFIG_SR_CLOCK_MSK GENMASK(12, 9)
  58. #define AD5758_DAC_CONFIG_SR_CLOCK_MODE(x) (((x) & 0xF) << 9)
  59. #define AD5758_DAC_CONFIG_SR_STEP_MSK GENMASK(15, 13)
  60. #define AD5758_DAC_CONFIG_SR_STEP_MODE(x) (((x) & 0x7) << 13)
  61. /* AD5758_KEY */
  62. #define AD5758_KEY_CODE_RESET_1 0x15FA
  63. #define AD5758_KEY_CODE_RESET_2 0xAF51
  64. #define AD5758_KEY_CODE_SINGLE_ADC_CONV 0x1ADC
  65. #define AD5758_KEY_CODE_RESET_WDT 0x0D06
  66. #define AD5758_KEY_CODE_CALIB_MEM_REFRESH 0xFCBA
  67. /* AD5758_DCDC_CONFIG1 */
  68. #define AD5758_DCDC_CONFIG1_DCDC_VPROG_MSK GENMASK(4, 0)
  69. #define AD5758_DCDC_CONFIG1_DCDC_VPROG_MODE(x) (((x) & 0x1F) << 0)
  70. #define AD5758_DCDC_CONFIG1_DCDC_MODE_MSK GENMASK(6, 5)
  71. #define AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(x) (((x) & 0x3) << 5)
  72. /* AD5758_DCDC_CONFIG2 */
  73. #define AD5758_DCDC_CONFIG2_ILIMIT_MSK GENMASK(3, 1)
  74. #define AD5758_DCDC_CONFIG2_ILIMIT_MODE(x) (((x) & 0x7) << 1)
  75. #define AD5758_DCDC_CONFIG2_INTR_SAT_3WI_MSK BIT(11)
  76. #define AD5758_DCDC_CONFIG2_BUSY_3WI_MSK BIT(12)
  77. /* AD5758_DIGITAL_DIAG_RESULTS */
  78. #define AD5758_CAL_MEM_UNREFRESHED_MSK BIT(15)
  79. /* AD5758_ADC_CONFIG */
  80. #define AD5758_ADC_CONFIG_PPC_BUF_EN(x) (((x) & 0x1) << 11)
  81. #define AD5758_ADC_CONFIG_PPC_BUF_MSK BIT(11)
  82. #define AD5758_WR_FLAG_MSK(x) (0x80 | ((x) & 0x1F))
  83. #define AD5758_FULL_SCALE_MICRO 65535000000ULL
  84. struct ad5758_range {
  85. int reg;
  86. int min;
  87. int max;
  88. };
  89. /**
  90. * struct ad5758_state - driver instance specific data
  91. * @spi: spi_device
  92. * @lock: mutex lock
  93. * @gpio_reset: gpio descriptor for the reset line
  94. * @out_range: struct which stores the output range
  95. * @dc_dc_mode: variable which stores the mode of operation
  96. * @dc_dc_ilim: variable which stores the dc-to-dc converter current limit
  97. * @slew_time: variable which stores the target slew time
  98. * @pwr_down: variable which contains whether a channel is powered down or not
  99. * @d32: spi transfer buffers
  100. */
  101. struct ad5758_state {
  102. struct spi_device *spi;
  103. struct mutex lock;
  104. struct gpio_desc *gpio_reset;
  105. struct ad5758_range out_range;
  106. unsigned int dc_dc_mode;
  107. unsigned int dc_dc_ilim;
  108. unsigned int slew_time;
  109. bool pwr_down;
  110. __be32 d32[3];
  111. };
  112. /*
  113. * Output ranges corresponding to bits [3:0] from DAC_CONFIG register
  114. * 0000: 0 V to 5 V voltage range
  115. * 0001: 0 V to 10 V voltage range
  116. * 0010: ±5 V voltage range
  117. * 0011: ±10 V voltage range
  118. * 1000: 0 mA to 20 mA current range
  119. * 1001: 0 mA to 24 mA current range
  120. * 1010: 4 mA to 20 mA current range
  121. * 1011: ±20 mA current range
  122. * 1100: ±24 mA current range
  123. * 1101: -1 mA to +22 mA current range
  124. */
  125. enum ad5758_output_range {
  126. AD5758_RANGE_0V_5V,
  127. AD5758_RANGE_0V_10V,
  128. AD5758_RANGE_PLUSMINUS_5V,
  129. AD5758_RANGE_PLUSMINUS_10V,
  130. AD5758_RANGE_0mA_20mA = 8,
  131. AD5758_RANGE_0mA_24mA,
  132. AD5758_RANGE_4mA_24mA,
  133. AD5758_RANGE_PLUSMINUS_20mA,
  134. AD5758_RANGE_PLUSMINUS_24mA,
  135. AD5758_RANGE_MINUS_1mA_PLUS_22mA,
  136. };
  137. enum ad5758_dc_dc_mode {
  138. AD5758_DCDC_MODE_POWER_OFF,
  139. AD5758_DCDC_MODE_DPC_CURRENT,
  140. AD5758_DCDC_MODE_DPC_VOLTAGE,
  141. AD5758_DCDC_MODE_PPC_CURRENT,
  142. };
  143. static const struct ad5758_range ad5758_voltage_range[] = {
  144. { AD5758_RANGE_0V_5V, 0, 5000000 },
  145. { AD5758_RANGE_0V_10V, 0, 10000000 },
  146. { AD5758_RANGE_PLUSMINUS_5V, -5000000, 5000000 },
  147. { AD5758_RANGE_PLUSMINUS_10V, -10000000, 10000000 }
  148. };
  149. static const struct ad5758_range ad5758_current_range[] = {
  150. { AD5758_RANGE_0mA_20mA, 0, 20000},
  151. { AD5758_RANGE_0mA_24mA, 0, 24000 },
  152. { AD5758_RANGE_4mA_24mA, 4, 24000 },
  153. { AD5758_RANGE_PLUSMINUS_20mA, -20000, 20000 },
  154. { AD5758_RANGE_PLUSMINUS_24mA, -24000, 24000 },
  155. { AD5758_RANGE_MINUS_1mA_PLUS_22mA, -1000, 22000 },
  156. };
  157. static const int ad5758_sr_clk[16] = {
  158. 240000, 200000, 150000, 128000, 64000, 32000, 16000, 8000, 4000, 2000,
  159. 1000, 512, 256, 128, 64, 16
  160. };
  161. static const int ad5758_sr_step[8] = {
  162. 4, 12, 64, 120, 256, 500, 1820, 2048
  163. };
  164. static const int ad5758_dc_dc_ilim[6] = {
  165. 150000, 200000, 250000, 300000, 350000, 400000
  166. };
  167. static int ad5758_spi_reg_read(struct ad5758_state *st, unsigned int addr)
  168. {
  169. struct spi_transfer t[] = {
  170. {
  171. .tx_buf = &st->d32[0],
  172. .len = 4,
  173. .cs_change = 1,
  174. }, {
  175. .tx_buf = &st->d32[1],
  176. .rx_buf = &st->d32[2],
  177. .len = 4,
  178. },
  179. };
  180. int ret;
  181. st->d32[0] = cpu_to_be32(
  182. (AD5758_WR_FLAG_MSK(AD5758_TWO_STAGE_READBACK_SELECT) << 24) |
  183. (addr << 8));
  184. st->d32[1] = cpu_to_be32(AD5758_WR_FLAG_MSK(AD5758_NOP) << 24);
  185. ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
  186. if (ret < 0)
  187. return ret;
  188. return (be32_to_cpu(st->d32[2]) >> 8) & 0xFFFF;
  189. }
  190. static int ad5758_spi_reg_write(struct ad5758_state *st,
  191. unsigned int addr,
  192. unsigned int val)
  193. {
  194. st->d32[0] = cpu_to_be32((AD5758_WR_FLAG_MSK(addr) << 24) |
  195. ((val & 0xFFFF) << 8));
  196. return spi_write(st->spi, &st->d32[0], sizeof(st->d32[0]));
  197. }
  198. static int ad5758_spi_write_mask(struct ad5758_state *st,
  199. unsigned int addr,
  200. unsigned long int mask,
  201. unsigned int val)
  202. {
  203. int regval;
  204. regval = ad5758_spi_reg_read(st, addr);
  205. if (regval < 0)
  206. return regval;
  207. regval &= ~mask;
  208. regval |= val;
  209. return ad5758_spi_reg_write(st, addr, regval);
  210. }
  211. static int cmpfunc(const void *a, const void *b)
  212. {
  213. return *(int *)a - *(int *)b;
  214. }
  215. static int ad5758_find_closest_match(const int *array,
  216. unsigned int size, int val)
  217. {
  218. int i;
  219. for (i = 0; i < size; i++) {
  220. if (val <= array[i])
  221. return i;
  222. }
  223. return size - 1;
  224. }
  225. static int ad5758_wait_for_task_complete(struct ad5758_state *st,
  226. unsigned int reg,
  227. unsigned int mask)
  228. {
  229. unsigned int timeout;
  230. int ret;
  231. timeout = 10;
  232. do {
  233. ret = ad5758_spi_reg_read(st, reg);
  234. if (ret < 0)
  235. return ret;
  236. if (!(ret & mask))
  237. return 0;
  238. usleep_range(100, 1000);
  239. } while (--timeout);
  240. dev_err(&st->spi->dev,
  241. "Error reading bit 0x%x in 0x%x register\n", mask, reg);
  242. return -EIO;
  243. }
  244. static int ad5758_calib_mem_refresh(struct ad5758_state *st)
  245. {
  246. int ret;
  247. ret = ad5758_spi_reg_write(st, AD5758_KEY,
  248. AD5758_KEY_CODE_CALIB_MEM_REFRESH);
  249. if (ret < 0) {
  250. dev_err(&st->spi->dev,
  251. "Failed to initiate a calibration memory refresh\n");
  252. return ret;
  253. }
  254. /* Wait to allow time for the internal calibrations to complete */
  255. return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
  256. AD5758_CAL_MEM_UNREFRESHED_MSK);
  257. }
  258. static int ad5758_soft_reset(struct ad5758_state *st)
  259. {
  260. int ret;
  261. ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_1);
  262. if (ret < 0)
  263. return ret;
  264. ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_2);
  265. /* Perform a software reset and wait at least 100us */
  266. usleep_range(100, 1000);
  267. return ret;
  268. }
  269. static int ad5758_set_dc_dc_conv_mode(struct ad5758_state *st,
  270. enum ad5758_dc_dc_mode mode)
  271. {
  272. int ret;
  273. /*
  274. * The ENABLE_PPC_BUFFERS bit must be set prior to enabling PPC current
  275. * mode.
  276. */
  277. if (mode == AD5758_DCDC_MODE_PPC_CURRENT) {
  278. ret = ad5758_spi_write_mask(st, AD5758_ADC_CONFIG,
  279. AD5758_ADC_CONFIG_PPC_BUF_MSK,
  280. AD5758_ADC_CONFIG_PPC_BUF_EN(1));
  281. if (ret < 0)
  282. return ret;
  283. }
  284. ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1,
  285. AD5758_DCDC_CONFIG1_DCDC_MODE_MSK,
  286. AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(mode));
  287. if (ret < 0)
  288. return ret;
  289. /*
  290. * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0.
  291. * This allows the 3-wire interface communication to complete.
  292. */
  293. ret = ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2,
  294. AD5758_DCDC_CONFIG2_BUSY_3WI_MSK);
  295. if (ret < 0)
  296. return ret;
  297. st->dc_dc_mode = mode;
  298. return ret;
  299. }
  300. static int ad5758_set_dc_dc_ilim(struct ad5758_state *st, unsigned int ilim)
  301. {
  302. int ret;
  303. ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG2,
  304. AD5758_DCDC_CONFIG2_ILIMIT_MSK,
  305. AD5758_DCDC_CONFIG2_ILIMIT_MODE(ilim));
  306. if (ret < 0)
  307. return ret;
  308. /*
  309. * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0.
  310. * This allows the 3-wire interface communication to complete.
  311. */
  312. return ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2,
  313. AD5758_DCDC_CONFIG2_BUSY_3WI_MSK);
  314. }
  315. static int ad5758_slew_rate_set(struct ad5758_state *st,
  316. unsigned int sr_clk_idx,
  317. unsigned int sr_step_idx)
  318. {
  319. unsigned int mode;
  320. unsigned long int mask;
  321. int ret;
  322. mask = AD5758_DAC_CONFIG_SR_EN_MSK |
  323. AD5758_DAC_CONFIG_SR_CLOCK_MSK |
  324. AD5758_DAC_CONFIG_SR_STEP_MSK;
  325. mode = AD5758_DAC_CONFIG_SR_EN_MODE(1) |
  326. AD5758_DAC_CONFIG_SR_STEP_MODE(sr_step_idx) |
  327. AD5758_DAC_CONFIG_SR_CLOCK_MODE(sr_clk_idx);
  328. ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, mask, mode);
  329. if (ret < 0)
  330. return ret;
  331. /* Wait to allow time for the internal calibrations to complete */
  332. return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
  333. AD5758_CAL_MEM_UNREFRESHED_MSK);
  334. }
  335. static int ad5758_slew_rate_config(struct ad5758_state *st)
  336. {
  337. unsigned int sr_clk_idx, sr_step_idx;
  338. int i, res;
  339. s64 diff_new, diff_old;
  340. u64 sr_step, calc_slew_time;
  341. sr_clk_idx = 0;
  342. sr_step_idx = 0;
  343. diff_old = S64_MAX;
  344. /*
  345. * The slew time can be determined by using the formula:
  346. * Slew Time = (Full Scale Out / (Step Size x Update Clk Freq))
  347. * where Slew time is expressed in microseconds
  348. * Given the desired slew time, the following algorithm determines the
  349. * best match for the step size and the update clock frequency.
  350. */
  351. for (i = 0; i < ARRAY_SIZE(ad5758_sr_clk); i++) {
  352. /*
  353. * Go through each valid update clock freq and determine a raw
  354. * value for the step size by using the formula:
  355. * Step Size = Full Scale Out / (Update Clk Freq * Slew Time)
  356. */
  357. sr_step = AD5758_FULL_SCALE_MICRO;
  358. do_div(sr_step, ad5758_sr_clk[i]);
  359. do_div(sr_step, st->slew_time);
  360. /*
  361. * After a raw value for step size was determined, find the
  362. * closest valid match
  363. */
  364. res = ad5758_find_closest_match(ad5758_sr_step,
  365. ARRAY_SIZE(ad5758_sr_step),
  366. sr_step);
  367. /* Calculate the slew time */
  368. calc_slew_time = AD5758_FULL_SCALE_MICRO;
  369. do_div(calc_slew_time, ad5758_sr_step[res]);
  370. do_div(calc_slew_time, ad5758_sr_clk[i]);
  371. /*
  372. * Determine with how many microseconds the calculated slew time
  373. * is different from the desired slew time and store the diff
  374. * for the next iteration
  375. */
  376. diff_new = abs(st->slew_time - calc_slew_time);
  377. if (diff_new < diff_old) {
  378. diff_old = diff_new;
  379. sr_clk_idx = i;
  380. sr_step_idx = res;
  381. }
  382. }
  383. return ad5758_slew_rate_set(st, sr_clk_idx, sr_step_idx);
  384. }
  385. static int ad5758_set_out_range(struct ad5758_state *st, int range)
  386. {
  387. int ret;
  388. ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
  389. AD5758_DAC_CONFIG_RANGE_MSK,
  390. AD5758_DAC_CONFIG_RANGE_MODE(range));
  391. if (ret < 0)
  392. return ret;
  393. /* Wait to allow time for the internal calibrations to complete */
  394. return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
  395. AD5758_CAL_MEM_UNREFRESHED_MSK);
  396. }
  397. static int ad5758_internal_buffers_en(struct ad5758_state *st, bool enable)
  398. {
  399. int ret;
  400. ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
  401. AD5758_DAC_CONFIG_INT_EN_MSK,
  402. AD5758_DAC_CONFIG_INT_EN_MODE(enable));
  403. if (ret < 0)
  404. return ret;
  405. /* Wait to allow time for the internal calibrations to complete */
  406. return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
  407. AD5758_CAL_MEM_UNREFRESHED_MSK);
  408. }
  409. static int ad5758_reset(struct ad5758_state *st)
  410. {
  411. if (st->gpio_reset) {
  412. gpiod_set_value(st->gpio_reset, 0);
  413. usleep_range(100, 1000);
  414. gpiod_set_value(st->gpio_reset, 1);
  415. usleep_range(100, 1000);
  416. return 0;
  417. } else {
  418. /* Perform a software reset */
  419. return ad5758_soft_reset(st);
  420. }
  421. }
  422. static int ad5758_reg_access(struct iio_dev *indio_dev,
  423. unsigned int reg,
  424. unsigned int writeval,
  425. unsigned int *readval)
  426. {
  427. struct ad5758_state *st = iio_priv(indio_dev);
  428. int ret;
  429. mutex_lock(&st->lock);
  430. if (readval) {
  431. ret = ad5758_spi_reg_read(st, reg);
  432. if (ret < 0) {
  433. mutex_unlock(&st->lock);
  434. return ret;
  435. }
  436. *readval = ret;
  437. ret = 0;
  438. } else {
  439. ret = ad5758_spi_reg_write(st, reg, writeval);
  440. }
  441. mutex_unlock(&st->lock);
  442. return ret;
  443. }
  444. static int ad5758_read_raw(struct iio_dev *indio_dev,
  445. struct iio_chan_spec const *chan,
  446. int *val, int *val2, long info)
  447. {
  448. struct ad5758_state *st = iio_priv(indio_dev);
  449. int max, min, ret;
  450. switch (info) {
  451. case IIO_CHAN_INFO_RAW:
  452. mutex_lock(&st->lock);
  453. ret = ad5758_spi_reg_read(st, AD5758_DAC_INPUT);
  454. mutex_unlock(&st->lock);
  455. if (ret < 0)
  456. return ret;
  457. *val = ret;
  458. return IIO_VAL_INT;
  459. case IIO_CHAN_INFO_SCALE:
  460. min = st->out_range.min;
  461. max = st->out_range.max;
  462. *val = (max - min) / 1000;
  463. *val2 = 16;
  464. return IIO_VAL_FRACTIONAL_LOG2;
  465. case IIO_CHAN_INFO_OFFSET:
  466. min = st->out_range.min;
  467. max = st->out_range.max;
  468. *val = ((min * (1 << 16)) / (max - min)) / 1000;
  469. return IIO_VAL_INT;
  470. default:
  471. return -EINVAL;
  472. }
  473. }
  474. static int ad5758_write_raw(struct iio_dev *indio_dev,
  475. struct iio_chan_spec const *chan,
  476. int val, int val2, long info)
  477. {
  478. struct ad5758_state *st = iio_priv(indio_dev);
  479. int ret;
  480. switch (info) {
  481. case IIO_CHAN_INFO_RAW:
  482. mutex_lock(&st->lock);
  483. ret = ad5758_spi_reg_write(st, AD5758_DAC_INPUT, val);
  484. mutex_unlock(&st->lock);
  485. return ret;
  486. default:
  487. return -EINVAL;
  488. }
  489. }
  490. static ssize_t ad5758_read_powerdown(struct iio_dev *indio_dev,
  491. uintptr_t priv,
  492. const struct iio_chan_spec *chan,
  493. char *buf)
  494. {
  495. struct ad5758_state *st = iio_priv(indio_dev);
  496. return sprintf(buf, "%d\n", st->pwr_down);
  497. }
  498. static ssize_t ad5758_write_powerdown(struct iio_dev *indio_dev,
  499. uintptr_t priv,
  500. struct iio_chan_spec const *chan,
  501. const char *buf, size_t len)
  502. {
  503. struct ad5758_state *st = iio_priv(indio_dev);
  504. bool pwr_down;
  505. unsigned int dac_config_mode, val;
  506. unsigned long int dac_config_msk;
  507. int ret;
  508. ret = kstrtobool(buf, &pwr_down);
  509. if (ret)
  510. return ret;
  511. mutex_lock(&st->lock);
  512. if (pwr_down)
  513. val = 0;
  514. else
  515. val = 1;
  516. dac_config_mode = AD5758_DAC_CONFIG_OUT_EN_MODE(val) |
  517. AD5758_DAC_CONFIG_INT_EN_MODE(val);
  518. dac_config_msk = AD5758_DAC_CONFIG_OUT_EN_MSK |
  519. AD5758_DAC_CONFIG_INT_EN_MSK;
  520. ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
  521. dac_config_msk,
  522. dac_config_mode);
  523. if (ret < 0)
  524. goto err_unlock;
  525. st->pwr_down = pwr_down;
  526. err_unlock:
  527. mutex_unlock(&st->lock);
  528. return ret ? ret : len;
  529. }
  530. static const struct iio_info ad5758_info = {
  531. .read_raw = ad5758_read_raw,
  532. .write_raw = ad5758_write_raw,
  533. .debugfs_reg_access = &ad5758_reg_access,
  534. };
  535. static const struct iio_chan_spec_ext_info ad5758_ext_info[] = {
  536. {
  537. .name = "powerdown",
  538. .read = ad5758_read_powerdown,
  539. .write = ad5758_write_powerdown,
  540. .shared = IIO_SHARED_BY_TYPE,
  541. },
  542. { }
  543. };
  544. #define AD5758_DAC_CHAN(_chan_type) { \
  545. .type = (_chan_type), \
  546. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \
  547. BIT(IIO_CHAN_INFO_SCALE) | \
  548. BIT(IIO_CHAN_INFO_OFFSET), \
  549. .indexed = 1, \
  550. .output = 1, \
  551. .ext_info = ad5758_ext_info, \
  552. }
  553. static const struct iio_chan_spec ad5758_voltage_ch[] = {
  554. AD5758_DAC_CHAN(IIO_VOLTAGE)
  555. };
  556. static const struct iio_chan_spec ad5758_current_ch[] = {
  557. AD5758_DAC_CHAN(IIO_CURRENT)
  558. };
  559. static bool ad5758_is_valid_mode(enum ad5758_dc_dc_mode mode)
  560. {
  561. switch (mode) {
  562. case AD5758_DCDC_MODE_DPC_CURRENT:
  563. case AD5758_DCDC_MODE_DPC_VOLTAGE:
  564. case AD5758_DCDC_MODE_PPC_CURRENT:
  565. return true;
  566. default:
  567. return false;
  568. }
  569. }
  570. static int ad5758_crc_disable(struct ad5758_state *st)
  571. {
  572. unsigned int mask;
  573. mask = (AD5758_WR_FLAG_MSK(AD5758_DIGITAL_DIAG_CONFIG) << 24) | 0x5C3A;
  574. st->d32[0] = cpu_to_be32(mask);
  575. return spi_write(st->spi, &st->d32[0], 4);
  576. }
  577. static int ad5758_find_out_range(struct ad5758_state *st,
  578. const struct ad5758_range *range,
  579. unsigned int size,
  580. int min, int max)
  581. {
  582. int i;
  583. for (i = 0; i < size; i++) {
  584. if ((min == range[i].min) && (max == range[i].max)) {
  585. st->out_range.reg = range[i].reg;
  586. st->out_range.min = range[i].min;
  587. st->out_range.max = range[i].max;
  588. return 0;
  589. }
  590. }
  591. return -EINVAL;
  592. }
  593. static int ad5758_parse_dt(struct ad5758_state *st)
  594. {
  595. unsigned int tmp, tmparray[2], size;
  596. const struct ad5758_range *range;
  597. int *index, ret;
  598. st->dc_dc_ilim = 0;
  599. ret = device_property_read_u32(&st->spi->dev,
  600. "adi,dc-dc-ilim-microamp", &tmp);
  601. if (ret) {
  602. dev_dbg(&st->spi->dev,
  603. "Missing \"dc-dc-ilim-microamp\" property\n");
  604. } else {
  605. index = bsearch(&tmp, ad5758_dc_dc_ilim,
  606. ARRAY_SIZE(ad5758_dc_dc_ilim),
  607. sizeof(int), cmpfunc);
  608. if (!index)
  609. dev_dbg(&st->spi->dev, "dc-dc-ilim out of range\n");
  610. else
  611. st->dc_dc_ilim = index - ad5758_dc_dc_ilim;
  612. }
  613. ret = device_property_read_u32(&st->spi->dev, "adi,dc-dc-mode",
  614. &st->dc_dc_mode);
  615. if (ret) {
  616. dev_err(&st->spi->dev, "Missing \"dc-dc-mode\" property\n");
  617. return ret;
  618. }
  619. if (!ad5758_is_valid_mode(st->dc_dc_mode))
  620. return -EINVAL;
  621. if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE) {
  622. ret = device_property_read_u32_array(&st->spi->dev,
  623. "adi,range-microvolt",
  624. tmparray, 2);
  625. if (ret) {
  626. dev_err(&st->spi->dev,
  627. "Missing \"range-microvolt\" property\n");
  628. return ret;
  629. }
  630. range = ad5758_voltage_range;
  631. size = ARRAY_SIZE(ad5758_voltage_range);
  632. } else {
  633. ret = device_property_read_u32_array(&st->spi->dev,
  634. "adi,range-microamp",
  635. tmparray, 2);
  636. if (ret) {
  637. dev_err(&st->spi->dev,
  638. "Missing \"range-microamp\" property\n");
  639. return ret;
  640. }
  641. range = ad5758_current_range;
  642. size = ARRAY_SIZE(ad5758_current_range);
  643. }
  644. ret = ad5758_find_out_range(st, range, size, tmparray[0], tmparray[1]);
  645. if (ret) {
  646. dev_err(&st->spi->dev, "range invalid\n");
  647. return ret;
  648. }
  649. ret = device_property_read_u32(&st->spi->dev, "adi,slew-time-us", &tmp);
  650. if (ret) {
  651. dev_dbg(&st->spi->dev, "Missing \"slew-time-us\" property\n");
  652. st->slew_time = 0;
  653. } else {
  654. st->slew_time = tmp;
  655. }
  656. return 0;
  657. }
  658. static int ad5758_init(struct ad5758_state *st)
  659. {
  660. int regval, ret;
  661. st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
  662. GPIOD_OUT_HIGH);
  663. if (IS_ERR(st->gpio_reset))
  664. return PTR_ERR(st->gpio_reset);
  665. /* Disable CRC checks */
  666. ret = ad5758_crc_disable(st);
  667. if (ret < 0)
  668. return ret;
  669. /* Perform a reset */
  670. ret = ad5758_reset(st);
  671. if (ret < 0)
  672. return ret;
  673. /* Disable CRC checks */
  674. ret = ad5758_crc_disable(st);
  675. if (ret < 0)
  676. return ret;
  677. /* Perform a calibration memory refresh */
  678. ret = ad5758_calib_mem_refresh(st);
  679. if (ret < 0)
  680. return ret;
  681. regval = ad5758_spi_reg_read(st, AD5758_DIGITAL_DIAG_RESULTS);
  682. if (regval < 0)
  683. return regval;
  684. /* Clear all the error flags */
  685. ret = ad5758_spi_reg_write(st, AD5758_DIGITAL_DIAG_RESULTS, regval);
  686. if (ret < 0)
  687. return ret;
  688. /* Set the dc-to-dc current limit */
  689. ret = ad5758_set_dc_dc_ilim(st, st->dc_dc_ilim);
  690. if (ret < 0)
  691. return ret;
  692. /* Configure the dc-to-dc controller mode */
  693. ret = ad5758_set_dc_dc_conv_mode(st, st->dc_dc_mode);
  694. if (ret < 0)
  695. return ret;
  696. /* Configure the output range */
  697. ret = ad5758_set_out_range(st, st->out_range.reg);
  698. if (ret < 0)
  699. return ret;
  700. /* Enable Slew Rate Control, set the slew rate clock and step */
  701. if (st->slew_time) {
  702. ret = ad5758_slew_rate_config(st);
  703. if (ret < 0)
  704. return ret;
  705. }
  706. /* Power up the DAC and internal (INT) amplifiers */
  707. ret = ad5758_internal_buffers_en(st, 1);
  708. if (ret < 0)
  709. return ret;
  710. /* Enable VIOUT */
  711. return ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
  712. AD5758_DAC_CONFIG_OUT_EN_MSK,
  713. AD5758_DAC_CONFIG_OUT_EN_MODE(1));
  714. }
  715. static int ad5758_probe(struct spi_device *spi)
  716. {
  717. struct ad5758_state *st;
  718. struct iio_dev *indio_dev;
  719. int ret;
  720. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  721. if (!indio_dev)
  722. return -ENOMEM;
  723. st = iio_priv(indio_dev);
  724. spi_set_drvdata(spi, indio_dev);
  725. st->spi = spi;
  726. mutex_init(&st->lock);
  727. indio_dev->name = spi_get_device_id(spi)->name;
  728. indio_dev->info = &ad5758_info;
  729. indio_dev->modes = INDIO_DIRECT_MODE;
  730. indio_dev->num_channels = 1;
  731. ret = ad5758_parse_dt(st);
  732. if (ret < 0)
  733. return ret;
  734. if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE)
  735. indio_dev->channels = ad5758_voltage_ch;
  736. else
  737. indio_dev->channels = ad5758_current_ch;
  738. ret = ad5758_init(st);
  739. if (ret < 0) {
  740. dev_err(&spi->dev, "AD5758 init failed\n");
  741. return ret;
  742. }
  743. return devm_iio_device_register(&st->spi->dev, indio_dev);
  744. }
  745. static const struct spi_device_id ad5758_id[] = {
  746. { "ad5758", 0 },
  747. {}
  748. };
  749. MODULE_DEVICE_TABLE(spi, ad5758_id);
  750. static const struct of_device_id ad5758_of_match[] = {
  751. { .compatible = "adi,ad5758" },
  752. { },
  753. };
  754. MODULE_DEVICE_TABLE(of, ad5758_of_match);
  755. static struct spi_driver ad5758_driver = {
  756. .driver = {
  757. .name = KBUILD_MODNAME,
  758. .of_match_table = ad5758_of_match,
  759. },
  760. .probe = ad5758_probe,
  761. .id_table = ad5758_id,
  762. };
  763. module_spi_driver(ad5758_driver);
  764. MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
  765. MODULE_DESCRIPTION("Analog Devices AD5758 DAC");
  766. MODULE_LICENSE("GPL v2");