ad5755.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
  4. *
  5. * Copyright 2012 Analog Devices Inc.
  6. */
  7. #include <linux/device.h>
  8. #include <linux/err.h>
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/spi/spi.h>
  12. #include <linux/slab.h>
  13. #include <linux/sysfs.h>
  14. #include <linux/delay.h>
  15. #include <linux/of.h>
  16. #include <linux/iio/iio.h>
  17. #include <linux/iio/sysfs.h>
  18. #include <linux/platform_data/ad5755.h>
  19. #define AD5755_NUM_CHANNELS 4
  20. #define AD5755_ADDR(x) ((x) << 16)
  21. #define AD5755_WRITE_REG_DATA(chan) (chan)
  22. #define AD5755_WRITE_REG_GAIN(chan) (0x08 | (chan))
  23. #define AD5755_WRITE_REG_OFFSET(chan) (0x10 | (chan))
  24. #define AD5755_WRITE_REG_CTRL(chan) (0x1c | (chan))
  25. #define AD5755_READ_REG_DATA(chan) (chan)
  26. #define AD5755_READ_REG_CTRL(chan) (0x4 | (chan))
  27. #define AD5755_READ_REG_GAIN(chan) (0x8 | (chan))
  28. #define AD5755_READ_REG_OFFSET(chan) (0xc | (chan))
  29. #define AD5755_READ_REG_CLEAR(chan) (0x10 | (chan))
  30. #define AD5755_READ_REG_SLEW(chan) (0x14 | (chan))
  31. #define AD5755_READ_REG_STATUS 0x18
  32. #define AD5755_READ_REG_MAIN 0x19
  33. #define AD5755_READ_REG_DC_DC 0x1a
  34. #define AD5755_CTRL_REG_SLEW 0x0
  35. #define AD5755_CTRL_REG_MAIN 0x1
  36. #define AD5755_CTRL_REG_DAC 0x2
  37. #define AD5755_CTRL_REG_DC_DC 0x3
  38. #define AD5755_CTRL_REG_SW 0x4
  39. #define AD5755_READ_FLAG 0x800000
  40. #define AD5755_NOOP 0x1CE000
  41. #define AD5755_DAC_INT_EN BIT(8)
  42. #define AD5755_DAC_CLR_EN BIT(7)
  43. #define AD5755_DAC_OUT_EN BIT(6)
  44. #define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR BIT(5)
  45. #define AD5755_DAC_DC_DC_EN BIT(4)
  46. #define AD5755_DAC_VOLTAGE_OVERRANGE_EN BIT(3)
  47. #define AD5755_DC_DC_MAXV 0
  48. #define AD5755_DC_DC_FREQ_SHIFT 2
  49. #define AD5755_DC_DC_PHASE_SHIFT 4
  50. #define AD5755_EXT_DC_DC_COMP_RES BIT(6)
  51. #define AD5755_SLEW_STEP_SIZE_SHIFT 0
  52. #define AD5755_SLEW_RATE_SHIFT 3
  53. #define AD5755_SLEW_ENABLE BIT(12)
  54. /**
  55. * struct ad5755_chip_info - chip specific information
  56. * @channel_template: channel specification
  57. * @calib_shift: shift for the calibration data registers
  58. * @has_voltage_out: whether the chip has voltage outputs
  59. */
  60. struct ad5755_chip_info {
  61. const struct iio_chan_spec channel_template;
  62. unsigned int calib_shift;
  63. bool has_voltage_out;
  64. };
  65. /**
  66. * struct ad5755_state - driver instance specific data
  67. * @spi: spi device the driver is attached to
  68. * @chip_info: chip model specific constants, available modes etc
  69. * @pwr_down: bitmask which contains hether a channel is powered down or not
  70. * @ctrl: software shadow of the channel ctrl registers
  71. * @channels: iio channel spec for the device
  72. * @lock: lock to protect the data buffer during SPI ops
  73. * @data: spi transfer buffers
  74. */
  75. struct ad5755_state {
  76. struct spi_device *spi;
  77. const struct ad5755_chip_info *chip_info;
  78. unsigned int pwr_down;
  79. unsigned int ctrl[AD5755_NUM_CHANNELS];
  80. struct iio_chan_spec channels[AD5755_NUM_CHANNELS];
  81. struct mutex lock;
  82. /*
  83. * DMA (thus cache coherency maintenance) requires the
  84. * transfer buffers to live in their own cache lines.
  85. */
  86. union {
  87. __be32 d32;
  88. u8 d8[4];
  89. } data[2] ____cacheline_aligned;
  90. };
  91. enum ad5755_type {
  92. ID_AD5755,
  93. ID_AD5757,
  94. ID_AD5735,
  95. ID_AD5737,
  96. };
  97. #ifdef CONFIG_OF
  98. static const int ad5755_dcdc_freq_table[][2] = {
  99. { 250000, AD5755_DC_DC_FREQ_250kHZ },
  100. { 410000, AD5755_DC_DC_FREQ_410kHZ },
  101. { 650000, AD5755_DC_DC_FREQ_650kHZ }
  102. };
  103. static const int ad5755_dcdc_maxv_table[][2] = {
  104. { 23000000, AD5755_DC_DC_MAXV_23V },
  105. { 24500000, AD5755_DC_DC_MAXV_24V5 },
  106. { 27000000, AD5755_DC_DC_MAXV_27V },
  107. { 29500000, AD5755_DC_DC_MAXV_29V5 },
  108. };
  109. static const int ad5755_slew_rate_table[][2] = {
  110. { 64000, AD5755_SLEW_RATE_64k },
  111. { 32000, AD5755_SLEW_RATE_32k },
  112. { 16000, AD5755_SLEW_RATE_16k },
  113. { 8000, AD5755_SLEW_RATE_8k },
  114. { 4000, AD5755_SLEW_RATE_4k },
  115. { 2000, AD5755_SLEW_RATE_2k },
  116. { 1000, AD5755_SLEW_RATE_1k },
  117. { 500, AD5755_SLEW_RATE_500 },
  118. { 250, AD5755_SLEW_RATE_250 },
  119. { 125, AD5755_SLEW_RATE_125 },
  120. { 64, AD5755_SLEW_RATE_64 },
  121. { 32, AD5755_SLEW_RATE_32 },
  122. { 16, AD5755_SLEW_RATE_16 },
  123. { 8, AD5755_SLEW_RATE_8 },
  124. { 4, AD5755_SLEW_RATE_4 },
  125. { 0, AD5755_SLEW_RATE_0_5 },
  126. };
  127. static const int ad5755_slew_step_table[][2] = {
  128. { 256, AD5755_SLEW_STEP_SIZE_256 },
  129. { 128, AD5755_SLEW_STEP_SIZE_128 },
  130. { 64, AD5755_SLEW_STEP_SIZE_64 },
  131. { 32, AD5755_SLEW_STEP_SIZE_32 },
  132. { 16, AD5755_SLEW_STEP_SIZE_16 },
  133. { 4, AD5755_SLEW_STEP_SIZE_4 },
  134. { 2, AD5755_SLEW_STEP_SIZE_2 },
  135. { 1, AD5755_SLEW_STEP_SIZE_1 },
  136. };
  137. #endif
  138. static int ad5755_write_unlocked(struct iio_dev *indio_dev,
  139. unsigned int reg, unsigned int val)
  140. {
  141. struct ad5755_state *st = iio_priv(indio_dev);
  142. st->data[0].d32 = cpu_to_be32((reg << 16) | val);
  143. return spi_write(st->spi, &st->data[0].d8[1], 3);
  144. }
  145. static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev,
  146. unsigned int channel, unsigned int reg, unsigned int val)
  147. {
  148. return ad5755_write_unlocked(indio_dev,
  149. AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val);
  150. }
  151. static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg,
  152. unsigned int val)
  153. {
  154. struct ad5755_state *st = iio_priv(indio_dev);
  155. int ret;
  156. mutex_lock(&st->lock);
  157. ret = ad5755_write_unlocked(indio_dev, reg, val);
  158. mutex_unlock(&st->lock);
  159. return ret;
  160. }
  161. static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel,
  162. unsigned int reg, unsigned int val)
  163. {
  164. struct ad5755_state *st = iio_priv(indio_dev);
  165. int ret;
  166. mutex_lock(&st->lock);
  167. ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val);
  168. mutex_unlock(&st->lock);
  169. return ret;
  170. }
  171. static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr)
  172. {
  173. struct ad5755_state *st = iio_priv(indio_dev);
  174. int ret;
  175. struct spi_transfer t[] = {
  176. {
  177. .tx_buf = &st->data[0].d8[1],
  178. .len = 3,
  179. .cs_change = 1,
  180. }, {
  181. .tx_buf = &st->data[1].d8[1],
  182. .rx_buf = &st->data[1].d8[1],
  183. .len = 3,
  184. },
  185. };
  186. mutex_lock(&st->lock);
  187. st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16));
  188. st->data[1].d32 = cpu_to_be32(AD5755_NOOP);
  189. ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
  190. if (ret >= 0)
  191. ret = be32_to_cpu(st->data[1].d32) & 0xffff;
  192. mutex_unlock(&st->lock);
  193. return ret;
  194. }
  195. static int ad5755_update_dac_ctrl(struct iio_dev *indio_dev,
  196. unsigned int channel, unsigned int set, unsigned int clr)
  197. {
  198. struct ad5755_state *st = iio_priv(indio_dev);
  199. int ret;
  200. st->ctrl[channel] |= set;
  201. st->ctrl[channel] &= ~clr;
  202. ret = ad5755_write_ctrl_unlocked(indio_dev, channel,
  203. AD5755_CTRL_REG_DAC, st->ctrl[channel]);
  204. return ret;
  205. }
  206. static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev,
  207. unsigned int channel, bool pwr_down)
  208. {
  209. struct ad5755_state *st = iio_priv(indio_dev);
  210. unsigned int mask = BIT(channel);
  211. mutex_lock(&st->lock);
  212. if ((bool)(st->pwr_down & mask) == pwr_down)
  213. goto out_unlock;
  214. if (!pwr_down) {
  215. st->pwr_down &= ~mask;
  216. ad5755_update_dac_ctrl(indio_dev, channel,
  217. AD5755_DAC_INT_EN | AD5755_DAC_DC_DC_EN, 0);
  218. udelay(200);
  219. ad5755_update_dac_ctrl(indio_dev, channel,
  220. AD5755_DAC_OUT_EN, 0);
  221. } else {
  222. st->pwr_down |= mask;
  223. ad5755_update_dac_ctrl(indio_dev, channel,
  224. 0, AD5755_DAC_INT_EN | AD5755_DAC_OUT_EN |
  225. AD5755_DAC_DC_DC_EN);
  226. }
  227. out_unlock:
  228. mutex_unlock(&st->lock);
  229. return 0;
  230. }
  231. static const int ad5755_min_max_table[][2] = {
  232. [AD5755_MODE_VOLTAGE_0V_5V] = { 0, 5000 },
  233. [AD5755_MODE_VOLTAGE_0V_10V] = { 0, 10000 },
  234. [AD5755_MODE_VOLTAGE_PLUSMINUS_5V] = { -5000, 5000 },
  235. [AD5755_MODE_VOLTAGE_PLUSMINUS_10V] = { -10000, 10000 },
  236. [AD5755_MODE_CURRENT_4mA_20mA] = { 4, 20 },
  237. [AD5755_MODE_CURRENT_0mA_20mA] = { 0, 20 },
  238. [AD5755_MODE_CURRENT_0mA_24mA] = { 0, 24 },
  239. };
  240. static void ad5755_get_min_max(struct ad5755_state *st,
  241. struct iio_chan_spec const *chan, int *min, int *max)
  242. {
  243. enum ad5755_mode mode = st->ctrl[chan->channel] & 7;
  244. *min = ad5755_min_max_table[mode][0];
  245. *max = ad5755_min_max_table[mode][1];
  246. }
  247. static inline int ad5755_get_offset(struct ad5755_state *st,
  248. struct iio_chan_spec const *chan)
  249. {
  250. int min, max;
  251. ad5755_get_min_max(st, chan, &min, &max);
  252. return (min * (1 << chan->scan_type.realbits)) / (max - min);
  253. }
  254. static int ad5755_chan_reg_info(struct ad5755_state *st,
  255. struct iio_chan_spec const *chan, long info, bool write,
  256. unsigned int *reg, unsigned int *shift, unsigned int *offset)
  257. {
  258. switch (info) {
  259. case IIO_CHAN_INFO_RAW:
  260. if (write)
  261. *reg = AD5755_WRITE_REG_DATA(chan->address);
  262. else
  263. *reg = AD5755_READ_REG_DATA(chan->address);
  264. *shift = chan->scan_type.shift;
  265. *offset = 0;
  266. break;
  267. case IIO_CHAN_INFO_CALIBBIAS:
  268. if (write)
  269. *reg = AD5755_WRITE_REG_OFFSET(chan->address);
  270. else
  271. *reg = AD5755_READ_REG_OFFSET(chan->address);
  272. *shift = st->chip_info->calib_shift;
  273. *offset = 32768;
  274. break;
  275. case IIO_CHAN_INFO_CALIBSCALE:
  276. if (write)
  277. *reg = AD5755_WRITE_REG_GAIN(chan->address);
  278. else
  279. *reg = AD5755_READ_REG_GAIN(chan->address);
  280. *shift = st->chip_info->calib_shift;
  281. *offset = 0;
  282. break;
  283. default:
  284. return -EINVAL;
  285. }
  286. return 0;
  287. }
  288. static int ad5755_read_raw(struct iio_dev *indio_dev,
  289. const struct iio_chan_spec *chan, int *val, int *val2, long info)
  290. {
  291. struct ad5755_state *st = iio_priv(indio_dev);
  292. unsigned int reg, shift, offset;
  293. int min, max;
  294. int ret;
  295. switch (info) {
  296. case IIO_CHAN_INFO_SCALE:
  297. ad5755_get_min_max(st, chan, &min, &max);
  298. *val = max - min;
  299. *val2 = chan->scan_type.realbits;
  300. return IIO_VAL_FRACTIONAL_LOG2;
  301. case IIO_CHAN_INFO_OFFSET:
  302. *val = ad5755_get_offset(st, chan);
  303. return IIO_VAL_INT;
  304. default:
  305. ret = ad5755_chan_reg_info(st, chan, info, false,
  306. &reg, &shift, &offset);
  307. if (ret)
  308. return ret;
  309. ret = ad5755_read(indio_dev, reg);
  310. if (ret < 0)
  311. return ret;
  312. *val = (ret - offset) >> shift;
  313. return IIO_VAL_INT;
  314. }
  315. return -EINVAL;
  316. }
  317. static int ad5755_write_raw(struct iio_dev *indio_dev,
  318. const struct iio_chan_spec *chan, int val, int val2, long info)
  319. {
  320. struct ad5755_state *st = iio_priv(indio_dev);
  321. unsigned int shift, reg, offset;
  322. int ret;
  323. ret = ad5755_chan_reg_info(st, chan, info, true,
  324. &reg, &shift, &offset);
  325. if (ret)
  326. return ret;
  327. val <<= shift;
  328. val += offset;
  329. if (val < 0 || val > 0xffff)
  330. return -EINVAL;
  331. return ad5755_write(indio_dev, reg, val);
  332. }
  333. static ssize_t ad5755_read_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
  334. const struct iio_chan_spec *chan, char *buf)
  335. {
  336. struct ad5755_state *st = iio_priv(indio_dev);
  337. return sprintf(buf, "%d\n",
  338. (bool)(st->pwr_down & (1 << chan->channel)));
  339. }
  340. static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
  341. struct iio_chan_spec const *chan, const char *buf, size_t len)
  342. {
  343. bool pwr_down;
  344. int ret;
  345. ret = strtobool(buf, &pwr_down);
  346. if (ret)
  347. return ret;
  348. ret = ad5755_set_channel_pwr_down(indio_dev, chan->channel, pwr_down);
  349. return ret ? ret : len;
  350. }
  351. static const struct iio_info ad5755_info = {
  352. .read_raw = ad5755_read_raw,
  353. .write_raw = ad5755_write_raw,
  354. };
  355. static const struct iio_chan_spec_ext_info ad5755_ext_info[] = {
  356. {
  357. .name = "powerdown",
  358. .read = ad5755_read_powerdown,
  359. .write = ad5755_write_powerdown,
  360. .shared = IIO_SEPARATE,
  361. },
  362. { },
  363. };
  364. #define AD5755_CHANNEL(_bits) { \
  365. .indexed = 1, \
  366. .output = 1, \
  367. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  368. BIT(IIO_CHAN_INFO_SCALE) | \
  369. BIT(IIO_CHAN_INFO_OFFSET) | \
  370. BIT(IIO_CHAN_INFO_CALIBSCALE) | \
  371. BIT(IIO_CHAN_INFO_CALIBBIAS), \
  372. .scan_type = { \
  373. .sign = 'u', \
  374. .realbits = (_bits), \
  375. .storagebits = 16, \
  376. .shift = 16 - (_bits), \
  377. }, \
  378. .ext_info = ad5755_ext_info, \
  379. }
  380. static const struct ad5755_chip_info ad5755_chip_info_tbl[] = {
  381. [ID_AD5735] = {
  382. .channel_template = AD5755_CHANNEL(14),
  383. .has_voltage_out = true,
  384. .calib_shift = 4,
  385. },
  386. [ID_AD5737] = {
  387. .channel_template = AD5755_CHANNEL(14),
  388. .has_voltage_out = false,
  389. .calib_shift = 4,
  390. },
  391. [ID_AD5755] = {
  392. .channel_template = AD5755_CHANNEL(16),
  393. .has_voltage_out = true,
  394. .calib_shift = 0,
  395. },
  396. [ID_AD5757] = {
  397. .channel_template = AD5755_CHANNEL(16),
  398. .has_voltage_out = false,
  399. .calib_shift = 0,
  400. },
  401. };
  402. static bool ad5755_is_valid_mode(struct ad5755_state *st, enum ad5755_mode mode)
  403. {
  404. switch (mode) {
  405. case AD5755_MODE_VOLTAGE_0V_5V:
  406. case AD5755_MODE_VOLTAGE_0V_10V:
  407. case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
  408. case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
  409. return st->chip_info->has_voltage_out;
  410. case AD5755_MODE_CURRENT_4mA_20mA:
  411. case AD5755_MODE_CURRENT_0mA_20mA:
  412. case AD5755_MODE_CURRENT_0mA_24mA:
  413. return true;
  414. default:
  415. return false;
  416. }
  417. }
  418. static int ad5755_setup_pdata(struct iio_dev *indio_dev,
  419. const struct ad5755_platform_data *pdata)
  420. {
  421. struct ad5755_state *st = iio_priv(indio_dev);
  422. unsigned int val;
  423. unsigned int i;
  424. int ret;
  425. if (pdata->dc_dc_phase > AD5755_DC_DC_PHASE_90_DEGREE ||
  426. pdata->dc_dc_freq > AD5755_DC_DC_FREQ_650kHZ ||
  427. pdata->dc_dc_maxv > AD5755_DC_DC_MAXV_29V5)
  428. return -EINVAL;
  429. val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV;
  430. val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT;
  431. val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT;
  432. if (pdata->ext_dc_dc_compenstation_resistor)
  433. val |= AD5755_EXT_DC_DC_COMP_RES;
  434. ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val);
  435. if (ret < 0)
  436. return ret;
  437. for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
  438. val = pdata->dac[i].slew.step_size <<
  439. AD5755_SLEW_STEP_SIZE_SHIFT;
  440. val |= pdata->dac[i].slew.rate <<
  441. AD5755_SLEW_RATE_SHIFT;
  442. if (pdata->dac[i].slew.enable)
  443. val |= AD5755_SLEW_ENABLE;
  444. ret = ad5755_write_ctrl(indio_dev, i,
  445. AD5755_CTRL_REG_SLEW, val);
  446. if (ret < 0)
  447. return ret;
  448. }
  449. for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
  450. if (!ad5755_is_valid_mode(st, pdata->dac[i].mode))
  451. return -EINVAL;
  452. val = 0;
  453. if (!pdata->dac[i].ext_current_sense_resistor)
  454. val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR;
  455. if (pdata->dac[i].enable_voltage_overrange)
  456. val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN;
  457. val |= pdata->dac[i].mode;
  458. ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0);
  459. if (ret < 0)
  460. return ret;
  461. }
  462. return 0;
  463. }
  464. static bool ad5755_is_voltage_mode(enum ad5755_mode mode)
  465. {
  466. switch (mode) {
  467. case AD5755_MODE_VOLTAGE_0V_5V:
  468. case AD5755_MODE_VOLTAGE_0V_10V:
  469. case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
  470. case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
  471. return true;
  472. default:
  473. return false;
  474. }
  475. }
  476. static int ad5755_init_channels(struct iio_dev *indio_dev,
  477. const struct ad5755_platform_data *pdata)
  478. {
  479. struct ad5755_state *st = iio_priv(indio_dev);
  480. struct iio_chan_spec *channels = st->channels;
  481. unsigned int i;
  482. for (i = 0; i < AD5755_NUM_CHANNELS; ++i) {
  483. channels[i] = st->chip_info->channel_template;
  484. channels[i].channel = i;
  485. channels[i].address = i;
  486. if (pdata && ad5755_is_voltage_mode(pdata->dac[i].mode))
  487. channels[i].type = IIO_VOLTAGE;
  488. else
  489. channels[i].type = IIO_CURRENT;
  490. }
  491. indio_dev->channels = channels;
  492. return 0;
  493. }
  494. #define AD5755_DEFAULT_DAC_PDATA { \
  495. .mode = AD5755_MODE_CURRENT_4mA_20mA, \
  496. .ext_current_sense_resistor = true, \
  497. .enable_voltage_overrange = false, \
  498. .slew = { \
  499. .enable = false, \
  500. .rate = AD5755_SLEW_RATE_64k, \
  501. .step_size = AD5755_SLEW_STEP_SIZE_1, \
  502. }, \
  503. }
  504. static const struct ad5755_platform_data ad5755_default_pdata = {
  505. .ext_dc_dc_compenstation_resistor = false,
  506. .dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE,
  507. .dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ,
  508. .dc_dc_maxv = AD5755_DC_DC_MAXV_23V,
  509. .dac = {
  510. [0] = AD5755_DEFAULT_DAC_PDATA,
  511. [1] = AD5755_DEFAULT_DAC_PDATA,
  512. [2] = AD5755_DEFAULT_DAC_PDATA,
  513. [3] = AD5755_DEFAULT_DAC_PDATA,
  514. },
  515. };
  516. #ifdef CONFIG_OF
  517. static struct ad5755_platform_data *ad5755_parse_dt(struct device *dev)
  518. {
  519. struct device_node *np = dev->of_node;
  520. struct device_node *pp;
  521. struct ad5755_platform_data *pdata;
  522. unsigned int tmp;
  523. unsigned int tmparray[3];
  524. int devnr, i;
  525. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  526. if (!pdata)
  527. return NULL;
  528. pdata->ext_dc_dc_compenstation_resistor =
  529. of_property_read_bool(np, "adi,ext-dc-dc-compenstation-resistor");
  530. if (!of_property_read_u32(np, "adi,dc-dc-phase", &tmp))
  531. pdata->dc_dc_phase = tmp;
  532. else
  533. pdata->dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE;
  534. pdata->dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ;
  535. if (!of_property_read_u32(np, "adi,dc-dc-freq-hz", &tmp)) {
  536. for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_freq_table); i++) {
  537. if (tmp == ad5755_dcdc_freq_table[i][0]) {
  538. pdata->dc_dc_freq = ad5755_dcdc_freq_table[i][1];
  539. break;
  540. }
  541. }
  542. if (i == ARRAY_SIZE(ad5755_dcdc_freq_table))
  543. dev_err(dev,
  544. "adi,dc-dc-freq out of range selecting 410kHz\n");
  545. }
  546. pdata->dc_dc_maxv = AD5755_DC_DC_MAXV_23V;
  547. if (!of_property_read_u32(np, "adi,dc-dc-max-microvolt", &tmp)) {
  548. for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_maxv_table); i++) {
  549. if (tmp == ad5755_dcdc_maxv_table[i][0]) {
  550. pdata->dc_dc_maxv = ad5755_dcdc_maxv_table[i][1];
  551. break;
  552. }
  553. }
  554. if (i == ARRAY_SIZE(ad5755_dcdc_maxv_table))
  555. dev_err(dev,
  556. "adi,dc-dc-maxv out of range selecting 23V\n");
  557. }
  558. devnr = 0;
  559. for_each_child_of_node(np, pp) {
  560. if (devnr >= AD5755_NUM_CHANNELS) {
  561. dev_err(dev,
  562. "There are too many channels defined in DT\n");
  563. goto error_out;
  564. }
  565. if (!of_property_read_u32(pp, "adi,mode", &tmp))
  566. pdata->dac[devnr].mode = tmp;
  567. else
  568. pdata->dac[devnr].mode = AD5755_MODE_CURRENT_4mA_20mA;
  569. pdata->dac[devnr].ext_current_sense_resistor =
  570. of_property_read_bool(pp, "adi,ext-current-sense-resistor");
  571. pdata->dac[devnr].enable_voltage_overrange =
  572. of_property_read_bool(pp, "adi,enable-voltage-overrange");
  573. if (!of_property_read_u32_array(pp, "adi,slew", tmparray, 3)) {
  574. pdata->dac[devnr].slew.enable = tmparray[0];
  575. pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
  576. for (i = 0; i < ARRAY_SIZE(ad5755_slew_rate_table); i++) {
  577. if (tmparray[1] == ad5755_slew_rate_table[i][0]) {
  578. pdata->dac[devnr].slew.rate =
  579. ad5755_slew_rate_table[i][1];
  580. break;
  581. }
  582. }
  583. if (i == ARRAY_SIZE(ad5755_slew_rate_table))
  584. dev_err(dev,
  585. "channel %d slew rate out of range selecting 64kHz\n",
  586. devnr);
  587. pdata->dac[devnr].slew.step_size = AD5755_SLEW_STEP_SIZE_1;
  588. for (i = 0; i < ARRAY_SIZE(ad5755_slew_step_table); i++) {
  589. if (tmparray[2] == ad5755_slew_step_table[i][0]) {
  590. pdata->dac[devnr].slew.step_size =
  591. ad5755_slew_step_table[i][1];
  592. break;
  593. }
  594. }
  595. if (i == ARRAY_SIZE(ad5755_slew_step_table))
  596. dev_err(dev,
  597. "channel %d slew step size out of range selecting 1 LSB\n",
  598. devnr);
  599. } else {
  600. pdata->dac[devnr].slew.enable = false;
  601. pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
  602. pdata->dac[devnr].slew.step_size =
  603. AD5755_SLEW_STEP_SIZE_1;
  604. }
  605. devnr++;
  606. }
  607. return pdata;
  608. error_out:
  609. devm_kfree(dev, pdata);
  610. return NULL;
  611. }
  612. #else
  613. static
  614. struct ad5755_platform_data *ad5755_parse_dt(struct device *dev)
  615. {
  616. return NULL;
  617. }
  618. #endif
  619. static int ad5755_probe(struct spi_device *spi)
  620. {
  621. enum ad5755_type type = spi_get_device_id(spi)->driver_data;
  622. const struct ad5755_platform_data *pdata = dev_get_platdata(&spi->dev);
  623. struct iio_dev *indio_dev;
  624. struct ad5755_state *st;
  625. int ret;
  626. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  627. if (indio_dev == NULL) {
  628. dev_err(&spi->dev, "Failed to allocate iio device\n");
  629. return -ENOMEM;
  630. }
  631. st = iio_priv(indio_dev);
  632. spi_set_drvdata(spi, indio_dev);
  633. st->chip_info = &ad5755_chip_info_tbl[type];
  634. st->spi = spi;
  635. st->pwr_down = 0xf;
  636. indio_dev->name = spi_get_device_id(spi)->name;
  637. indio_dev->info = &ad5755_info;
  638. indio_dev->modes = INDIO_DIRECT_MODE;
  639. indio_dev->num_channels = AD5755_NUM_CHANNELS;
  640. mutex_init(&st->lock);
  641. if (spi->dev.of_node)
  642. pdata = ad5755_parse_dt(&spi->dev);
  643. else
  644. pdata = spi->dev.platform_data;
  645. if (!pdata) {
  646. dev_warn(&spi->dev, "no platform data? using default\n");
  647. pdata = &ad5755_default_pdata;
  648. }
  649. ret = ad5755_init_channels(indio_dev, pdata);
  650. if (ret)
  651. return ret;
  652. ret = ad5755_setup_pdata(indio_dev, pdata);
  653. if (ret)
  654. return ret;
  655. return devm_iio_device_register(&spi->dev, indio_dev);
  656. }
  657. static const struct spi_device_id ad5755_id[] = {
  658. { "ad5755", ID_AD5755 },
  659. { "ad5755-1", ID_AD5755 },
  660. { "ad5757", ID_AD5757 },
  661. { "ad5735", ID_AD5735 },
  662. { "ad5737", ID_AD5737 },
  663. {}
  664. };
  665. MODULE_DEVICE_TABLE(spi, ad5755_id);
  666. static const struct of_device_id ad5755_of_match[] = {
  667. { .compatible = "adi,ad5755" },
  668. { .compatible = "adi,ad5755-1" },
  669. { .compatible = "adi,ad5757" },
  670. { .compatible = "adi,ad5735" },
  671. { .compatible = "adi,ad5737" },
  672. { }
  673. };
  674. MODULE_DEVICE_TABLE(of, ad5755_of_match);
  675. static struct spi_driver ad5755_driver = {
  676. .driver = {
  677. .name = "ad5755",
  678. },
  679. .probe = ad5755_probe,
  680. .id_table = ad5755_id,
  681. };
  682. module_spi_driver(ad5755_driver);
  683. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  684. MODULE_DESCRIPTION("Analog Devices AD5755/55-1/57/35/37 DAC");
  685. MODULE_LICENSE("GPL v2");