ad5449.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AD5415, AD5426, AD5429, AD5432, AD5439, AD5443, AD5449 Digital to Analog
  4. * Converter driver.
  5. *
  6. * Copyright 2012 Analog Devices Inc.
  7. * Author: Lars-Peter Clausen <lars@metafoo.de>
  8. */
  9. #include <linux/device.h>
  10. #include <linux/err.h>
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/slab.h>
  15. #include <linux/sysfs.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <asm/unaligned.h>
  18. #include <linux/iio/iio.h>
  19. #include <linux/iio/sysfs.h>
  20. #include <linux/platform_data/ad5449.h>
  21. #define AD5449_MAX_CHANNELS 2
  22. #define AD5449_MAX_VREFS 2
  23. #define AD5449_CMD_NOOP 0x0
  24. #define AD5449_CMD_LOAD_AND_UPDATE(x) (0x1 + (x) * 3)
  25. #define AD5449_CMD_READ(x) (0x2 + (x) * 3)
  26. #define AD5449_CMD_LOAD(x) (0x3 + (x) * 3)
  27. #define AD5449_CMD_CTRL 13
  28. #define AD5449_CTRL_SDO_OFFSET 10
  29. #define AD5449_CTRL_DAISY_CHAIN BIT(9)
  30. #define AD5449_CTRL_HCLR_TO_MIDSCALE BIT(8)
  31. #define AD5449_CTRL_SAMPLE_RISING BIT(7)
  32. /**
  33. * struct ad5449_chip_info - chip specific information
  34. * @channels: Channel specification
  35. * @num_channels: Number of channels
  36. * @has_ctrl: Chip has a control register
  37. */
  38. struct ad5449_chip_info {
  39. const struct iio_chan_spec *channels;
  40. unsigned int num_channels;
  41. bool has_ctrl;
  42. };
  43. /**
  44. * struct ad5449 - driver instance specific data
  45. * @spi: the SPI device for this driver instance
  46. * @chip_info: chip model specific constants, available modes etc
  47. * @vref_reg: vref supply regulators
  48. * @has_sdo: whether the SDO line is connected
  49. * @dac_cache: Cache for the DAC values
  50. * @data: spi transfer buffers
  51. * @lock: lock to protect the data buffer during SPI ops
  52. */
  53. struct ad5449 {
  54. struct spi_device *spi;
  55. const struct ad5449_chip_info *chip_info;
  56. struct regulator_bulk_data vref_reg[AD5449_MAX_VREFS];
  57. struct mutex lock;
  58. bool has_sdo;
  59. uint16_t dac_cache[AD5449_MAX_CHANNELS];
  60. /*
  61. * DMA (thus cache coherency maintenance) requires the
  62. * transfer buffers to live in their own cache lines.
  63. */
  64. __be16 data[2] ____cacheline_aligned;
  65. };
  66. enum ad5449_type {
  67. ID_AD5426,
  68. ID_AD5429,
  69. ID_AD5432,
  70. ID_AD5439,
  71. ID_AD5443,
  72. ID_AD5449,
  73. };
  74. static int ad5449_write(struct iio_dev *indio_dev, unsigned int addr,
  75. unsigned int val)
  76. {
  77. struct ad5449 *st = iio_priv(indio_dev);
  78. int ret;
  79. mutex_lock(&st->lock);
  80. st->data[0] = cpu_to_be16((addr << 12) | val);
  81. ret = spi_write(st->spi, st->data, 2);
  82. mutex_unlock(&st->lock);
  83. return ret;
  84. }
  85. static int ad5449_read(struct iio_dev *indio_dev, unsigned int addr,
  86. unsigned int *val)
  87. {
  88. struct ad5449 *st = iio_priv(indio_dev);
  89. int ret;
  90. struct spi_transfer t[] = {
  91. {
  92. .tx_buf = &st->data[0],
  93. .len = 2,
  94. .cs_change = 1,
  95. }, {
  96. .tx_buf = &st->data[1],
  97. .rx_buf = &st->data[1],
  98. .len = 2,
  99. },
  100. };
  101. mutex_lock(&st->lock);
  102. st->data[0] = cpu_to_be16(addr << 12);
  103. st->data[1] = cpu_to_be16(AD5449_CMD_NOOP);
  104. ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
  105. if (ret < 0)
  106. goto out_unlock;
  107. *val = be16_to_cpu(st->data[1]);
  108. out_unlock:
  109. mutex_unlock(&st->lock);
  110. return ret;
  111. }
  112. static int ad5449_read_raw(struct iio_dev *indio_dev,
  113. struct iio_chan_spec const *chan, int *val, int *val2, long info)
  114. {
  115. struct ad5449 *st = iio_priv(indio_dev);
  116. struct regulator_bulk_data *reg;
  117. int scale_uv;
  118. int ret;
  119. switch (info) {
  120. case IIO_CHAN_INFO_RAW:
  121. if (st->has_sdo) {
  122. ret = ad5449_read(indio_dev,
  123. AD5449_CMD_READ(chan->address), val);
  124. if (ret)
  125. return ret;
  126. *val &= 0xfff;
  127. } else {
  128. *val = st->dac_cache[chan->address];
  129. }
  130. return IIO_VAL_INT;
  131. case IIO_CHAN_INFO_SCALE:
  132. reg = &st->vref_reg[chan->channel];
  133. scale_uv = regulator_get_voltage(reg->consumer);
  134. if (scale_uv < 0)
  135. return scale_uv;
  136. *val = scale_uv / 1000;
  137. *val2 = chan->scan_type.realbits;
  138. return IIO_VAL_FRACTIONAL_LOG2;
  139. default:
  140. break;
  141. }
  142. return -EINVAL;
  143. }
  144. static int ad5449_write_raw(struct iio_dev *indio_dev,
  145. struct iio_chan_spec const *chan, int val, int val2, long info)
  146. {
  147. struct ad5449 *st = iio_priv(indio_dev);
  148. int ret;
  149. switch (info) {
  150. case IIO_CHAN_INFO_RAW:
  151. if (val < 0 || val >= (1 << chan->scan_type.realbits))
  152. return -EINVAL;
  153. ret = ad5449_write(indio_dev,
  154. AD5449_CMD_LOAD_AND_UPDATE(chan->address),
  155. val << chan->scan_type.shift);
  156. if (ret == 0)
  157. st->dac_cache[chan->address] = val;
  158. break;
  159. default:
  160. ret = -EINVAL;
  161. }
  162. return ret;
  163. }
  164. static const struct iio_info ad5449_info = {
  165. .read_raw = ad5449_read_raw,
  166. .write_raw = ad5449_write_raw,
  167. };
  168. #define AD5449_CHANNEL(chan, bits) { \
  169. .type = IIO_VOLTAGE, \
  170. .indexed = 1, \
  171. .output = 1, \
  172. .channel = (chan), \
  173. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  174. BIT(IIO_CHAN_INFO_SCALE), \
  175. .address = (chan), \
  176. .scan_type = { \
  177. .sign = 'u', \
  178. .realbits = (bits), \
  179. .storagebits = 16, \
  180. .shift = 12 - (bits), \
  181. }, \
  182. }
  183. #define DECLARE_AD5449_CHANNELS(name, bits) \
  184. const struct iio_chan_spec name[] = { \
  185. AD5449_CHANNEL(0, bits), \
  186. AD5449_CHANNEL(1, bits), \
  187. }
  188. static DECLARE_AD5449_CHANNELS(ad5429_channels, 8);
  189. static DECLARE_AD5449_CHANNELS(ad5439_channels, 10);
  190. static DECLARE_AD5449_CHANNELS(ad5449_channels, 12);
  191. static const struct ad5449_chip_info ad5449_chip_info[] = {
  192. [ID_AD5426] = {
  193. .channels = ad5429_channels,
  194. .num_channels = 1,
  195. .has_ctrl = false,
  196. },
  197. [ID_AD5429] = {
  198. .channels = ad5429_channels,
  199. .num_channels = 2,
  200. .has_ctrl = true,
  201. },
  202. [ID_AD5432] = {
  203. .channels = ad5439_channels,
  204. .num_channels = 1,
  205. .has_ctrl = false,
  206. },
  207. [ID_AD5439] = {
  208. .channels = ad5439_channels,
  209. .num_channels = 2,
  210. .has_ctrl = true,
  211. },
  212. [ID_AD5443] = {
  213. .channels = ad5449_channels,
  214. .num_channels = 1,
  215. .has_ctrl = false,
  216. },
  217. [ID_AD5449] = {
  218. .channels = ad5449_channels,
  219. .num_channels = 2,
  220. .has_ctrl = true,
  221. },
  222. };
  223. static const char *ad5449_vref_name(struct ad5449 *st, int n)
  224. {
  225. if (st->chip_info->num_channels == 1)
  226. return "VREF";
  227. if (n == 0)
  228. return "VREFA";
  229. else
  230. return "VREFB";
  231. }
  232. static int ad5449_spi_probe(struct spi_device *spi)
  233. {
  234. struct ad5449_platform_data *pdata = spi->dev.platform_data;
  235. const struct spi_device_id *id = spi_get_device_id(spi);
  236. struct iio_dev *indio_dev;
  237. struct ad5449 *st;
  238. unsigned int i;
  239. int ret;
  240. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  241. if (indio_dev == NULL)
  242. return -ENOMEM;
  243. st = iio_priv(indio_dev);
  244. spi_set_drvdata(spi, indio_dev);
  245. st->chip_info = &ad5449_chip_info[id->driver_data];
  246. st->spi = spi;
  247. for (i = 0; i < st->chip_info->num_channels; ++i)
  248. st->vref_reg[i].supply = ad5449_vref_name(st, i);
  249. ret = devm_regulator_bulk_get(&spi->dev, st->chip_info->num_channels,
  250. st->vref_reg);
  251. if (ret)
  252. return ret;
  253. ret = regulator_bulk_enable(st->chip_info->num_channels, st->vref_reg);
  254. if (ret)
  255. return ret;
  256. indio_dev->name = id->name;
  257. indio_dev->info = &ad5449_info;
  258. indio_dev->modes = INDIO_DIRECT_MODE;
  259. indio_dev->channels = st->chip_info->channels;
  260. indio_dev->num_channels = st->chip_info->num_channels;
  261. mutex_init(&st->lock);
  262. if (st->chip_info->has_ctrl) {
  263. unsigned int ctrl = 0x00;
  264. if (pdata) {
  265. if (pdata->hardware_clear_to_midscale)
  266. ctrl |= AD5449_CTRL_HCLR_TO_MIDSCALE;
  267. ctrl |= pdata->sdo_mode << AD5449_CTRL_SDO_OFFSET;
  268. st->has_sdo = pdata->sdo_mode != AD5449_SDO_DISABLED;
  269. } else {
  270. st->has_sdo = true;
  271. }
  272. ad5449_write(indio_dev, AD5449_CMD_CTRL, ctrl);
  273. }
  274. ret = iio_device_register(indio_dev);
  275. if (ret)
  276. goto error_disable_reg;
  277. return 0;
  278. error_disable_reg:
  279. regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
  280. return ret;
  281. }
  282. static int ad5449_spi_remove(struct spi_device *spi)
  283. {
  284. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  285. struct ad5449 *st = iio_priv(indio_dev);
  286. iio_device_unregister(indio_dev);
  287. regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
  288. return 0;
  289. }
  290. static const struct spi_device_id ad5449_spi_ids[] = {
  291. { "ad5415", ID_AD5449 },
  292. { "ad5426", ID_AD5426 },
  293. { "ad5429", ID_AD5429 },
  294. { "ad5432", ID_AD5432 },
  295. { "ad5439", ID_AD5439 },
  296. { "ad5443", ID_AD5443 },
  297. { "ad5449", ID_AD5449 },
  298. {}
  299. };
  300. MODULE_DEVICE_TABLE(spi, ad5449_spi_ids);
  301. static struct spi_driver ad5449_spi_driver = {
  302. .driver = {
  303. .name = "ad5449",
  304. },
  305. .probe = ad5449_spi_probe,
  306. .remove = ad5449_spi_remove,
  307. .id_table = ad5449_spi_ids,
  308. };
  309. module_spi_driver(ad5449_spi_driver);
  310. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  311. MODULE_DESCRIPTION("Analog Devices AD5449 and similar DACs");
  312. MODULE_LICENSE("GPL v2");