ad5421.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AD5421 Digital to analog converters driver
  4. *
  5. * Copyright 2011 Analog Devices Inc.
  6. */
  7. #include <linux/device.h>
  8. #include <linux/delay.h>
  9. #include <linux/err.h>
  10. #include <linux/module.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/kernel.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/slab.h>
  15. #include <linux/sysfs.h>
  16. #include <linux/iio/iio.h>
  17. #include <linux/iio/sysfs.h>
  18. #include <linux/iio/events.h>
  19. #include <linux/iio/dac/ad5421.h>
  20. #define AD5421_REG_DAC_DATA 0x1
  21. #define AD5421_REG_CTRL 0x2
  22. #define AD5421_REG_OFFSET 0x3
  23. #define AD5421_REG_GAIN 0x4
  24. /* load dac and fault shared the same register number. Writing to it will cause
  25. * a dac load command, reading from it will return the fault status register */
  26. #define AD5421_REG_LOAD_DAC 0x5
  27. #define AD5421_REG_FAULT 0x5
  28. #define AD5421_REG_FORCE_ALARM_CURRENT 0x6
  29. #define AD5421_REG_RESET 0x7
  30. #define AD5421_REG_START_CONVERSION 0x8
  31. #define AD5421_REG_NOOP 0x9
  32. #define AD5421_CTRL_WATCHDOG_DISABLE BIT(12)
  33. #define AD5421_CTRL_AUTO_FAULT_READBACK BIT(11)
  34. #define AD5421_CTRL_MIN_CURRENT BIT(9)
  35. #define AD5421_CTRL_ADC_SOURCE_TEMP BIT(8)
  36. #define AD5421_CTRL_ADC_ENABLE BIT(7)
  37. #define AD5421_CTRL_PWR_DOWN_INT_VREF BIT(6)
  38. #define AD5421_FAULT_SPI BIT(15)
  39. #define AD5421_FAULT_PEC BIT(14)
  40. #define AD5421_FAULT_OVER_CURRENT BIT(13)
  41. #define AD5421_FAULT_UNDER_CURRENT BIT(12)
  42. #define AD5421_FAULT_TEMP_OVER_140 BIT(11)
  43. #define AD5421_FAULT_TEMP_OVER_100 BIT(10)
  44. #define AD5421_FAULT_UNDER_VOLTAGE_6V BIT(9)
  45. #define AD5421_FAULT_UNDER_VOLTAGE_12V BIT(8)
  46. /* These bits will cause the fault pin to go high */
  47. #define AD5421_FAULT_TRIGGER_IRQ \
  48. (AD5421_FAULT_SPI | AD5421_FAULT_PEC | AD5421_FAULT_OVER_CURRENT | \
  49. AD5421_FAULT_UNDER_CURRENT | AD5421_FAULT_TEMP_OVER_140)
  50. /**
  51. * struct ad5421_state - driver instance specific data
  52. * @spi: spi_device
  53. * @ctrl: control register cache
  54. * @current_range: current range which the device is configured for
  55. * @data: spi transfer buffers
  56. * @fault_mask: software masking of events
  57. * @lock: lock to protect the data buffer during SPI ops
  58. */
  59. struct ad5421_state {
  60. struct spi_device *spi;
  61. unsigned int ctrl;
  62. enum ad5421_current_range current_range;
  63. unsigned int fault_mask;
  64. struct mutex lock;
  65. /*
  66. * DMA (thus cache coherency maintenance) requires the
  67. * transfer buffers to live in their own cache lines.
  68. */
  69. union {
  70. __be32 d32;
  71. u8 d8[4];
  72. } data[2] ____cacheline_aligned;
  73. };
  74. static const struct iio_event_spec ad5421_current_event[] = {
  75. {
  76. .type = IIO_EV_TYPE_THRESH,
  77. .dir = IIO_EV_DIR_RISING,
  78. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  79. BIT(IIO_EV_INFO_ENABLE),
  80. }, {
  81. .type = IIO_EV_TYPE_THRESH,
  82. .dir = IIO_EV_DIR_FALLING,
  83. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  84. BIT(IIO_EV_INFO_ENABLE),
  85. },
  86. };
  87. static const struct iio_event_spec ad5421_temp_event[] = {
  88. {
  89. .type = IIO_EV_TYPE_THRESH,
  90. .dir = IIO_EV_DIR_RISING,
  91. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  92. BIT(IIO_EV_INFO_ENABLE),
  93. },
  94. };
  95. static const struct iio_chan_spec ad5421_channels[] = {
  96. {
  97. .type = IIO_CURRENT,
  98. .indexed = 1,
  99. .output = 1,
  100. .channel = 0,
  101. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  102. BIT(IIO_CHAN_INFO_CALIBSCALE) |
  103. BIT(IIO_CHAN_INFO_CALIBBIAS),
  104. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
  105. BIT(IIO_CHAN_INFO_OFFSET),
  106. .scan_type = {
  107. .sign = 'u',
  108. .realbits = 16,
  109. .storagebits = 16,
  110. },
  111. .event_spec = ad5421_current_event,
  112. .num_event_specs = ARRAY_SIZE(ad5421_current_event),
  113. },
  114. {
  115. .type = IIO_TEMP,
  116. .channel = -1,
  117. .event_spec = ad5421_temp_event,
  118. .num_event_specs = ARRAY_SIZE(ad5421_temp_event),
  119. },
  120. };
  121. static int ad5421_write_unlocked(struct iio_dev *indio_dev,
  122. unsigned int reg, unsigned int val)
  123. {
  124. struct ad5421_state *st = iio_priv(indio_dev);
  125. st->data[0].d32 = cpu_to_be32((reg << 16) | val);
  126. return spi_write(st->spi, &st->data[0].d8[1], 3);
  127. }
  128. static int ad5421_write(struct iio_dev *indio_dev, unsigned int reg,
  129. unsigned int val)
  130. {
  131. struct ad5421_state *st = iio_priv(indio_dev);
  132. int ret;
  133. mutex_lock(&st->lock);
  134. ret = ad5421_write_unlocked(indio_dev, reg, val);
  135. mutex_unlock(&st->lock);
  136. return ret;
  137. }
  138. static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg)
  139. {
  140. struct ad5421_state *st = iio_priv(indio_dev);
  141. int ret;
  142. struct spi_transfer t[] = {
  143. {
  144. .tx_buf = &st->data[0].d8[1],
  145. .len = 3,
  146. .cs_change = 1,
  147. }, {
  148. .rx_buf = &st->data[1].d8[1],
  149. .len = 3,
  150. },
  151. };
  152. mutex_lock(&st->lock);
  153. st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
  154. ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
  155. if (ret >= 0)
  156. ret = be32_to_cpu(st->data[1].d32) & 0xffff;
  157. mutex_unlock(&st->lock);
  158. return ret;
  159. }
  160. static int ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
  161. unsigned int clr)
  162. {
  163. struct ad5421_state *st = iio_priv(indio_dev);
  164. unsigned int ret;
  165. mutex_lock(&st->lock);
  166. st->ctrl &= ~clr;
  167. st->ctrl |= set;
  168. ret = ad5421_write_unlocked(indio_dev, AD5421_REG_CTRL, st->ctrl);
  169. mutex_unlock(&st->lock);
  170. return ret;
  171. }
  172. static irqreturn_t ad5421_fault_handler(int irq, void *data)
  173. {
  174. struct iio_dev *indio_dev = data;
  175. struct ad5421_state *st = iio_priv(indio_dev);
  176. unsigned int fault;
  177. unsigned int old_fault = 0;
  178. unsigned int events;
  179. fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
  180. if (!fault)
  181. return IRQ_NONE;
  182. /* If we had a fault, this might mean that the DAC has lost its state
  183. * and has been reset. Make sure that the control register actually
  184. * contains what we expect it to contain. Otherwise the watchdog might
  185. * be enabled and we get watchdog timeout faults, which will render the
  186. * DAC unusable. */
  187. ad5421_update_ctrl(indio_dev, 0, 0);
  188. /* The fault pin stays high as long as a fault condition is present and
  189. * it is not possible to mask fault conditions. For certain fault
  190. * conditions for example like over-temperature it takes some time
  191. * until the fault condition disappears. If we would exit the interrupt
  192. * handler immediately after handling the event it would be entered
  193. * again instantly. Thus we fall back to polling in case we detect that
  194. * a interrupt condition is still present.
  195. */
  196. do {
  197. /* 0xffff is a invalid value for the register and will only be
  198. * read if there has been a communication error */
  199. if (fault == 0xffff)
  200. fault = 0;
  201. /* we are only interested in new events */
  202. events = (old_fault ^ fault) & fault;
  203. events &= st->fault_mask;
  204. if (events & AD5421_FAULT_OVER_CURRENT) {
  205. iio_push_event(indio_dev,
  206. IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
  207. 0,
  208. IIO_EV_TYPE_THRESH,
  209. IIO_EV_DIR_RISING),
  210. iio_get_time_ns(indio_dev));
  211. }
  212. if (events & AD5421_FAULT_UNDER_CURRENT) {
  213. iio_push_event(indio_dev,
  214. IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
  215. 0,
  216. IIO_EV_TYPE_THRESH,
  217. IIO_EV_DIR_FALLING),
  218. iio_get_time_ns(indio_dev));
  219. }
  220. if (events & AD5421_FAULT_TEMP_OVER_140) {
  221. iio_push_event(indio_dev,
  222. IIO_UNMOD_EVENT_CODE(IIO_TEMP,
  223. 0,
  224. IIO_EV_TYPE_MAG,
  225. IIO_EV_DIR_RISING),
  226. iio_get_time_ns(indio_dev));
  227. }
  228. old_fault = fault;
  229. fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
  230. /* still active? go to sleep for some time */
  231. if (fault & AD5421_FAULT_TRIGGER_IRQ)
  232. msleep(1000);
  233. } while (fault & AD5421_FAULT_TRIGGER_IRQ);
  234. return IRQ_HANDLED;
  235. }
  236. static void ad5421_get_current_min_max(struct ad5421_state *st,
  237. unsigned int *min, unsigned int *max)
  238. {
  239. /* The current range is configured using external pins, which are
  240. * usually hard-wired and not run-time switchable. */
  241. switch (st->current_range) {
  242. case AD5421_CURRENT_RANGE_4mA_20mA:
  243. *min = 4000;
  244. *max = 20000;
  245. break;
  246. case AD5421_CURRENT_RANGE_3mA8_21mA:
  247. *min = 3800;
  248. *max = 21000;
  249. break;
  250. case AD5421_CURRENT_RANGE_3mA2_24mA:
  251. *min = 3200;
  252. *max = 24000;
  253. break;
  254. default:
  255. *min = 0;
  256. *max = 1;
  257. break;
  258. }
  259. }
  260. static inline unsigned int ad5421_get_offset(struct ad5421_state *st)
  261. {
  262. unsigned int min, max;
  263. ad5421_get_current_min_max(st, &min, &max);
  264. return (min * (1 << 16)) / (max - min);
  265. }
  266. static int ad5421_read_raw(struct iio_dev *indio_dev,
  267. struct iio_chan_spec const *chan, int *val, int *val2, long m)
  268. {
  269. struct ad5421_state *st = iio_priv(indio_dev);
  270. unsigned int min, max;
  271. int ret;
  272. if (chan->type != IIO_CURRENT)
  273. return -EINVAL;
  274. switch (m) {
  275. case IIO_CHAN_INFO_RAW:
  276. ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
  277. if (ret < 0)
  278. return ret;
  279. *val = ret;
  280. return IIO_VAL_INT;
  281. case IIO_CHAN_INFO_SCALE:
  282. ad5421_get_current_min_max(st, &min, &max);
  283. *val = max - min;
  284. *val2 = (1 << 16) * 1000;
  285. return IIO_VAL_FRACTIONAL;
  286. case IIO_CHAN_INFO_OFFSET:
  287. *val = ad5421_get_offset(st);
  288. return IIO_VAL_INT;
  289. case IIO_CHAN_INFO_CALIBBIAS:
  290. ret = ad5421_read(indio_dev, AD5421_REG_OFFSET);
  291. if (ret < 0)
  292. return ret;
  293. *val = ret - 32768;
  294. return IIO_VAL_INT;
  295. case IIO_CHAN_INFO_CALIBSCALE:
  296. ret = ad5421_read(indio_dev, AD5421_REG_GAIN);
  297. if (ret < 0)
  298. return ret;
  299. *val = ret;
  300. return IIO_VAL_INT;
  301. }
  302. return -EINVAL;
  303. }
  304. static int ad5421_write_raw(struct iio_dev *indio_dev,
  305. struct iio_chan_spec const *chan, int val, int val2, long mask)
  306. {
  307. const unsigned int max_val = 1 << 16;
  308. switch (mask) {
  309. case IIO_CHAN_INFO_RAW:
  310. if (val >= max_val || val < 0)
  311. return -EINVAL;
  312. return ad5421_write(indio_dev, AD5421_REG_DAC_DATA, val);
  313. case IIO_CHAN_INFO_CALIBBIAS:
  314. val += 32768;
  315. if (val >= max_val || val < 0)
  316. return -EINVAL;
  317. return ad5421_write(indio_dev, AD5421_REG_OFFSET, val);
  318. case IIO_CHAN_INFO_CALIBSCALE:
  319. if (val >= max_val || val < 0)
  320. return -EINVAL;
  321. return ad5421_write(indio_dev, AD5421_REG_GAIN, val);
  322. default:
  323. break;
  324. }
  325. return -EINVAL;
  326. }
  327. static int ad5421_write_event_config(struct iio_dev *indio_dev,
  328. const struct iio_chan_spec *chan, enum iio_event_type type,
  329. enum iio_event_direction dir, int state)
  330. {
  331. struct ad5421_state *st = iio_priv(indio_dev);
  332. unsigned int mask;
  333. switch (chan->type) {
  334. case IIO_CURRENT:
  335. if (dir == IIO_EV_DIR_RISING)
  336. mask = AD5421_FAULT_OVER_CURRENT;
  337. else
  338. mask = AD5421_FAULT_UNDER_CURRENT;
  339. break;
  340. case IIO_TEMP:
  341. mask = AD5421_FAULT_TEMP_OVER_140;
  342. break;
  343. default:
  344. return -EINVAL;
  345. }
  346. mutex_lock(&st->lock);
  347. if (state)
  348. st->fault_mask |= mask;
  349. else
  350. st->fault_mask &= ~mask;
  351. mutex_unlock(&st->lock);
  352. return 0;
  353. }
  354. static int ad5421_read_event_config(struct iio_dev *indio_dev,
  355. const struct iio_chan_spec *chan, enum iio_event_type type,
  356. enum iio_event_direction dir)
  357. {
  358. struct ad5421_state *st = iio_priv(indio_dev);
  359. unsigned int mask;
  360. switch (chan->type) {
  361. case IIO_CURRENT:
  362. if (dir == IIO_EV_DIR_RISING)
  363. mask = AD5421_FAULT_OVER_CURRENT;
  364. else
  365. mask = AD5421_FAULT_UNDER_CURRENT;
  366. break;
  367. case IIO_TEMP:
  368. mask = AD5421_FAULT_TEMP_OVER_140;
  369. break;
  370. default:
  371. return -EINVAL;
  372. }
  373. return (bool)(st->fault_mask & mask);
  374. }
  375. static int ad5421_read_event_value(struct iio_dev *indio_dev,
  376. const struct iio_chan_spec *chan, enum iio_event_type type,
  377. enum iio_event_direction dir, enum iio_event_info info, int *val,
  378. int *val2)
  379. {
  380. int ret;
  381. switch (chan->type) {
  382. case IIO_CURRENT:
  383. ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
  384. if (ret < 0)
  385. return ret;
  386. *val = ret;
  387. break;
  388. case IIO_TEMP:
  389. *val = 140000;
  390. break;
  391. default:
  392. return -EINVAL;
  393. }
  394. return IIO_VAL_INT;
  395. }
  396. static const struct iio_info ad5421_info = {
  397. .read_raw = ad5421_read_raw,
  398. .write_raw = ad5421_write_raw,
  399. .read_event_config = ad5421_read_event_config,
  400. .write_event_config = ad5421_write_event_config,
  401. .read_event_value = ad5421_read_event_value,
  402. };
  403. static int ad5421_probe(struct spi_device *spi)
  404. {
  405. struct ad5421_platform_data *pdata = dev_get_platdata(&spi->dev);
  406. struct iio_dev *indio_dev;
  407. struct ad5421_state *st;
  408. int ret;
  409. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  410. if (indio_dev == NULL) {
  411. dev_err(&spi->dev, "Failed to allocate iio device\n");
  412. return -ENOMEM;
  413. }
  414. st = iio_priv(indio_dev);
  415. spi_set_drvdata(spi, indio_dev);
  416. st->spi = spi;
  417. indio_dev->name = "ad5421";
  418. indio_dev->info = &ad5421_info;
  419. indio_dev->modes = INDIO_DIRECT_MODE;
  420. indio_dev->channels = ad5421_channels;
  421. indio_dev->num_channels = ARRAY_SIZE(ad5421_channels);
  422. mutex_init(&st->lock);
  423. st->ctrl = AD5421_CTRL_WATCHDOG_DISABLE |
  424. AD5421_CTRL_AUTO_FAULT_READBACK;
  425. if (pdata) {
  426. st->current_range = pdata->current_range;
  427. if (pdata->external_vref)
  428. st->ctrl |= AD5421_CTRL_PWR_DOWN_INT_VREF;
  429. } else {
  430. st->current_range = AD5421_CURRENT_RANGE_4mA_20mA;
  431. }
  432. /* write initial ctrl register value */
  433. ad5421_update_ctrl(indio_dev, 0, 0);
  434. if (spi->irq) {
  435. ret = devm_request_threaded_irq(&spi->dev, spi->irq,
  436. NULL,
  437. ad5421_fault_handler,
  438. IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
  439. "ad5421 fault",
  440. indio_dev);
  441. if (ret)
  442. return ret;
  443. }
  444. return devm_iio_device_register(&spi->dev, indio_dev);
  445. }
  446. static struct spi_driver ad5421_driver = {
  447. .driver = {
  448. .name = "ad5421",
  449. },
  450. .probe = ad5421_probe,
  451. };
  452. module_spi_driver(ad5421_driver);
  453. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  454. MODULE_DESCRIPTION("Analog Devices AD5421 DAC");
  455. MODULE_LICENSE("GPL v2");
  456. MODULE_ALIAS("spi:ad5421");