ad5360.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Analog devices AD5360, AD5361, AD5362, AD5363, AD5370, AD5371, AD5373
  4. * multi-channel Digital to Analog Converters driver
  5. *
  6. * Copyright 2011 Analog Devices Inc.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/err.h>
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/spi/spi.h>
  13. #include <linux/slab.h>
  14. #include <linux/sysfs.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/iio/iio.h>
  17. #include <linux/iio/sysfs.h>
  18. #define AD5360_CMD(x) ((x) << 22)
  19. #define AD5360_ADDR(x) ((x) << 16)
  20. #define AD5360_READBACK_TYPE(x) ((x) << 13)
  21. #define AD5360_READBACK_ADDR(x) ((x) << 7)
  22. #define AD5360_CHAN_ADDR(chan) ((chan) + 0x8)
  23. #define AD5360_CMD_WRITE_DATA 0x3
  24. #define AD5360_CMD_WRITE_OFFSET 0x2
  25. #define AD5360_CMD_WRITE_GAIN 0x1
  26. #define AD5360_CMD_SPECIAL_FUNCTION 0x0
  27. /* Special function register addresses */
  28. #define AD5360_REG_SF_NOP 0x0
  29. #define AD5360_REG_SF_CTRL 0x1
  30. #define AD5360_REG_SF_OFS(x) (0x2 + (x))
  31. #define AD5360_REG_SF_READBACK 0x5
  32. #define AD5360_SF_CTRL_PWR_DOWN BIT(0)
  33. #define AD5360_READBACK_X1A 0x0
  34. #define AD5360_READBACK_X1B 0x1
  35. #define AD5360_READBACK_OFFSET 0x2
  36. #define AD5360_READBACK_GAIN 0x3
  37. #define AD5360_READBACK_SF 0x4
  38. /**
  39. * struct ad5360_chip_info - chip specific information
  40. * @channel_template: channel specification template
  41. * @num_channels: number of channels
  42. * @channels_per_group: number of channels per group
  43. * @num_vrefs: number of vref supplies for the chip
  44. */
  45. struct ad5360_chip_info {
  46. struct iio_chan_spec channel_template;
  47. unsigned int num_channels;
  48. unsigned int channels_per_group;
  49. unsigned int num_vrefs;
  50. };
  51. /**
  52. * struct ad5360_state - driver instance specific data
  53. * @spi: spi_device
  54. * @chip_info: chip model specific constants, available modes etc
  55. * @vref_reg: vref supply regulators
  56. * @ctrl: control register cache
  57. * @lock: lock to protect the data buffer during SPI ops
  58. * @data: spi transfer buffers
  59. */
  60. struct ad5360_state {
  61. struct spi_device *spi;
  62. const struct ad5360_chip_info *chip_info;
  63. struct regulator_bulk_data vref_reg[3];
  64. unsigned int ctrl;
  65. struct mutex lock;
  66. /*
  67. * DMA (thus cache coherency maintenance) requires the
  68. * transfer buffers to live in their own cache lines.
  69. */
  70. union {
  71. __be32 d32;
  72. u8 d8[4];
  73. } data[2] ____cacheline_aligned;
  74. };
  75. enum ad5360_type {
  76. ID_AD5360,
  77. ID_AD5361,
  78. ID_AD5362,
  79. ID_AD5363,
  80. ID_AD5370,
  81. ID_AD5371,
  82. ID_AD5372,
  83. ID_AD5373,
  84. };
  85. #define AD5360_CHANNEL(bits) { \
  86. .type = IIO_VOLTAGE, \
  87. .indexed = 1, \
  88. .output = 1, \
  89. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  90. BIT(IIO_CHAN_INFO_SCALE) | \
  91. BIT(IIO_CHAN_INFO_OFFSET) | \
  92. BIT(IIO_CHAN_INFO_CALIBSCALE) | \
  93. BIT(IIO_CHAN_INFO_CALIBBIAS), \
  94. .scan_type = { \
  95. .sign = 'u', \
  96. .realbits = (bits), \
  97. .storagebits = 16, \
  98. .shift = 16 - (bits), \
  99. }, \
  100. }
  101. static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
  102. [ID_AD5360] = {
  103. .channel_template = AD5360_CHANNEL(16),
  104. .num_channels = 16,
  105. .channels_per_group = 8,
  106. .num_vrefs = 2,
  107. },
  108. [ID_AD5361] = {
  109. .channel_template = AD5360_CHANNEL(14),
  110. .num_channels = 16,
  111. .channels_per_group = 8,
  112. .num_vrefs = 2,
  113. },
  114. [ID_AD5362] = {
  115. .channel_template = AD5360_CHANNEL(16),
  116. .num_channels = 8,
  117. .channels_per_group = 4,
  118. .num_vrefs = 2,
  119. },
  120. [ID_AD5363] = {
  121. .channel_template = AD5360_CHANNEL(14),
  122. .num_channels = 8,
  123. .channels_per_group = 4,
  124. .num_vrefs = 2,
  125. },
  126. [ID_AD5370] = {
  127. .channel_template = AD5360_CHANNEL(16),
  128. .num_channels = 40,
  129. .channels_per_group = 8,
  130. .num_vrefs = 2,
  131. },
  132. [ID_AD5371] = {
  133. .channel_template = AD5360_CHANNEL(14),
  134. .num_channels = 40,
  135. .channels_per_group = 8,
  136. .num_vrefs = 3,
  137. },
  138. [ID_AD5372] = {
  139. .channel_template = AD5360_CHANNEL(16),
  140. .num_channels = 32,
  141. .channels_per_group = 8,
  142. .num_vrefs = 2,
  143. },
  144. [ID_AD5373] = {
  145. .channel_template = AD5360_CHANNEL(14),
  146. .num_channels = 32,
  147. .channels_per_group = 8,
  148. .num_vrefs = 2,
  149. },
  150. };
  151. static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
  152. unsigned int channel)
  153. {
  154. unsigned int i;
  155. /* The first groups have their own vref, while the remaining groups
  156. * share the last vref */
  157. i = channel / st->chip_info->channels_per_group;
  158. if (i >= st->chip_info->num_vrefs)
  159. i = st->chip_info->num_vrefs - 1;
  160. return i;
  161. }
  162. static int ad5360_get_channel_vref(struct ad5360_state *st,
  163. unsigned int channel)
  164. {
  165. unsigned int i = ad5360_get_channel_vref_index(st, channel);
  166. return regulator_get_voltage(st->vref_reg[i].consumer);
  167. }
  168. static int ad5360_write_unlocked(struct iio_dev *indio_dev,
  169. unsigned int cmd, unsigned int addr, unsigned int val,
  170. unsigned int shift)
  171. {
  172. struct ad5360_state *st = iio_priv(indio_dev);
  173. val <<= shift;
  174. val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
  175. st->data[0].d32 = cpu_to_be32(val);
  176. return spi_write(st->spi, &st->data[0].d8[1], 3);
  177. }
  178. static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
  179. unsigned int addr, unsigned int val, unsigned int shift)
  180. {
  181. int ret;
  182. struct ad5360_state *st = iio_priv(indio_dev);
  183. mutex_lock(&st->lock);
  184. ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
  185. mutex_unlock(&st->lock);
  186. return ret;
  187. }
  188. static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
  189. unsigned int addr)
  190. {
  191. struct ad5360_state *st = iio_priv(indio_dev);
  192. int ret;
  193. struct spi_transfer t[] = {
  194. {
  195. .tx_buf = &st->data[0].d8[1],
  196. .len = 3,
  197. .cs_change = 1,
  198. }, {
  199. .rx_buf = &st->data[1].d8[1],
  200. .len = 3,
  201. },
  202. };
  203. mutex_lock(&st->lock);
  204. st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
  205. AD5360_ADDR(AD5360_REG_SF_READBACK) |
  206. AD5360_READBACK_TYPE(type) |
  207. AD5360_READBACK_ADDR(addr));
  208. ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
  209. if (ret >= 0)
  210. ret = be32_to_cpu(st->data[1].d32) & 0xffff;
  211. mutex_unlock(&st->lock);
  212. return ret;
  213. }
  214. static ssize_t ad5360_read_dac_powerdown(struct device *dev,
  215. struct device_attribute *attr,
  216. char *buf)
  217. {
  218. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  219. struct ad5360_state *st = iio_priv(indio_dev);
  220. return sprintf(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
  221. }
  222. static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
  223. unsigned int clr)
  224. {
  225. struct ad5360_state *st = iio_priv(indio_dev);
  226. unsigned int ret;
  227. mutex_lock(&st->lock);
  228. st->ctrl |= set;
  229. st->ctrl &= ~clr;
  230. ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
  231. AD5360_REG_SF_CTRL, st->ctrl, 0);
  232. mutex_unlock(&st->lock);
  233. return ret;
  234. }
  235. static ssize_t ad5360_write_dac_powerdown(struct device *dev,
  236. struct device_attribute *attr, const char *buf, size_t len)
  237. {
  238. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  239. bool pwr_down;
  240. int ret;
  241. ret = strtobool(buf, &pwr_down);
  242. if (ret)
  243. return ret;
  244. if (pwr_down)
  245. ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
  246. else
  247. ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
  248. return ret ? ret : len;
  249. }
  250. static IIO_DEVICE_ATTR(out_voltage_powerdown,
  251. S_IRUGO | S_IWUSR,
  252. ad5360_read_dac_powerdown,
  253. ad5360_write_dac_powerdown, 0);
  254. static struct attribute *ad5360_attributes[] = {
  255. &iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
  256. NULL,
  257. };
  258. static const struct attribute_group ad5360_attribute_group = {
  259. .attrs = ad5360_attributes,
  260. };
  261. static int ad5360_write_raw(struct iio_dev *indio_dev,
  262. struct iio_chan_spec const *chan,
  263. int val,
  264. int val2,
  265. long mask)
  266. {
  267. struct ad5360_state *st = iio_priv(indio_dev);
  268. int max_val = (1 << chan->scan_type.realbits);
  269. unsigned int ofs_index;
  270. switch (mask) {
  271. case IIO_CHAN_INFO_RAW:
  272. if (val >= max_val || val < 0)
  273. return -EINVAL;
  274. return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
  275. chan->address, val, chan->scan_type.shift);
  276. case IIO_CHAN_INFO_CALIBBIAS:
  277. if (val >= max_val || val < 0)
  278. return -EINVAL;
  279. return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
  280. chan->address, val, chan->scan_type.shift);
  281. case IIO_CHAN_INFO_CALIBSCALE:
  282. if (val >= max_val || val < 0)
  283. return -EINVAL;
  284. return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
  285. chan->address, val, chan->scan_type.shift);
  286. case IIO_CHAN_INFO_OFFSET:
  287. if (val <= -max_val || val > 0)
  288. return -EINVAL;
  289. val = -val;
  290. /* offset is supposed to have the same scale as raw, but it
  291. * is always 14bits wide, so on a chip where the raw value has
  292. * more bits, we need to shift offset. */
  293. val >>= (chan->scan_type.realbits - 14);
  294. /* There is one DAC offset register per vref. Changing one
  295. * channels offset will also change the offset for all other
  296. * channels which share the same vref supply. */
  297. ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
  298. return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
  299. AD5360_REG_SF_OFS(ofs_index), val, 0);
  300. default:
  301. break;
  302. }
  303. return -EINVAL;
  304. }
  305. static int ad5360_read_raw(struct iio_dev *indio_dev,
  306. struct iio_chan_spec const *chan,
  307. int *val,
  308. int *val2,
  309. long m)
  310. {
  311. struct ad5360_state *st = iio_priv(indio_dev);
  312. unsigned int ofs_index;
  313. int scale_uv;
  314. int ret;
  315. switch (m) {
  316. case IIO_CHAN_INFO_RAW:
  317. ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
  318. chan->address);
  319. if (ret < 0)
  320. return ret;
  321. *val = ret >> chan->scan_type.shift;
  322. return IIO_VAL_INT;
  323. case IIO_CHAN_INFO_SCALE:
  324. scale_uv = ad5360_get_channel_vref(st, chan->channel);
  325. if (scale_uv < 0)
  326. return scale_uv;
  327. /* vout = 4 * vref * dac_code */
  328. *val = scale_uv * 4 / 1000;
  329. *val2 = chan->scan_type.realbits;
  330. return IIO_VAL_FRACTIONAL_LOG2;
  331. case IIO_CHAN_INFO_CALIBBIAS:
  332. ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
  333. chan->address);
  334. if (ret < 0)
  335. return ret;
  336. *val = ret;
  337. return IIO_VAL_INT;
  338. case IIO_CHAN_INFO_CALIBSCALE:
  339. ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
  340. chan->address);
  341. if (ret < 0)
  342. return ret;
  343. *val = ret;
  344. return IIO_VAL_INT;
  345. case IIO_CHAN_INFO_OFFSET:
  346. ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
  347. ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
  348. AD5360_REG_SF_OFS(ofs_index));
  349. if (ret < 0)
  350. return ret;
  351. ret <<= (chan->scan_type.realbits - 14);
  352. *val = -ret;
  353. return IIO_VAL_INT;
  354. }
  355. return -EINVAL;
  356. }
  357. static const struct iio_info ad5360_info = {
  358. .read_raw = ad5360_read_raw,
  359. .write_raw = ad5360_write_raw,
  360. .attrs = &ad5360_attribute_group,
  361. };
  362. static const char * const ad5360_vref_name[] = {
  363. "vref0", "vref1", "vref2"
  364. };
  365. static int ad5360_alloc_channels(struct iio_dev *indio_dev)
  366. {
  367. struct ad5360_state *st = iio_priv(indio_dev);
  368. struct iio_chan_spec *channels;
  369. unsigned int i;
  370. channels = kcalloc(st->chip_info->num_channels,
  371. sizeof(struct iio_chan_spec), GFP_KERNEL);
  372. if (!channels)
  373. return -ENOMEM;
  374. for (i = 0; i < st->chip_info->num_channels; ++i) {
  375. channels[i] = st->chip_info->channel_template;
  376. channels[i].channel = i;
  377. channels[i].address = AD5360_CHAN_ADDR(i);
  378. }
  379. indio_dev->channels = channels;
  380. return 0;
  381. }
  382. static int ad5360_probe(struct spi_device *spi)
  383. {
  384. enum ad5360_type type = spi_get_device_id(spi)->driver_data;
  385. struct iio_dev *indio_dev;
  386. struct ad5360_state *st;
  387. unsigned int i;
  388. int ret;
  389. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  390. if (indio_dev == NULL) {
  391. dev_err(&spi->dev, "Failed to allocate iio device\n");
  392. return -ENOMEM;
  393. }
  394. st = iio_priv(indio_dev);
  395. spi_set_drvdata(spi, indio_dev);
  396. st->chip_info = &ad5360_chip_info_tbl[type];
  397. st->spi = spi;
  398. indio_dev->name = spi_get_device_id(spi)->name;
  399. indio_dev->info = &ad5360_info;
  400. indio_dev->modes = INDIO_DIRECT_MODE;
  401. indio_dev->num_channels = st->chip_info->num_channels;
  402. mutex_init(&st->lock);
  403. ret = ad5360_alloc_channels(indio_dev);
  404. if (ret) {
  405. dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
  406. return ret;
  407. }
  408. for (i = 0; i < st->chip_info->num_vrefs; ++i)
  409. st->vref_reg[i].supply = ad5360_vref_name[i];
  410. ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
  411. st->vref_reg);
  412. if (ret) {
  413. dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
  414. goto error_free_channels;
  415. }
  416. ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
  417. if (ret) {
  418. dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
  419. goto error_free_channels;
  420. }
  421. ret = iio_device_register(indio_dev);
  422. if (ret) {
  423. dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
  424. goto error_disable_reg;
  425. }
  426. return 0;
  427. error_disable_reg:
  428. regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
  429. error_free_channels:
  430. kfree(indio_dev->channels);
  431. return ret;
  432. }
  433. static int ad5360_remove(struct spi_device *spi)
  434. {
  435. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  436. struct ad5360_state *st = iio_priv(indio_dev);
  437. iio_device_unregister(indio_dev);
  438. kfree(indio_dev->channels);
  439. regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
  440. return 0;
  441. }
  442. static const struct spi_device_id ad5360_ids[] = {
  443. { "ad5360", ID_AD5360 },
  444. { "ad5361", ID_AD5361 },
  445. { "ad5362", ID_AD5362 },
  446. { "ad5363", ID_AD5363 },
  447. { "ad5370", ID_AD5370 },
  448. { "ad5371", ID_AD5371 },
  449. { "ad5372", ID_AD5372 },
  450. { "ad5373", ID_AD5373 },
  451. {}
  452. };
  453. MODULE_DEVICE_TABLE(spi, ad5360_ids);
  454. static struct spi_driver ad5360_driver = {
  455. .driver = {
  456. .name = "ad5360",
  457. },
  458. .probe = ad5360_probe,
  459. .remove = ad5360_remove,
  460. .id_table = ad5360_ids,
  461. };
  462. module_spi_driver(ad5360_driver);
  463. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  464. MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
  465. MODULE_LICENSE("GPL v2");