xilinx-xadc-core.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Xilinx XADC driver
  4. *
  5. * Copyright 2013-2014 Analog Devices Inc.
  6. * Author: Lars-Peter Clausen <lars@metafoo.de>
  7. *
  8. * Documentation for the parts can be found at:
  9. * - XADC hardmacro: Xilinx UG480
  10. * - ZYNQ XADC interface: Xilinx UG585
  11. * - AXI XADC interface: Xilinx PG019
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/device.h>
  15. #include <linux/err.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <linux/sysfs.h>
  24. #include <linux/iio/buffer.h>
  25. #include <linux/iio/events.h>
  26. #include <linux/iio/iio.h>
  27. #include <linux/iio/sysfs.h>
  28. #include <linux/iio/trigger.h>
  29. #include <linux/iio/trigger_consumer.h>
  30. #include <linux/iio/triggered_buffer.h>
  31. #include "xilinx-xadc.h"
  32. static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
  33. /* ZYNQ register definitions */
  34. #define XADC_ZYNQ_REG_CFG 0x00
  35. #define XADC_ZYNQ_REG_INTSTS 0x04
  36. #define XADC_ZYNQ_REG_INTMSK 0x08
  37. #define XADC_ZYNQ_REG_STATUS 0x0c
  38. #define XADC_ZYNQ_REG_CFIFO 0x10
  39. #define XADC_ZYNQ_REG_DFIFO 0x14
  40. #define XADC_ZYNQ_REG_CTL 0x18
  41. #define XADC_ZYNQ_CFG_ENABLE BIT(31)
  42. #define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
  43. #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
  44. #define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
  45. #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
  46. #define XADC_ZYNQ_CFG_WEDGE BIT(13)
  47. #define XADC_ZYNQ_CFG_REDGE BIT(12)
  48. #define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
  49. #define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
  50. #define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
  51. #define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
  52. #define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
  53. #define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
  54. #define XADC_ZYNQ_CFG_IGAP(x) (x)
  55. #define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
  56. #define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
  57. #define XADC_ZYNQ_INT_ALARM_MASK 0xff
  58. #define XADC_ZYNQ_INT_ALARM_OFFSET 0
  59. #define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
  60. #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
  61. #define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
  62. #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
  63. #define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
  64. #define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
  65. #define XADC_ZYNQ_STATUS_DFIFOF BIT(9)
  66. #define XADC_ZYNQ_STATUS_DFIFOE BIT(8)
  67. #define XADC_ZYNQ_STATUS_OT BIT(7)
  68. #define XADC_ZYNQ_STATUS_ALM(x) BIT(x)
  69. #define XADC_ZYNQ_CTL_RESET BIT(4)
  70. #define XADC_ZYNQ_CMD_NOP 0x00
  71. #define XADC_ZYNQ_CMD_READ 0x01
  72. #define XADC_ZYNQ_CMD_WRITE 0x02
  73. #define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
  74. /* AXI register definitions */
  75. #define XADC_AXI_REG_RESET 0x00
  76. #define XADC_AXI_REG_STATUS 0x04
  77. #define XADC_AXI_REG_ALARM_STATUS 0x08
  78. #define XADC_AXI_REG_CONVST 0x0c
  79. #define XADC_AXI_REG_XADC_RESET 0x10
  80. #define XADC_AXI_REG_GIER 0x5c
  81. #define XADC_AXI_REG_IPISR 0x60
  82. #define XADC_AXI_REG_IPIER 0x68
  83. #define XADC_AXI_ADC_REG_OFFSET 0x200
  84. #define XADC_AXI_RESET_MAGIC 0xa
  85. #define XADC_AXI_GIER_ENABLE BIT(31)
  86. #define XADC_AXI_INT_EOS BIT(4)
  87. #define XADC_AXI_INT_ALARM_MASK 0x3c0f
  88. #define XADC_FLAGS_BUFFERED BIT(0)
  89. /*
  90. * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
  91. * not have a hardware FIFO. Which means an interrupt is generated for each
  92. * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
  93. * overloaded by the interrupts that it soft-lockups. For this reason the driver
  94. * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
  95. * but still responsive.
  96. */
  97. #define XADC_MAX_SAMPLERATE 150000
  98. static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
  99. uint32_t val)
  100. {
  101. writel(val, xadc->base + reg);
  102. }
  103. static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
  104. uint32_t *val)
  105. {
  106. *val = readl(xadc->base + reg);
  107. }
  108. /*
  109. * The ZYNQ interface uses two asynchronous FIFOs for communication with the
  110. * XADC. Reads and writes to the XADC register are performed by submitting a
  111. * request to the command FIFO (CFIFO), once the request has been completed the
  112. * result can be read from the data FIFO (DFIFO). The method currently used in
  113. * this driver is to submit the request for a read/write operation, then go to
  114. * sleep and wait for an interrupt that signals that a response is available in
  115. * the data FIFO.
  116. */
  117. static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
  118. unsigned int n)
  119. {
  120. unsigned int i;
  121. for (i = 0; i < n; i++)
  122. xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
  123. }
  124. static void xadc_zynq_drain_fifo(struct xadc *xadc)
  125. {
  126. uint32_t status, tmp;
  127. xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
  128. while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
  129. xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
  130. xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
  131. }
  132. }
  133. static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
  134. unsigned int val)
  135. {
  136. xadc->zynq_intmask &= ~mask;
  137. xadc->zynq_intmask |= val;
  138. xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
  139. xadc->zynq_intmask | xadc->zynq_masked_alarm);
  140. }
  141. static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
  142. uint16_t val)
  143. {
  144. uint32_t cmd[1];
  145. uint32_t tmp;
  146. int ret;
  147. spin_lock_irq(&xadc->lock);
  148. xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
  149. XADC_ZYNQ_INT_DFIFO_GTH);
  150. reinit_completion(&xadc->completion);
  151. cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
  152. xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
  153. xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
  154. tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
  155. tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
  156. xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
  157. xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
  158. spin_unlock_irq(&xadc->lock);
  159. ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
  160. if (ret == 0)
  161. ret = -EIO;
  162. else
  163. ret = 0;
  164. xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
  165. return ret;
  166. }
  167. static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
  168. uint16_t *val)
  169. {
  170. uint32_t cmd[2];
  171. uint32_t resp, tmp;
  172. int ret;
  173. cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
  174. cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
  175. spin_lock_irq(&xadc->lock);
  176. xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
  177. XADC_ZYNQ_INT_DFIFO_GTH);
  178. xadc_zynq_drain_fifo(xadc);
  179. reinit_completion(&xadc->completion);
  180. xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
  181. xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
  182. tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
  183. tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
  184. xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
  185. xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
  186. spin_unlock_irq(&xadc->lock);
  187. ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
  188. if (ret == 0)
  189. ret = -EIO;
  190. if (ret < 0)
  191. return ret;
  192. xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
  193. xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
  194. *val = resp & 0xffff;
  195. return 0;
  196. }
  197. static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
  198. {
  199. return ((alarm & 0x80) >> 4) |
  200. ((alarm & 0x78) << 1) |
  201. (alarm & 0x07);
  202. }
  203. /*
  204. * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
  205. * threshold condition go way from within the interrupt handler, this means as
  206. * soon as a threshold condition is present we would enter the interrupt handler
  207. * again and again. To work around this we mask all active thresholds interrupts
  208. * in the interrupt handler and start a timer. In this timer we poll the
  209. * interrupt status and only if the interrupt is inactive we unmask it again.
  210. */
  211. static void xadc_zynq_unmask_worker(struct work_struct *work)
  212. {
  213. struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
  214. unsigned int misc_sts, unmask;
  215. xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
  216. misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
  217. spin_lock_irq(&xadc->lock);
  218. /* Clear those bits which are not active anymore */
  219. unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
  220. xadc->zynq_masked_alarm &= misc_sts;
  221. /* Also clear those which are masked out anyway */
  222. xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
  223. /* Clear the interrupts before we unmask them */
  224. xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
  225. xadc_zynq_update_intmsk(xadc, 0, 0);
  226. spin_unlock_irq(&xadc->lock);
  227. /* if still pending some alarm re-trigger the timer */
  228. if (xadc->zynq_masked_alarm) {
  229. schedule_delayed_work(&xadc->zynq_unmask_work,
  230. msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
  231. }
  232. }
  233. static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
  234. {
  235. struct iio_dev *indio_dev = devid;
  236. struct xadc *xadc = iio_priv(indio_dev);
  237. uint32_t status;
  238. xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
  239. status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
  240. if (!status)
  241. return IRQ_NONE;
  242. spin_lock(&xadc->lock);
  243. xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
  244. if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
  245. xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
  246. XADC_ZYNQ_INT_DFIFO_GTH);
  247. complete(&xadc->completion);
  248. }
  249. status &= XADC_ZYNQ_INT_ALARM_MASK;
  250. if (status) {
  251. xadc->zynq_masked_alarm |= status;
  252. /*
  253. * mask the current event interrupt,
  254. * unmask it when the interrupt is no more active.
  255. */
  256. xadc_zynq_update_intmsk(xadc, 0, 0);
  257. xadc_handle_events(indio_dev,
  258. xadc_zynq_transform_alarm(status));
  259. /* unmask the required interrupts in timer. */
  260. schedule_delayed_work(&xadc->zynq_unmask_work,
  261. msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
  262. }
  263. spin_unlock(&xadc->lock);
  264. return IRQ_HANDLED;
  265. }
  266. #define XADC_ZYNQ_TCK_RATE_MAX 50000000
  267. #define XADC_ZYNQ_IGAP_DEFAULT 20
  268. #define XADC_ZYNQ_PCAP_RATE_MAX 200000000
  269. static int xadc_zynq_setup(struct platform_device *pdev,
  270. struct iio_dev *indio_dev, int irq)
  271. {
  272. struct xadc *xadc = iio_priv(indio_dev);
  273. unsigned long pcap_rate;
  274. unsigned int tck_div;
  275. unsigned int div;
  276. unsigned int igap;
  277. unsigned int tck_rate;
  278. int ret;
  279. /* TODO: Figure out how to make igap and tck_rate configurable */
  280. igap = XADC_ZYNQ_IGAP_DEFAULT;
  281. tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
  282. xadc->zynq_intmask = ~0;
  283. pcap_rate = clk_get_rate(xadc->clk);
  284. if (!pcap_rate)
  285. return -EINVAL;
  286. if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
  287. ret = clk_set_rate(xadc->clk,
  288. (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
  289. if (ret)
  290. return ret;
  291. }
  292. if (tck_rate > pcap_rate / 2) {
  293. div = 2;
  294. } else {
  295. div = pcap_rate / tck_rate;
  296. if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
  297. div++;
  298. }
  299. if (div <= 3)
  300. tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
  301. else if (div <= 7)
  302. tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
  303. else if (div <= 15)
  304. tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
  305. else
  306. tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
  307. xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
  308. xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
  309. xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
  310. xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
  311. xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
  312. XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
  313. tck_div | XADC_ZYNQ_CFG_IGAP(igap));
  314. if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
  315. ret = clk_set_rate(xadc->clk, pcap_rate);
  316. if (ret)
  317. return ret;
  318. }
  319. return 0;
  320. }
  321. static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
  322. {
  323. unsigned int div;
  324. uint32_t val;
  325. xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
  326. switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
  327. case XADC_ZYNQ_CFG_TCKRATE_DIV4:
  328. div = 4;
  329. break;
  330. case XADC_ZYNQ_CFG_TCKRATE_DIV8:
  331. div = 8;
  332. break;
  333. case XADC_ZYNQ_CFG_TCKRATE_DIV16:
  334. div = 16;
  335. break;
  336. default:
  337. div = 2;
  338. break;
  339. }
  340. return clk_get_rate(xadc->clk) / div;
  341. }
  342. static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
  343. {
  344. unsigned long flags;
  345. uint32_t status;
  346. /* Move OT to bit 7 */
  347. alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
  348. spin_lock_irqsave(&xadc->lock, flags);
  349. /* Clear previous interrupts if any. */
  350. xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
  351. xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
  352. xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
  353. ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
  354. spin_unlock_irqrestore(&xadc->lock, flags);
  355. }
  356. static const struct xadc_ops xadc_zynq_ops = {
  357. .read = xadc_zynq_read_adc_reg,
  358. .write = xadc_zynq_write_adc_reg,
  359. .setup = xadc_zynq_setup,
  360. .get_dclk_rate = xadc_zynq_get_dclk_rate,
  361. .interrupt_handler = xadc_zynq_interrupt_handler,
  362. .update_alarm = xadc_zynq_update_alarm,
  363. };
  364. static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
  365. uint16_t *val)
  366. {
  367. uint32_t val32;
  368. xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32);
  369. *val = val32 & 0xffff;
  370. return 0;
  371. }
  372. static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
  373. uint16_t val)
  374. {
  375. xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val);
  376. return 0;
  377. }
  378. static int xadc_axi_setup(struct platform_device *pdev,
  379. struct iio_dev *indio_dev, int irq)
  380. {
  381. struct xadc *xadc = iio_priv(indio_dev);
  382. xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
  383. xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
  384. return 0;
  385. }
  386. static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
  387. {
  388. struct iio_dev *indio_dev = devid;
  389. struct xadc *xadc = iio_priv(indio_dev);
  390. uint32_t status, mask;
  391. unsigned int events;
  392. xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
  393. xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
  394. status &= mask;
  395. if (!status)
  396. return IRQ_NONE;
  397. if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
  398. iio_trigger_poll(xadc->trigger);
  399. if (status & XADC_AXI_INT_ALARM_MASK) {
  400. /*
  401. * The order of the bits in the AXI-XADC status register does
  402. * not match the order of the bits in the XADC alarm enable
  403. * register. xadc_handle_events() expects the events to be in
  404. * the same order as the XADC alarm enable register.
  405. */
  406. events = (status & 0x000e) >> 1;
  407. events |= (status & 0x0001) << 3;
  408. events |= (status & 0x3c00) >> 6;
  409. xadc_handle_events(indio_dev, events);
  410. }
  411. xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
  412. return IRQ_HANDLED;
  413. }
  414. static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
  415. {
  416. uint32_t val;
  417. unsigned long flags;
  418. /*
  419. * The order of the bits in the AXI-XADC status register does not match
  420. * the order of the bits in the XADC alarm enable register. We get
  421. * passed the alarm mask in the same order as in the XADC alarm enable
  422. * register.
  423. */
  424. alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
  425. ((alarm & 0xf0) << 6);
  426. spin_lock_irqsave(&xadc->lock, flags);
  427. xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
  428. val &= ~XADC_AXI_INT_ALARM_MASK;
  429. val |= alarm;
  430. xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
  431. spin_unlock_irqrestore(&xadc->lock, flags);
  432. }
  433. static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
  434. {
  435. return clk_get_rate(xadc->clk);
  436. }
  437. static const struct xadc_ops xadc_axi_ops = {
  438. .read = xadc_axi_read_adc_reg,
  439. .write = xadc_axi_write_adc_reg,
  440. .setup = xadc_axi_setup,
  441. .get_dclk_rate = xadc_axi_get_dclk,
  442. .update_alarm = xadc_axi_update_alarm,
  443. .interrupt_handler = xadc_axi_interrupt_handler,
  444. .flags = XADC_FLAGS_BUFFERED,
  445. };
  446. static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
  447. uint16_t mask, uint16_t val)
  448. {
  449. uint16_t tmp;
  450. int ret;
  451. ret = _xadc_read_adc_reg(xadc, reg, &tmp);
  452. if (ret)
  453. return ret;
  454. return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
  455. }
  456. static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
  457. uint16_t mask, uint16_t val)
  458. {
  459. int ret;
  460. mutex_lock(&xadc->mutex);
  461. ret = _xadc_update_adc_reg(xadc, reg, mask, val);
  462. mutex_unlock(&xadc->mutex);
  463. return ret;
  464. }
  465. static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
  466. {
  467. return xadc->ops->get_dclk_rate(xadc);
  468. }
  469. static int xadc_update_scan_mode(struct iio_dev *indio_dev,
  470. const unsigned long *mask)
  471. {
  472. struct xadc *xadc = iio_priv(indio_dev);
  473. unsigned int n;
  474. n = bitmap_weight(mask, indio_dev->masklength);
  475. kfree(xadc->data);
  476. xadc->data = kcalloc(n, sizeof(*xadc->data), GFP_KERNEL);
  477. if (!xadc->data)
  478. return -ENOMEM;
  479. return 0;
  480. }
  481. static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
  482. {
  483. switch (scan_index) {
  484. case 5:
  485. return XADC_REG_VCCPINT;
  486. case 6:
  487. return XADC_REG_VCCPAUX;
  488. case 7:
  489. return XADC_REG_VCCO_DDR;
  490. case 8:
  491. return XADC_REG_TEMP;
  492. case 9:
  493. return XADC_REG_VCCINT;
  494. case 10:
  495. return XADC_REG_VCCAUX;
  496. case 11:
  497. return XADC_REG_VPVN;
  498. case 12:
  499. return XADC_REG_VREFP;
  500. case 13:
  501. return XADC_REG_VREFN;
  502. case 14:
  503. return XADC_REG_VCCBRAM;
  504. default:
  505. return XADC_REG_VAUX(scan_index - 16);
  506. }
  507. }
  508. static irqreturn_t xadc_trigger_handler(int irq, void *p)
  509. {
  510. struct iio_poll_func *pf = p;
  511. struct iio_dev *indio_dev = pf->indio_dev;
  512. struct xadc *xadc = iio_priv(indio_dev);
  513. unsigned int chan;
  514. int i, j;
  515. if (!xadc->data)
  516. goto out;
  517. j = 0;
  518. for_each_set_bit(i, indio_dev->active_scan_mask,
  519. indio_dev->masklength) {
  520. chan = xadc_scan_index_to_channel(i);
  521. xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
  522. j++;
  523. }
  524. iio_push_to_buffers(indio_dev, xadc->data);
  525. out:
  526. iio_trigger_notify_done(indio_dev->trig);
  527. return IRQ_HANDLED;
  528. }
  529. static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
  530. {
  531. struct xadc *xadc = iio_trigger_get_drvdata(trigger);
  532. unsigned long flags;
  533. unsigned int convst;
  534. unsigned int val;
  535. int ret = 0;
  536. mutex_lock(&xadc->mutex);
  537. if (state) {
  538. /* Only one of the two triggers can be active at a time. */
  539. if (xadc->trigger != NULL) {
  540. ret = -EBUSY;
  541. goto err_out;
  542. } else {
  543. xadc->trigger = trigger;
  544. if (trigger == xadc->convst_trigger)
  545. convst = XADC_CONF0_EC;
  546. else
  547. convst = 0;
  548. }
  549. ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
  550. convst);
  551. if (ret)
  552. goto err_out;
  553. } else {
  554. xadc->trigger = NULL;
  555. }
  556. spin_lock_irqsave(&xadc->lock, flags);
  557. xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
  558. xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
  559. if (state)
  560. val |= XADC_AXI_INT_EOS;
  561. else
  562. val &= ~XADC_AXI_INT_EOS;
  563. xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
  564. spin_unlock_irqrestore(&xadc->lock, flags);
  565. err_out:
  566. mutex_unlock(&xadc->mutex);
  567. return ret;
  568. }
  569. static const struct iio_trigger_ops xadc_trigger_ops = {
  570. .set_trigger_state = &xadc_trigger_set_state,
  571. };
  572. static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
  573. const char *name)
  574. {
  575. struct iio_trigger *trig;
  576. int ret;
  577. trig = iio_trigger_alloc("%s%d-%s", indio_dev->name,
  578. indio_dev->id, name);
  579. if (trig == NULL)
  580. return ERR_PTR(-ENOMEM);
  581. trig->dev.parent = indio_dev->dev.parent;
  582. trig->ops = &xadc_trigger_ops;
  583. iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
  584. ret = iio_trigger_register(trig);
  585. if (ret)
  586. goto error_free_trig;
  587. return trig;
  588. error_free_trig:
  589. iio_trigger_free(trig);
  590. return ERR_PTR(ret);
  591. }
  592. static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
  593. {
  594. uint16_t val;
  595. /* Powerdown the ADC-B when it is not needed. */
  596. switch (seq_mode) {
  597. case XADC_CONF1_SEQ_SIMULTANEOUS:
  598. case XADC_CONF1_SEQ_INDEPENDENT:
  599. val = 0;
  600. break;
  601. default:
  602. val = XADC_CONF2_PD_ADC_B;
  603. break;
  604. }
  605. return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
  606. val);
  607. }
  608. static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
  609. {
  610. unsigned int aux_scan_mode = scan_mode >> 16;
  611. if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
  612. return XADC_CONF1_SEQ_SIMULTANEOUS;
  613. if ((aux_scan_mode & 0xff00) == 0 ||
  614. (aux_scan_mode & 0x00ff) == 0)
  615. return XADC_CONF1_SEQ_CONTINUOUS;
  616. return XADC_CONF1_SEQ_SIMULTANEOUS;
  617. }
  618. static int xadc_postdisable(struct iio_dev *indio_dev)
  619. {
  620. struct xadc *xadc = iio_priv(indio_dev);
  621. unsigned long scan_mask;
  622. int ret;
  623. int i;
  624. scan_mask = 1; /* Run calibration as part of the sequence */
  625. for (i = 0; i < indio_dev->num_channels; i++)
  626. scan_mask |= BIT(indio_dev->channels[i].scan_index);
  627. /* Enable all channels and calibration */
  628. ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
  629. if (ret)
  630. return ret;
  631. ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
  632. if (ret)
  633. return ret;
  634. ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
  635. XADC_CONF1_SEQ_CONTINUOUS);
  636. if (ret)
  637. return ret;
  638. return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
  639. }
  640. static int xadc_preenable(struct iio_dev *indio_dev)
  641. {
  642. struct xadc *xadc = iio_priv(indio_dev);
  643. unsigned long scan_mask;
  644. int seq_mode;
  645. int ret;
  646. ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
  647. XADC_CONF1_SEQ_DEFAULT);
  648. if (ret)
  649. goto err;
  650. scan_mask = *indio_dev->active_scan_mask;
  651. seq_mode = xadc_get_seq_mode(xadc, scan_mask);
  652. ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
  653. if (ret)
  654. goto err;
  655. /*
  656. * In simultaneous mode the upper and lower aux channels are samples at
  657. * the same time. In this mode the upper 8 bits in the sequencer
  658. * register are don't care and the lower 8 bits control two channels
  659. * each. As such we must set the bit if either the channel in the lower
  660. * group or the upper group is enabled.
  661. */
  662. if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
  663. scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
  664. ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
  665. if (ret)
  666. goto err;
  667. ret = xadc_power_adc_b(xadc, seq_mode);
  668. if (ret)
  669. goto err;
  670. ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
  671. seq_mode);
  672. if (ret)
  673. goto err;
  674. return 0;
  675. err:
  676. xadc_postdisable(indio_dev);
  677. return ret;
  678. }
  679. static const struct iio_buffer_setup_ops xadc_buffer_ops = {
  680. .preenable = &xadc_preenable,
  681. .postdisable = &xadc_postdisable,
  682. };
  683. static int xadc_read_samplerate(struct xadc *xadc)
  684. {
  685. unsigned int div;
  686. uint16_t val16;
  687. int ret;
  688. ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
  689. if (ret)
  690. return ret;
  691. div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
  692. if (div < 2)
  693. div = 2;
  694. return xadc_get_dclk_rate(xadc) / div / 26;
  695. }
  696. static int xadc_read_raw(struct iio_dev *indio_dev,
  697. struct iio_chan_spec const *chan, int *val, int *val2, long info)
  698. {
  699. struct xadc *xadc = iio_priv(indio_dev);
  700. uint16_t val16;
  701. int ret;
  702. switch (info) {
  703. case IIO_CHAN_INFO_RAW:
  704. if (iio_buffer_enabled(indio_dev))
  705. return -EBUSY;
  706. ret = xadc_read_adc_reg(xadc, chan->address, &val16);
  707. if (ret < 0)
  708. return ret;
  709. val16 >>= 4;
  710. if (chan->scan_type.sign == 'u')
  711. *val = val16;
  712. else
  713. *val = sign_extend32(val16, 11);
  714. return IIO_VAL_INT;
  715. case IIO_CHAN_INFO_SCALE:
  716. switch (chan->type) {
  717. case IIO_VOLTAGE:
  718. /* V = (val * 3.0) / 4096 */
  719. switch (chan->address) {
  720. case XADC_REG_VCCINT:
  721. case XADC_REG_VCCAUX:
  722. case XADC_REG_VREFP:
  723. case XADC_REG_VREFN:
  724. case XADC_REG_VCCBRAM:
  725. case XADC_REG_VCCPINT:
  726. case XADC_REG_VCCPAUX:
  727. case XADC_REG_VCCO_DDR:
  728. *val = 3000;
  729. break;
  730. default:
  731. *val = 1000;
  732. break;
  733. }
  734. *val2 = 12;
  735. return IIO_VAL_FRACTIONAL_LOG2;
  736. case IIO_TEMP:
  737. /* Temp in C = (val * 503.975) / 4096 - 273.15 */
  738. *val = 503975;
  739. *val2 = 12;
  740. return IIO_VAL_FRACTIONAL_LOG2;
  741. default:
  742. return -EINVAL;
  743. }
  744. case IIO_CHAN_INFO_OFFSET:
  745. /* Only the temperature channel has an offset */
  746. *val = -((273150 << 12) / 503975);
  747. return IIO_VAL_INT;
  748. case IIO_CHAN_INFO_SAMP_FREQ:
  749. ret = xadc_read_samplerate(xadc);
  750. if (ret < 0)
  751. return ret;
  752. *val = ret;
  753. return IIO_VAL_INT;
  754. default:
  755. return -EINVAL;
  756. }
  757. }
  758. static int xadc_write_samplerate(struct xadc *xadc, int val)
  759. {
  760. unsigned long clk_rate = xadc_get_dclk_rate(xadc);
  761. unsigned int div;
  762. if (!clk_rate)
  763. return -EINVAL;
  764. if (val <= 0)
  765. return -EINVAL;
  766. /* Max. 150 kSPS */
  767. if (val > XADC_MAX_SAMPLERATE)
  768. val = XADC_MAX_SAMPLERATE;
  769. val *= 26;
  770. /* Min 1MHz */
  771. if (val < 1000000)
  772. val = 1000000;
  773. /*
  774. * We want to round down, but only if we do not exceed the 150 kSPS
  775. * limit.
  776. */
  777. div = clk_rate / val;
  778. if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
  779. div++;
  780. if (div < 2)
  781. div = 2;
  782. else if (div > 0xff)
  783. div = 0xff;
  784. return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
  785. div << XADC_CONF2_DIV_OFFSET);
  786. }
  787. static int xadc_write_raw(struct iio_dev *indio_dev,
  788. struct iio_chan_spec const *chan, int val, int val2, long info)
  789. {
  790. struct xadc *xadc = iio_priv(indio_dev);
  791. if (info != IIO_CHAN_INFO_SAMP_FREQ)
  792. return -EINVAL;
  793. return xadc_write_samplerate(xadc, val);
  794. }
  795. static const struct iio_event_spec xadc_temp_events[] = {
  796. {
  797. .type = IIO_EV_TYPE_THRESH,
  798. .dir = IIO_EV_DIR_RISING,
  799. .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
  800. BIT(IIO_EV_INFO_VALUE) |
  801. BIT(IIO_EV_INFO_HYSTERESIS),
  802. },
  803. };
  804. /* Separate values for upper and lower thresholds, but only a shared enabled */
  805. static const struct iio_event_spec xadc_voltage_events[] = {
  806. {
  807. .type = IIO_EV_TYPE_THRESH,
  808. .dir = IIO_EV_DIR_RISING,
  809. .mask_separate = BIT(IIO_EV_INFO_VALUE),
  810. }, {
  811. .type = IIO_EV_TYPE_THRESH,
  812. .dir = IIO_EV_DIR_FALLING,
  813. .mask_separate = BIT(IIO_EV_INFO_VALUE),
  814. }, {
  815. .type = IIO_EV_TYPE_THRESH,
  816. .dir = IIO_EV_DIR_EITHER,
  817. .mask_separate = BIT(IIO_EV_INFO_ENABLE),
  818. },
  819. };
  820. #define XADC_CHAN_TEMP(_chan, _scan_index, _addr) { \
  821. .type = IIO_TEMP, \
  822. .indexed = 1, \
  823. .channel = (_chan), \
  824. .address = (_addr), \
  825. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  826. BIT(IIO_CHAN_INFO_SCALE) | \
  827. BIT(IIO_CHAN_INFO_OFFSET), \
  828. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  829. .event_spec = xadc_temp_events, \
  830. .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
  831. .scan_index = (_scan_index), \
  832. .scan_type = { \
  833. .sign = 'u', \
  834. .realbits = 12, \
  835. .storagebits = 16, \
  836. .shift = 4, \
  837. .endianness = IIO_CPU, \
  838. }, \
  839. }
  840. #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) { \
  841. .type = IIO_VOLTAGE, \
  842. .indexed = 1, \
  843. .channel = (_chan), \
  844. .address = (_addr), \
  845. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  846. BIT(IIO_CHAN_INFO_SCALE), \
  847. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  848. .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
  849. .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
  850. .scan_index = (_scan_index), \
  851. .scan_type = { \
  852. .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
  853. .realbits = 12, \
  854. .storagebits = 16, \
  855. .shift = 4, \
  856. .endianness = IIO_CPU, \
  857. }, \
  858. .extend_name = _ext, \
  859. }
  860. static const struct iio_chan_spec xadc_channels[] = {
  861. XADC_CHAN_TEMP(0, 8, XADC_REG_TEMP),
  862. XADC_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
  863. XADC_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
  864. XADC_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
  865. XADC_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
  866. XADC_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
  867. XADC_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
  868. XADC_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
  869. XADC_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
  870. XADC_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
  871. XADC_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
  872. XADC_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
  873. XADC_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
  874. XADC_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
  875. XADC_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
  876. XADC_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
  877. XADC_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
  878. XADC_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
  879. XADC_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
  880. XADC_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
  881. XADC_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
  882. XADC_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
  883. XADC_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
  884. XADC_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
  885. XADC_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
  886. XADC_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
  887. };
  888. static const struct iio_info xadc_info = {
  889. .read_raw = &xadc_read_raw,
  890. .write_raw = &xadc_write_raw,
  891. .read_event_config = &xadc_read_event_config,
  892. .write_event_config = &xadc_write_event_config,
  893. .read_event_value = &xadc_read_event_value,
  894. .write_event_value = &xadc_write_event_value,
  895. .update_scan_mode = &xadc_update_scan_mode,
  896. };
  897. static const struct of_device_id xadc_of_match_table[] = {
  898. { .compatible = "xlnx,zynq-xadc-1.00.a", (void *)&xadc_zynq_ops },
  899. { .compatible = "xlnx,axi-xadc-1.00.a", (void *)&xadc_axi_ops },
  900. { },
  901. };
  902. MODULE_DEVICE_TABLE(of, xadc_of_match_table);
  903. static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
  904. unsigned int *conf)
  905. {
  906. struct device *dev = indio_dev->dev.parent;
  907. struct xadc *xadc = iio_priv(indio_dev);
  908. struct iio_chan_spec *channels, *chan;
  909. struct device_node *chan_node, *child;
  910. unsigned int num_channels;
  911. const char *external_mux;
  912. u32 ext_mux_chan;
  913. u32 reg;
  914. int ret;
  915. *conf = 0;
  916. ret = of_property_read_string(np, "xlnx,external-mux", &external_mux);
  917. if (ret < 0 || strcasecmp(external_mux, "none") == 0)
  918. xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
  919. else if (strcasecmp(external_mux, "single") == 0)
  920. xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
  921. else if (strcasecmp(external_mux, "dual") == 0)
  922. xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
  923. else
  924. return -EINVAL;
  925. if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
  926. ret = of_property_read_u32(np, "xlnx,external-mux-channel",
  927. &ext_mux_chan);
  928. if (ret < 0)
  929. return ret;
  930. if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
  931. if (ext_mux_chan == 0)
  932. ext_mux_chan = XADC_REG_VPVN;
  933. else if (ext_mux_chan <= 16)
  934. ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
  935. else
  936. return -EINVAL;
  937. } else {
  938. if (ext_mux_chan > 0 && ext_mux_chan <= 8)
  939. ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
  940. else
  941. return -EINVAL;
  942. }
  943. *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
  944. }
  945. channels = devm_kmemdup(dev, xadc_channels,
  946. sizeof(xadc_channels), GFP_KERNEL);
  947. if (!channels)
  948. return -ENOMEM;
  949. num_channels = 9;
  950. chan = &channels[9];
  951. chan_node = of_get_child_by_name(np, "xlnx,channels");
  952. if (chan_node) {
  953. for_each_child_of_node(chan_node, child) {
  954. if (num_channels >= ARRAY_SIZE(xadc_channels)) {
  955. of_node_put(child);
  956. break;
  957. }
  958. ret = of_property_read_u32(child, "reg", &reg);
  959. if (ret || reg > 16)
  960. continue;
  961. if (of_property_read_bool(child, "xlnx,bipolar"))
  962. chan->scan_type.sign = 's';
  963. if (reg == 0) {
  964. chan->scan_index = 11;
  965. chan->address = XADC_REG_VPVN;
  966. } else {
  967. chan->scan_index = 15 + reg;
  968. chan->address = XADC_REG_VAUX(reg - 1);
  969. }
  970. num_channels++;
  971. chan++;
  972. }
  973. }
  974. of_node_put(chan_node);
  975. indio_dev->num_channels = num_channels;
  976. indio_dev->channels = devm_krealloc(dev, channels,
  977. sizeof(*channels) * num_channels,
  978. GFP_KERNEL);
  979. /* If we can't resize the channels array, just use the original */
  980. if (!indio_dev->channels)
  981. indio_dev->channels = channels;
  982. return 0;
  983. }
  984. static int xadc_probe(struct platform_device *pdev)
  985. {
  986. const struct of_device_id *id;
  987. struct iio_dev *indio_dev;
  988. unsigned int bipolar_mask;
  989. unsigned int conf0;
  990. struct xadc *xadc;
  991. int ret;
  992. int irq;
  993. int i;
  994. if (!pdev->dev.of_node)
  995. return -ENODEV;
  996. id = of_match_node(xadc_of_match_table, pdev->dev.of_node);
  997. if (!id)
  998. return -EINVAL;
  999. irq = platform_get_irq(pdev, 0);
  1000. if (irq <= 0)
  1001. return -ENXIO;
  1002. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*xadc));
  1003. if (!indio_dev)
  1004. return -ENOMEM;
  1005. xadc = iio_priv(indio_dev);
  1006. xadc->ops = id->data;
  1007. xadc->irq = irq;
  1008. init_completion(&xadc->completion);
  1009. mutex_init(&xadc->mutex);
  1010. spin_lock_init(&xadc->lock);
  1011. INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
  1012. xadc->base = devm_platform_ioremap_resource(pdev, 0);
  1013. if (IS_ERR(xadc->base))
  1014. return PTR_ERR(xadc->base);
  1015. indio_dev->name = "xadc";
  1016. indio_dev->modes = INDIO_DIRECT_MODE;
  1017. indio_dev->info = &xadc_info;
  1018. ret = xadc_parse_dt(indio_dev, pdev->dev.of_node, &conf0);
  1019. if (ret)
  1020. return ret;
  1021. if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
  1022. ret = iio_triggered_buffer_setup(indio_dev,
  1023. &iio_pollfunc_store_time, &xadc_trigger_handler,
  1024. &xadc_buffer_ops);
  1025. if (ret)
  1026. return ret;
  1027. xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
  1028. if (IS_ERR(xadc->convst_trigger)) {
  1029. ret = PTR_ERR(xadc->convst_trigger);
  1030. goto err_triggered_buffer_cleanup;
  1031. }
  1032. xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
  1033. "samplerate");
  1034. if (IS_ERR(xadc->samplerate_trigger)) {
  1035. ret = PTR_ERR(xadc->samplerate_trigger);
  1036. goto err_free_convst_trigger;
  1037. }
  1038. }
  1039. xadc->clk = devm_clk_get(&pdev->dev, NULL);
  1040. if (IS_ERR(xadc->clk)) {
  1041. ret = PTR_ERR(xadc->clk);
  1042. goto err_free_samplerate_trigger;
  1043. }
  1044. ret = clk_prepare_enable(xadc->clk);
  1045. if (ret)
  1046. goto err_free_samplerate_trigger;
  1047. /*
  1048. * Make sure not to exceed the maximum samplerate since otherwise the
  1049. * resulting interrupt storm will soft-lock the system.
  1050. */
  1051. if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
  1052. ret = xadc_read_samplerate(xadc);
  1053. if (ret < 0)
  1054. goto err_free_samplerate_trigger;
  1055. if (ret > XADC_MAX_SAMPLERATE) {
  1056. ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
  1057. if (ret < 0)
  1058. goto err_free_samplerate_trigger;
  1059. }
  1060. }
  1061. ret = request_irq(xadc->irq, xadc->ops->interrupt_handler, 0,
  1062. dev_name(&pdev->dev), indio_dev);
  1063. if (ret)
  1064. goto err_clk_disable_unprepare;
  1065. ret = xadc->ops->setup(pdev, indio_dev, xadc->irq);
  1066. if (ret)
  1067. goto err_free_irq;
  1068. for (i = 0; i < 16; i++)
  1069. xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
  1070. &xadc->threshold[i]);
  1071. ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
  1072. if (ret)
  1073. goto err_free_irq;
  1074. bipolar_mask = 0;
  1075. for (i = 0; i < indio_dev->num_channels; i++) {
  1076. if (indio_dev->channels[i].scan_type.sign == 's')
  1077. bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
  1078. }
  1079. ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
  1080. if (ret)
  1081. goto err_free_irq;
  1082. ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
  1083. bipolar_mask >> 16);
  1084. if (ret)
  1085. goto err_free_irq;
  1086. /* Disable all alarms */
  1087. ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,
  1088. XADC_CONF1_ALARM_MASK);
  1089. if (ret)
  1090. goto err_free_irq;
  1091. /* Set thresholds to min/max */
  1092. for (i = 0; i < 16; i++) {
  1093. /*
  1094. * Set max voltage threshold and both temperature thresholds to
  1095. * 0xffff, min voltage threshold to 0.
  1096. */
  1097. if (i % 8 < 4 || i == 7)
  1098. xadc->threshold[i] = 0xffff;
  1099. else
  1100. xadc->threshold[i] = 0;
  1101. ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),
  1102. xadc->threshold[i]);
  1103. if (ret)
  1104. goto err_free_irq;
  1105. }
  1106. /* Go to non-buffered mode */
  1107. xadc_postdisable(indio_dev);
  1108. ret = iio_device_register(indio_dev);
  1109. if (ret)
  1110. goto err_free_irq;
  1111. platform_set_drvdata(pdev, indio_dev);
  1112. return 0;
  1113. err_free_irq:
  1114. free_irq(xadc->irq, indio_dev);
  1115. cancel_delayed_work_sync(&xadc->zynq_unmask_work);
  1116. err_clk_disable_unprepare:
  1117. clk_disable_unprepare(xadc->clk);
  1118. err_free_samplerate_trigger:
  1119. if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
  1120. iio_trigger_free(xadc->samplerate_trigger);
  1121. err_free_convst_trigger:
  1122. if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
  1123. iio_trigger_free(xadc->convst_trigger);
  1124. err_triggered_buffer_cleanup:
  1125. if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
  1126. iio_triggered_buffer_cleanup(indio_dev);
  1127. return ret;
  1128. }
  1129. static int xadc_remove(struct platform_device *pdev)
  1130. {
  1131. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  1132. struct xadc *xadc = iio_priv(indio_dev);
  1133. iio_device_unregister(indio_dev);
  1134. if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
  1135. iio_trigger_free(xadc->samplerate_trigger);
  1136. iio_trigger_free(xadc->convst_trigger);
  1137. iio_triggered_buffer_cleanup(indio_dev);
  1138. }
  1139. free_irq(xadc->irq, indio_dev);
  1140. cancel_delayed_work_sync(&xadc->zynq_unmask_work);
  1141. clk_disable_unprepare(xadc->clk);
  1142. kfree(xadc->data);
  1143. return 0;
  1144. }
  1145. static struct platform_driver xadc_driver = {
  1146. .probe = xadc_probe,
  1147. .remove = xadc_remove,
  1148. .driver = {
  1149. .name = "xadc",
  1150. .of_match_table = xadc_of_match_table,
  1151. },
  1152. };
  1153. module_platform_driver(xadc_driver);
  1154. MODULE_LICENSE("GPL v2");
  1155. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  1156. MODULE_DESCRIPTION("Xilinx XADC IIO driver");