vf610_adc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale Vybrid vf610 ADC driver
  4. *
  5. * Copyright 2013 Freescale Semiconductor, Inc.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/slab.h>
  13. #include <linux/io.h>
  14. #include <linux/clk.h>
  15. #include <linux/completion.h>
  16. #include <linux/of.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/err.h>
  21. #include <linux/iio/iio.h>
  22. #include <linux/iio/buffer.h>
  23. #include <linux/iio/sysfs.h>
  24. #include <linux/iio/trigger.h>
  25. #include <linux/iio/trigger_consumer.h>
  26. #include <linux/iio/triggered_buffer.h>
  27. /* This will be the driver name the kernel reports */
  28. #define DRIVER_NAME "vf610-adc"
  29. /* Vybrid/IMX ADC registers */
  30. #define VF610_REG_ADC_HC0 0x00
  31. #define VF610_REG_ADC_HC1 0x04
  32. #define VF610_REG_ADC_HS 0x08
  33. #define VF610_REG_ADC_R0 0x0c
  34. #define VF610_REG_ADC_R1 0x10
  35. #define VF610_REG_ADC_CFG 0x14
  36. #define VF610_REG_ADC_GC 0x18
  37. #define VF610_REG_ADC_GS 0x1c
  38. #define VF610_REG_ADC_CV 0x20
  39. #define VF610_REG_ADC_OFS 0x24
  40. #define VF610_REG_ADC_CAL 0x28
  41. #define VF610_REG_ADC_PCTL 0x30
  42. /* Configuration register field define */
  43. #define VF610_ADC_MODE_BIT8 0x00
  44. #define VF610_ADC_MODE_BIT10 0x04
  45. #define VF610_ADC_MODE_BIT12 0x08
  46. #define VF610_ADC_MODE_MASK 0x0c
  47. #define VF610_ADC_BUSCLK2_SEL 0x01
  48. #define VF610_ADC_ALTCLK_SEL 0x02
  49. #define VF610_ADC_ADACK_SEL 0x03
  50. #define VF610_ADC_ADCCLK_MASK 0x03
  51. #define VF610_ADC_CLK_DIV2 0x20
  52. #define VF610_ADC_CLK_DIV4 0x40
  53. #define VF610_ADC_CLK_DIV8 0x60
  54. #define VF610_ADC_CLK_MASK 0x60
  55. #define VF610_ADC_ADLSMP_LONG 0x10
  56. #define VF610_ADC_ADSTS_SHORT 0x100
  57. #define VF610_ADC_ADSTS_NORMAL 0x200
  58. #define VF610_ADC_ADSTS_LONG 0x300
  59. #define VF610_ADC_ADSTS_MASK 0x300
  60. #define VF610_ADC_ADLPC_EN 0x80
  61. #define VF610_ADC_ADHSC_EN 0x400
  62. #define VF610_ADC_REFSEL_VALT 0x800
  63. #define VF610_ADC_REFSEL_VBG 0x1000
  64. #define VF610_ADC_ADTRG_HARD 0x2000
  65. #define VF610_ADC_AVGS_8 0x4000
  66. #define VF610_ADC_AVGS_16 0x8000
  67. #define VF610_ADC_AVGS_32 0xC000
  68. #define VF610_ADC_AVGS_MASK 0xC000
  69. #define VF610_ADC_OVWREN 0x10000
  70. /* General control register field define */
  71. #define VF610_ADC_ADACKEN 0x1
  72. #define VF610_ADC_DMAEN 0x2
  73. #define VF610_ADC_ACREN 0x4
  74. #define VF610_ADC_ACFGT 0x8
  75. #define VF610_ADC_ACFE 0x10
  76. #define VF610_ADC_AVGEN 0x20
  77. #define VF610_ADC_ADCON 0x40
  78. #define VF610_ADC_CAL 0x80
  79. /* Other field define */
  80. #define VF610_ADC_ADCHC(x) ((x) & 0x1F)
  81. #define VF610_ADC_AIEN (0x1 << 7)
  82. #define VF610_ADC_CONV_DISABLE 0x1F
  83. #define VF610_ADC_HS_COCO0 0x1
  84. #define VF610_ADC_CALF 0x2
  85. #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
  86. #define DEFAULT_SAMPLE_TIME 1000
  87. /* V at 25°C of 696 mV */
  88. #define VF610_VTEMP25_3V0 950
  89. /* V at 25°C of 699 mV */
  90. #define VF610_VTEMP25_3V3 867
  91. /* Typical sensor slope coefficient at all temperatures */
  92. #define VF610_TEMP_SLOPE_COEFF 1840
  93. enum clk_sel {
  94. VF610_ADCIOC_BUSCLK_SET,
  95. VF610_ADCIOC_ALTCLK_SET,
  96. VF610_ADCIOC_ADACK_SET,
  97. };
  98. enum vol_ref {
  99. VF610_ADCIOC_VR_VREF_SET,
  100. VF610_ADCIOC_VR_VALT_SET,
  101. VF610_ADCIOC_VR_VBG_SET,
  102. };
  103. enum average_sel {
  104. VF610_ADC_SAMPLE_1,
  105. VF610_ADC_SAMPLE_4,
  106. VF610_ADC_SAMPLE_8,
  107. VF610_ADC_SAMPLE_16,
  108. VF610_ADC_SAMPLE_32,
  109. };
  110. enum conversion_mode_sel {
  111. VF610_ADC_CONV_NORMAL,
  112. VF610_ADC_CONV_HIGH_SPEED,
  113. VF610_ADC_CONV_LOW_POWER,
  114. };
  115. enum lst_adder_sel {
  116. VF610_ADCK_CYCLES_3,
  117. VF610_ADCK_CYCLES_5,
  118. VF610_ADCK_CYCLES_7,
  119. VF610_ADCK_CYCLES_9,
  120. VF610_ADCK_CYCLES_13,
  121. VF610_ADCK_CYCLES_17,
  122. VF610_ADCK_CYCLES_21,
  123. VF610_ADCK_CYCLES_25,
  124. };
  125. struct vf610_adc_feature {
  126. enum clk_sel clk_sel;
  127. enum vol_ref vol_ref;
  128. enum conversion_mode_sel conv_mode;
  129. int clk_div;
  130. int sample_rate;
  131. int res_mode;
  132. u32 lst_adder_index;
  133. u32 default_sample_time;
  134. bool calibration;
  135. bool ovwren;
  136. };
  137. struct vf610_adc {
  138. struct device *dev;
  139. void __iomem *regs;
  140. struct clk *clk;
  141. u32 vref_uv;
  142. u32 value;
  143. struct regulator *vref;
  144. u32 max_adck_rate[3];
  145. struct vf610_adc_feature adc_feature;
  146. u32 sample_freq_avail[5];
  147. struct completion completion;
  148. /* Ensure the timestamp is naturally aligned */
  149. struct {
  150. u16 chan;
  151. s64 timestamp __aligned(8);
  152. } scan;
  153. };
  154. static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
  155. static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
  156. static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
  157. {
  158. struct vf610_adc_feature *adc_feature = &info->adc_feature;
  159. unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
  160. u32 adck_period, lst_addr_min;
  161. int divisor, i;
  162. adck_rate = info->max_adck_rate[adc_feature->conv_mode];
  163. if (adck_rate) {
  164. /* calculate clk divider which is within specification */
  165. divisor = ipg_rate / adck_rate;
  166. adc_feature->clk_div = 1 << fls(divisor + 1);
  167. } else {
  168. /* fall-back value using a safe divisor */
  169. adc_feature->clk_div = 8;
  170. }
  171. adck_rate = ipg_rate / adc_feature->clk_div;
  172. /*
  173. * Determine the long sample time adder value to be used based
  174. * on the default minimum sample time provided.
  175. */
  176. adck_period = NSEC_PER_SEC / adck_rate;
  177. lst_addr_min = adc_feature->default_sample_time / adck_period;
  178. for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
  179. if (vf610_lst_adder[i] > lst_addr_min) {
  180. adc_feature->lst_adder_index = i;
  181. break;
  182. }
  183. }
  184. /*
  185. * Calculate ADC sample frequencies
  186. * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
  187. * which is the same as bus clock.
  188. *
  189. * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
  190. * SFCAdder: fixed to 6 ADCK cycles
  191. * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
  192. * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
  193. * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
  194. */
  195. for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
  196. info->sample_freq_avail[i] =
  197. adck_rate / (6 + vf610_hw_avgs[i] *
  198. (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
  199. }
  200. static inline void vf610_adc_cfg_init(struct vf610_adc *info)
  201. {
  202. struct vf610_adc_feature *adc_feature = &info->adc_feature;
  203. /* set default Configuration for ADC controller */
  204. adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
  205. adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
  206. adc_feature->calibration = true;
  207. adc_feature->ovwren = true;
  208. adc_feature->res_mode = 12;
  209. adc_feature->sample_rate = 1;
  210. adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
  211. vf610_adc_calculate_rates(info);
  212. }
  213. static void vf610_adc_cfg_post_set(struct vf610_adc *info)
  214. {
  215. struct vf610_adc_feature *adc_feature = &info->adc_feature;
  216. int cfg_data = 0;
  217. int gc_data = 0;
  218. switch (adc_feature->clk_sel) {
  219. case VF610_ADCIOC_ALTCLK_SET:
  220. cfg_data |= VF610_ADC_ALTCLK_SEL;
  221. break;
  222. case VF610_ADCIOC_ADACK_SET:
  223. cfg_data |= VF610_ADC_ADACK_SEL;
  224. break;
  225. default:
  226. break;
  227. }
  228. /* low power set for calibration */
  229. cfg_data |= VF610_ADC_ADLPC_EN;
  230. /* enable high speed for calibration */
  231. cfg_data |= VF610_ADC_ADHSC_EN;
  232. /* voltage reference */
  233. switch (adc_feature->vol_ref) {
  234. case VF610_ADCIOC_VR_VREF_SET:
  235. break;
  236. case VF610_ADCIOC_VR_VALT_SET:
  237. cfg_data |= VF610_ADC_REFSEL_VALT;
  238. break;
  239. case VF610_ADCIOC_VR_VBG_SET:
  240. cfg_data |= VF610_ADC_REFSEL_VBG;
  241. break;
  242. default:
  243. dev_err(info->dev, "error voltage reference\n");
  244. }
  245. /* data overwrite enable */
  246. if (adc_feature->ovwren)
  247. cfg_data |= VF610_ADC_OVWREN;
  248. writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
  249. writel(gc_data, info->regs + VF610_REG_ADC_GC);
  250. }
  251. static void vf610_adc_calibration(struct vf610_adc *info)
  252. {
  253. int adc_gc, hc_cfg;
  254. if (!info->adc_feature.calibration)
  255. return;
  256. /* enable calibration interrupt */
  257. hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
  258. writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
  259. adc_gc = readl(info->regs + VF610_REG_ADC_GC);
  260. writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
  261. if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
  262. dev_err(info->dev, "Timeout for adc calibration\n");
  263. adc_gc = readl(info->regs + VF610_REG_ADC_GS);
  264. if (adc_gc & VF610_ADC_CALF)
  265. dev_err(info->dev, "ADC calibration failed\n");
  266. info->adc_feature.calibration = false;
  267. }
  268. static void vf610_adc_cfg_set(struct vf610_adc *info)
  269. {
  270. struct vf610_adc_feature *adc_feature = &(info->adc_feature);
  271. int cfg_data;
  272. cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
  273. cfg_data &= ~VF610_ADC_ADLPC_EN;
  274. if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
  275. cfg_data |= VF610_ADC_ADLPC_EN;
  276. cfg_data &= ~VF610_ADC_ADHSC_EN;
  277. if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
  278. cfg_data |= VF610_ADC_ADHSC_EN;
  279. writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
  280. }
  281. static void vf610_adc_sample_set(struct vf610_adc *info)
  282. {
  283. struct vf610_adc_feature *adc_feature = &(info->adc_feature);
  284. int cfg_data, gc_data;
  285. cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
  286. gc_data = readl(info->regs + VF610_REG_ADC_GC);
  287. /* resolution mode */
  288. cfg_data &= ~VF610_ADC_MODE_MASK;
  289. switch (adc_feature->res_mode) {
  290. case 8:
  291. cfg_data |= VF610_ADC_MODE_BIT8;
  292. break;
  293. case 10:
  294. cfg_data |= VF610_ADC_MODE_BIT10;
  295. break;
  296. case 12:
  297. cfg_data |= VF610_ADC_MODE_BIT12;
  298. break;
  299. default:
  300. dev_err(info->dev, "error resolution mode\n");
  301. break;
  302. }
  303. /* clock select and clock divider */
  304. cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
  305. switch (adc_feature->clk_div) {
  306. case 1:
  307. break;
  308. case 2:
  309. cfg_data |= VF610_ADC_CLK_DIV2;
  310. break;
  311. case 4:
  312. cfg_data |= VF610_ADC_CLK_DIV4;
  313. break;
  314. case 8:
  315. cfg_data |= VF610_ADC_CLK_DIV8;
  316. break;
  317. case 16:
  318. switch (adc_feature->clk_sel) {
  319. case VF610_ADCIOC_BUSCLK_SET:
  320. cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
  321. break;
  322. default:
  323. dev_err(info->dev, "error clk divider\n");
  324. break;
  325. }
  326. break;
  327. }
  328. /*
  329. * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
  330. * determined.
  331. */
  332. switch (adc_feature->lst_adder_index) {
  333. case VF610_ADCK_CYCLES_3:
  334. break;
  335. case VF610_ADCK_CYCLES_5:
  336. cfg_data |= VF610_ADC_ADSTS_SHORT;
  337. break;
  338. case VF610_ADCK_CYCLES_7:
  339. cfg_data |= VF610_ADC_ADSTS_NORMAL;
  340. break;
  341. case VF610_ADCK_CYCLES_9:
  342. cfg_data |= VF610_ADC_ADSTS_LONG;
  343. break;
  344. case VF610_ADCK_CYCLES_13:
  345. cfg_data |= VF610_ADC_ADLSMP_LONG;
  346. break;
  347. case VF610_ADCK_CYCLES_17:
  348. cfg_data |= VF610_ADC_ADLSMP_LONG;
  349. cfg_data |= VF610_ADC_ADSTS_SHORT;
  350. break;
  351. case VF610_ADCK_CYCLES_21:
  352. cfg_data |= VF610_ADC_ADLSMP_LONG;
  353. cfg_data |= VF610_ADC_ADSTS_NORMAL;
  354. break;
  355. case VF610_ADCK_CYCLES_25:
  356. cfg_data |= VF610_ADC_ADLSMP_LONG;
  357. cfg_data |= VF610_ADC_ADSTS_NORMAL;
  358. break;
  359. default:
  360. dev_err(info->dev, "error in sample time select\n");
  361. }
  362. /* update hardware average selection */
  363. cfg_data &= ~VF610_ADC_AVGS_MASK;
  364. gc_data &= ~VF610_ADC_AVGEN;
  365. switch (adc_feature->sample_rate) {
  366. case VF610_ADC_SAMPLE_1:
  367. break;
  368. case VF610_ADC_SAMPLE_4:
  369. gc_data |= VF610_ADC_AVGEN;
  370. break;
  371. case VF610_ADC_SAMPLE_8:
  372. gc_data |= VF610_ADC_AVGEN;
  373. cfg_data |= VF610_ADC_AVGS_8;
  374. break;
  375. case VF610_ADC_SAMPLE_16:
  376. gc_data |= VF610_ADC_AVGEN;
  377. cfg_data |= VF610_ADC_AVGS_16;
  378. break;
  379. case VF610_ADC_SAMPLE_32:
  380. gc_data |= VF610_ADC_AVGEN;
  381. cfg_data |= VF610_ADC_AVGS_32;
  382. break;
  383. default:
  384. dev_err(info->dev,
  385. "error hardware sample average select\n");
  386. }
  387. writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
  388. writel(gc_data, info->regs + VF610_REG_ADC_GC);
  389. }
  390. static void vf610_adc_hw_init(struct vf610_adc *info)
  391. {
  392. /* CFG: Feature set */
  393. vf610_adc_cfg_post_set(info);
  394. vf610_adc_sample_set(info);
  395. /* adc calibration */
  396. vf610_adc_calibration(info);
  397. /* CFG: power and speed set */
  398. vf610_adc_cfg_set(info);
  399. }
  400. static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
  401. const struct iio_chan_spec *chan,
  402. unsigned int mode)
  403. {
  404. struct vf610_adc *info = iio_priv(indio_dev);
  405. mutex_lock(&indio_dev->mlock);
  406. info->adc_feature.conv_mode = mode;
  407. vf610_adc_calculate_rates(info);
  408. vf610_adc_hw_init(info);
  409. mutex_unlock(&indio_dev->mlock);
  410. return 0;
  411. }
  412. static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
  413. const struct iio_chan_spec *chan)
  414. {
  415. struct vf610_adc *info = iio_priv(indio_dev);
  416. return info->adc_feature.conv_mode;
  417. }
  418. static const char * const vf610_conv_modes[] = { "normal", "high-speed",
  419. "low-power" };
  420. static const struct iio_enum vf610_conversion_mode = {
  421. .items = vf610_conv_modes,
  422. .num_items = ARRAY_SIZE(vf610_conv_modes),
  423. .get = vf610_get_conversion_mode,
  424. .set = vf610_set_conversion_mode,
  425. };
  426. static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
  427. IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
  428. {},
  429. };
  430. #define VF610_ADC_CHAN(_idx, _chan_type) { \
  431. .type = (_chan_type), \
  432. .indexed = 1, \
  433. .channel = (_idx), \
  434. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  435. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  436. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  437. .ext_info = vf610_ext_info, \
  438. .scan_index = (_idx), \
  439. .scan_type = { \
  440. .sign = 'u', \
  441. .realbits = 12, \
  442. .storagebits = 16, \
  443. }, \
  444. }
  445. #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
  446. .type = (_chan_type), \
  447. .channel = (_idx), \
  448. .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
  449. .scan_index = (_idx), \
  450. .scan_type = { \
  451. .sign = 'u', \
  452. .realbits = 12, \
  453. .storagebits = 16, \
  454. }, \
  455. }
  456. static const struct iio_chan_spec vf610_adc_iio_channels[] = {
  457. VF610_ADC_CHAN(0, IIO_VOLTAGE),
  458. VF610_ADC_CHAN(1, IIO_VOLTAGE),
  459. VF610_ADC_CHAN(2, IIO_VOLTAGE),
  460. VF610_ADC_CHAN(3, IIO_VOLTAGE),
  461. VF610_ADC_CHAN(4, IIO_VOLTAGE),
  462. VF610_ADC_CHAN(5, IIO_VOLTAGE),
  463. VF610_ADC_CHAN(6, IIO_VOLTAGE),
  464. VF610_ADC_CHAN(7, IIO_VOLTAGE),
  465. VF610_ADC_CHAN(8, IIO_VOLTAGE),
  466. VF610_ADC_CHAN(9, IIO_VOLTAGE),
  467. VF610_ADC_CHAN(10, IIO_VOLTAGE),
  468. VF610_ADC_CHAN(11, IIO_VOLTAGE),
  469. VF610_ADC_CHAN(12, IIO_VOLTAGE),
  470. VF610_ADC_CHAN(13, IIO_VOLTAGE),
  471. VF610_ADC_CHAN(14, IIO_VOLTAGE),
  472. VF610_ADC_CHAN(15, IIO_VOLTAGE),
  473. VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
  474. IIO_CHAN_SOFT_TIMESTAMP(32),
  475. /* sentinel */
  476. };
  477. static int vf610_adc_read_data(struct vf610_adc *info)
  478. {
  479. int result;
  480. result = readl(info->regs + VF610_REG_ADC_R0);
  481. switch (info->adc_feature.res_mode) {
  482. case 8:
  483. result &= 0xFF;
  484. break;
  485. case 10:
  486. result &= 0x3FF;
  487. break;
  488. case 12:
  489. result &= 0xFFF;
  490. break;
  491. default:
  492. break;
  493. }
  494. return result;
  495. }
  496. static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
  497. {
  498. struct iio_dev *indio_dev = dev_id;
  499. struct vf610_adc *info = iio_priv(indio_dev);
  500. int coco;
  501. coco = readl(info->regs + VF610_REG_ADC_HS);
  502. if (coco & VF610_ADC_HS_COCO0) {
  503. info->value = vf610_adc_read_data(info);
  504. if (iio_buffer_enabled(indio_dev)) {
  505. info->scan.chan = info->value;
  506. iio_push_to_buffers_with_timestamp(indio_dev,
  507. &info->scan,
  508. iio_get_time_ns(indio_dev));
  509. iio_trigger_notify_done(indio_dev->trig);
  510. } else
  511. complete(&info->completion);
  512. }
  513. return IRQ_HANDLED;
  514. }
  515. static ssize_t vf610_show_samp_freq_avail(struct device *dev,
  516. struct device_attribute *attr, char *buf)
  517. {
  518. struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
  519. size_t len = 0;
  520. int i;
  521. for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
  522. len += scnprintf(buf + len, PAGE_SIZE - len,
  523. "%u ", info->sample_freq_avail[i]);
  524. /* replace trailing space by newline */
  525. buf[len - 1] = '\n';
  526. return len;
  527. }
  528. static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
  529. static struct attribute *vf610_attributes[] = {
  530. &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
  531. NULL
  532. };
  533. static const struct attribute_group vf610_attribute_group = {
  534. .attrs = vf610_attributes,
  535. };
  536. static int vf610_read_raw(struct iio_dev *indio_dev,
  537. struct iio_chan_spec const *chan,
  538. int *val,
  539. int *val2,
  540. long mask)
  541. {
  542. struct vf610_adc *info = iio_priv(indio_dev);
  543. unsigned int hc_cfg;
  544. long ret;
  545. switch (mask) {
  546. case IIO_CHAN_INFO_RAW:
  547. case IIO_CHAN_INFO_PROCESSED:
  548. mutex_lock(&indio_dev->mlock);
  549. if (iio_buffer_enabled(indio_dev)) {
  550. mutex_unlock(&indio_dev->mlock);
  551. return -EBUSY;
  552. }
  553. reinit_completion(&info->completion);
  554. hc_cfg = VF610_ADC_ADCHC(chan->channel);
  555. hc_cfg |= VF610_ADC_AIEN;
  556. writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
  557. ret = wait_for_completion_interruptible_timeout
  558. (&info->completion, VF610_ADC_TIMEOUT);
  559. if (ret == 0) {
  560. mutex_unlock(&indio_dev->mlock);
  561. return -ETIMEDOUT;
  562. }
  563. if (ret < 0) {
  564. mutex_unlock(&indio_dev->mlock);
  565. return ret;
  566. }
  567. switch (chan->type) {
  568. case IIO_VOLTAGE:
  569. *val = info->value;
  570. break;
  571. case IIO_TEMP:
  572. /*
  573. * Calculate in degree Celsius times 1000
  574. * Using the typical sensor slope of 1.84 mV/°C
  575. * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
  576. */
  577. *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
  578. 1000000 / VF610_TEMP_SLOPE_COEFF;
  579. break;
  580. default:
  581. mutex_unlock(&indio_dev->mlock);
  582. return -EINVAL;
  583. }
  584. mutex_unlock(&indio_dev->mlock);
  585. return IIO_VAL_INT;
  586. case IIO_CHAN_INFO_SCALE:
  587. *val = info->vref_uv / 1000;
  588. *val2 = info->adc_feature.res_mode;
  589. return IIO_VAL_FRACTIONAL_LOG2;
  590. case IIO_CHAN_INFO_SAMP_FREQ:
  591. *val = info->sample_freq_avail[info->adc_feature.sample_rate];
  592. *val2 = 0;
  593. return IIO_VAL_INT;
  594. default:
  595. break;
  596. }
  597. return -EINVAL;
  598. }
  599. static int vf610_write_raw(struct iio_dev *indio_dev,
  600. struct iio_chan_spec const *chan,
  601. int val,
  602. int val2,
  603. long mask)
  604. {
  605. struct vf610_adc *info = iio_priv(indio_dev);
  606. int i;
  607. switch (mask) {
  608. case IIO_CHAN_INFO_SAMP_FREQ:
  609. for (i = 0;
  610. i < ARRAY_SIZE(info->sample_freq_avail);
  611. i++)
  612. if (val == info->sample_freq_avail[i]) {
  613. info->adc_feature.sample_rate = i;
  614. vf610_adc_sample_set(info);
  615. return 0;
  616. }
  617. break;
  618. default:
  619. break;
  620. }
  621. return -EINVAL;
  622. }
  623. static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
  624. {
  625. struct vf610_adc *info = iio_priv(indio_dev);
  626. unsigned int channel;
  627. int val;
  628. val = readl(info->regs + VF610_REG_ADC_GC);
  629. val |= VF610_ADC_ADCON;
  630. writel(val, info->regs + VF610_REG_ADC_GC);
  631. channel = find_first_bit(indio_dev->active_scan_mask,
  632. indio_dev->masklength);
  633. val = VF610_ADC_ADCHC(channel);
  634. val |= VF610_ADC_AIEN;
  635. writel(val, info->regs + VF610_REG_ADC_HC0);
  636. return 0;
  637. }
  638. static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
  639. {
  640. struct vf610_adc *info = iio_priv(indio_dev);
  641. unsigned int hc_cfg = 0;
  642. int val;
  643. val = readl(info->regs + VF610_REG_ADC_GC);
  644. val &= ~VF610_ADC_ADCON;
  645. writel(val, info->regs + VF610_REG_ADC_GC);
  646. hc_cfg |= VF610_ADC_CONV_DISABLE;
  647. hc_cfg &= ~VF610_ADC_AIEN;
  648. writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
  649. return 0;
  650. }
  651. static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
  652. .postenable = &vf610_adc_buffer_postenable,
  653. .predisable = &vf610_adc_buffer_predisable,
  654. .validate_scan_mask = &iio_validate_scan_mask_onehot,
  655. };
  656. static int vf610_adc_reg_access(struct iio_dev *indio_dev,
  657. unsigned reg, unsigned writeval,
  658. unsigned *readval)
  659. {
  660. struct vf610_adc *info = iio_priv(indio_dev);
  661. if ((readval == NULL) ||
  662. ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
  663. return -EINVAL;
  664. *readval = readl(info->regs + reg);
  665. return 0;
  666. }
  667. static const struct iio_info vf610_adc_iio_info = {
  668. .read_raw = &vf610_read_raw,
  669. .write_raw = &vf610_write_raw,
  670. .debugfs_reg_access = &vf610_adc_reg_access,
  671. .attrs = &vf610_attribute_group,
  672. };
  673. static const struct of_device_id vf610_adc_match[] = {
  674. { .compatible = "fsl,vf610-adc", },
  675. { /* sentinel */ }
  676. };
  677. MODULE_DEVICE_TABLE(of, vf610_adc_match);
  678. static int vf610_adc_probe(struct platform_device *pdev)
  679. {
  680. struct vf610_adc *info;
  681. struct iio_dev *indio_dev;
  682. int irq;
  683. int ret;
  684. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
  685. if (!indio_dev) {
  686. dev_err(&pdev->dev, "Failed allocating iio device\n");
  687. return -ENOMEM;
  688. }
  689. info = iio_priv(indio_dev);
  690. info->dev = &pdev->dev;
  691. info->regs = devm_platform_ioremap_resource(pdev, 0);
  692. if (IS_ERR(info->regs))
  693. return PTR_ERR(info->regs);
  694. irq = platform_get_irq(pdev, 0);
  695. if (irq < 0)
  696. return irq;
  697. ret = devm_request_irq(info->dev, irq,
  698. vf610_adc_isr, 0,
  699. dev_name(&pdev->dev), indio_dev);
  700. if (ret < 0) {
  701. dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
  702. return ret;
  703. }
  704. info->clk = devm_clk_get(&pdev->dev, "adc");
  705. if (IS_ERR(info->clk)) {
  706. dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
  707. PTR_ERR(info->clk));
  708. return PTR_ERR(info->clk);
  709. }
  710. info->vref = devm_regulator_get(&pdev->dev, "vref");
  711. if (IS_ERR(info->vref))
  712. return PTR_ERR(info->vref);
  713. ret = regulator_enable(info->vref);
  714. if (ret)
  715. return ret;
  716. info->vref_uv = regulator_get_voltage(info->vref);
  717. of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
  718. info->max_adck_rate, 3);
  719. ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
  720. &info->adc_feature.default_sample_time);
  721. if (ret)
  722. info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
  723. platform_set_drvdata(pdev, indio_dev);
  724. init_completion(&info->completion);
  725. indio_dev->name = dev_name(&pdev->dev);
  726. indio_dev->info = &vf610_adc_iio_info;
  727. indio_dev->modes = INDIO_DIRECT_MODE;
  728. indio_dev->channels = vf610_adc_iio_channels;
  729. indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
  730. ret = clk_prepare_enable(info->clk);
  731. if (ret) {
  732. dev_err(&pdev->dev,
  733. "Could not prepare or enable the clock.\n");
  734. goto error_adc_clk_enable;
  735. }
  736. vf610_adc_cfg_init(info);
  737. vf610_adc_hw_init(info);
  738. ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
  739. NULL, &iio_triggered_buffer_setup_ops);
  740. if (ret < 0) {
  741. dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
  742. goto error_iio_device_register;
  743. }
  744. ret = iio_device_register(indio_dev);
  745. if (ret) {
  746. dev_err(&pdev->dev, "Couldn't register the device.\n");
  747. goto error_adc_buffer_init;
  748. }
  749. return 0;
  750. error_adc_buffer_init:
  751. iio_triggered_buffer_cleanup(indio_dev);
  752. error_iio_device_register:
  753. clk_disable_unprepare(info->clk);
  754. error_adc_clk_enable:
  755. regulator_disable(info->vref);
  756. return ret;
  757. }
  758. static int vf610_adc_remove(struct platform_device *pdev)
  759. {
  760. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  761. struct vf610_adc *info = iio_priv(indio_dev);
  762. iio_device_unregister(indio_dev);
  763. iio_triggered_buffer_cleanup(indio_dev);
  764. regulator_disable(info->vref);
  765. clk_disable_unprepare(info->clk);
  766. return 0;
  767. }
  768. #ifdef CONFIG_PM_SLEEP
  769. static int vf610_adc_suspend(struct device *dev)
  770. {
  771. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  772. struct vf610_adc *info = iio_priv(indio_dev);
  773. int hc_cfg;
  774. /* ADC controller enters to stop mode */
  775. hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
  776. hc_cfg |= VF610_ADC_CONV_DISABLE;
  777. writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
  778. clk_disable_unprepare(info->clk);
  779. regulator_disable(info->vref);
  780. return 0;
  781. }
  782. static int vf610_adc_resume(struct device *dev)
  783. {
  784. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  785. struct vf610_adc *info = iio_priv(indio_dev);
  786. int ret;
  787. ret = regulator_enable(info->vref);
  788. if (ret)
  789. return ret;
  790. ret = clk_prepare_enable(info->clk);
  791. if (ret)
  792. goto disable_reg;
  793. vf610_adc_hw_init(info);
  794. return 0;
  795. disable_reg:
  796. regulator_disable(info->vref);
  797. return ret;
  798. }
  799. #endif
  800. static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
  801. static struct platform_driver vf610_adc_driver = {
  802. .probe = vf610_adc_probe,
  803. .remove = vf610_adc_remove,
  804. .driver = {
  805. .name = DRIVER_NAME,
  806. .of_match_table = vf610_adc_match,
  807. .pm = &vf610_adc_pm_ops,
  808. },
  809. };
  810. module_platform_driver(vf610_adc_driver);
  811. MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
  812. MODULE_DESCRIPTION("Freescale VF610 ADC driver");
  813. MODULE_LICENSE("GPL v2");