ti_am335x_adc.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727
  1. /*
  2. * TI ADC MFD driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/err.h>
  17. #include <linux/module.h>
  18. #include <linux/slab.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <linux/iio/iio.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. #include <linux/iio/machine.h>
  26. #include <linux/iio/driver.h>
  27. #include <linux/mfd/ti_am335x_tscadc.h>
  28. #include <linux/iio/buffer.h>
  29. #include <linux/iio/kfifo_buf.h>
  30. #include <linux/dmaengine.h>
  31. #include <linux/dma-mapping.h>
  32. #define DMA_BUFFER_SIZE SZ_2K
  33. struct tiadc_dma {
  34. struct dma_slave_config conf;
  35. struct dma_chan *chan;
  36. dma_addr_t addr;
  37. dma_cookie_t cookie;
  38. u8 *buf;
  39. int current_period;
  40. int period_size;
  41. u8 fifo_thresh;
  42. };
  43. struct tiadc_device {
  44. struct ti_tscadc_dev *mfd_tscadc;
  45. struct tiadc_dma dma;
  46. struct mutex fifo1_lock; /* to protect fifo access */
  47. int channels;
  48. int total_ch_enabled;
  49. u8 channel_line[8];
  50. u8 channel_step[8];
  51. int buffer_en_ch_steps;
  52. u16 data[8];
  53. u32 open_delay[8], sample_delay[8], step_avg[8];
  54. };
  55. static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg)
  56. {
  57. return readl(adc->mfd_tscadc->tscadc_base + reg);
  58. }
  59. static void tiadc_writel(struct tiadc_device *adc, unsigned int reg,
  60. unsigned int val)
  61. {
  62. writel(val, adc->mfd_tscadc->tscadc_base + reg);
  63. }
  64. static u32 get_adc_step_mask(struct tiadc_device *adc_dev)
  65. {
  66. u32 step_en;
  67. step_en = ((1 << adc_dev->channels) - 1);
  68. step_en <<= TOTAL_STEPS - adc_dev->channels + 1;
  69. return step_en;
  70. }
  71. static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev,
  72. struct iio_chan_spec const *chan)
  73. {
  74. int i;
  75. for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) {
  76. if (chan->channel == adc_dev->channel_line[i]) {
  77. u32 step;
  78. step = adc_dev->channel_step[i];
  79. /* +1 for the charger */
  80. return 1 << (step + 1);
  81. }
  82. }
  83. WARN_ON(1);
  84. return 0;
  85. }
  86. static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan)
  87. {
  88. return 1 << adc_dev->channel_step[chan];
  89. }
  90. static void tiadc_step_config(struct iio_dev *indio_dev)
  91. {
  92. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  93. struct device *dev = adc_dev->mfd_tscadc->dev;
  94. unsigned int stepconfig;
  95. int i, steps = 0;
  96. /*
  97. * There are 16 configurable steps and 8 analog input
  98. * lines available which are shared between Touchscreen and ADC.
  99. *
  100. * Steps forwards i.e. from 0 towards 16 are used by ADC
  101. * depending on number of input lines needed.
  102. * Channel would represent which analog input
  103. * needs to be given to ADC to digitalize data.
  104. */
  105. for (i = 0; i < adc_dev->channels; i++) {
  106. int chan;
  107. chan = adc_dev->channel_line[i];
  108. if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) {
  109. dev_warn(dev, "chan %d step_avg truncating to %d\n",
  110. chan, STEPCONFIG_AVG_16);
  111. adc_dev->step_avg[i] = STEPCONFIG_AVG_16;
  112. }
  113. if (adc_dev->step_avg[i])
  114. stepconfig =
  115. STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) |
  116. STEPCONFIG_FIFO1;
  117. else
  118. stepconfig = STEPCONFIG_FIFO1;
  119. if (iio_buffer_enabled(indio_dev))
  120. stepconfig |= STEPCONFIG_MODE_SWCNT;
  121. tiadc_writel(adc_dev, REG_STEPCONFIG(steps),
  122. stepconfig | STEPCONFIG_INP(chan) |
  123. STEPCONFIG_INM_ADCREFM |
  124. STEPCONFIG_RFP_VREFP |
  125. STEPCONFIG_RFM_VREFN);
  126. if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) {
  127. dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n",
  128. chan);
  129. adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK;
  130. }
  131. if (adc_dev->sample_delay[i] > 0xFF) {
  132. dev_warn(dev, "chan %d sample delay truncating to 0xFF\n",
  133. chan);
  134. adc_dev->sample_delay[i] = 0xFF;
  135. }
  136. tiadc_writel(adc_dev, REG_STEPDELAY(steps),
  137. STEPDELAY_OPEN(adc_dev->open_delay[i]) |
  138. STEPDELAY_SAMPLE(adc_dev->sample_delay[i]));
  139. adc_dev->channel_step[i] = steps;
  140. steps++;
  141. }
  142. }
  143. static irqreturn_t tiadc_irq_h(int irq, void *private)
  144. {
  145. struct iio_dev *indio_dev = private;
  146. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  147. unsigned int status, config, adc_fsm;
  148. unsigned short count = 0;
  149. status = tiadc_readl(adc_dev, REG_IRQSTATUS);
  150. /*
  151. * ADC and touchscreen share the IRQ line.
  152. * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only
  153. */
  154. if (status & IRQENB_FIFO1OVRRUN) {
  155. /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */
  156. config = tiadc_readl(adc_dev, REG_CTRL);
  157. config &= ~(CNTRLREG_TSCSSENB);
  158. tiadc_writel(adc_dev, REG_CTRL, config);
  159. tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN
  160. | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES);
  161. /* wait for idle state.
  162. * ADC needs to finish the current conversion
  163. * before disabling the module
  164. */
  165. do {
  166. adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM);
  167. } while (adc_fsm != 0x10 && count++ < 100);
  168. tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB));
  169. return IRQ_HANDLED;
  170. } else if (status & IRQENB_FIFO1THRES) {
  171. /* Disable irq and wake worker thread */
  172. tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES);
  173. return IRQ_WAKE_THREAD;
  174. }
  175. return IRQ_NONE;
  176. }
  177. static irqreturn_t tiadc_worker_h(int irq, void *private)
  178. {
  179. struct iio_dev *indio_dev = private;
  180. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  181. int i, k, fifo1count, read;
  182. u16 *data = adc_dev->data;
  183. fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
  184. for (k = 0; k < fifo1count; k = k + i) {
  185. for (i = 0; i < (indio_dev->scan_bytes)/2; i++) {
  186. read = tiadc_readl(adc_dev, REG_FIFO1);
  187. data[i] = read & FIFOREAD_DATA_MASK;
  188. }
  189. iio_push_to_buffers(indio_dev, (u8 *) data);
  190. }
  191. tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES);
  192. tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES);
  193. return IRQ_HANDLED;
  194. }
  195. static void tiadc_dma_rx_complete(void *param)
  196. {
  197. struct iio_dev *indio_dev = param;
  198. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  199. struct tiadc_dma *dma = &adc_dev->dma;
  200. u8 *data;
  201. int i;
  202. data = dma->buf + dma->current_period * dma->period_size;
  203. dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
  204. for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
  205. iio_push_to_buffers(indio_dev, data);
  206. data += indio_dev->scan_bytes;
  207. }
  208. }
  209. static int tiadc_start_dma(struct iio_dev *indio_dev)
  210. {
  211. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  212. struct tiadc_dma *dma = &adc_dev->dma;
  213. struct dma_async_tx_descriptor *desc;
  214. dma->current_period = 0; /* We start to fill period 0 */
  215. /*
  216. * Make the fifo thresh as the multiple of total number of
  217. * channels enabled, so make sure that cyclic DMA period
  218. * length is also a multiple of total number of channels
  219. * enabled. This ensures that no invalid data is reported
  220. * to the stack via iio_push_to_buffers().
  221. */
  222. dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
  223. adc_dev->total_ch_enabled) - 1;
  224. /* Make sure that period length is multiple of fifo thresh level */
  225. dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
  226. (dma->fifo_thresh + 1) * sizeof(u16));
  227. dma->conf.src_maxburst = dma->fifo_thresh + 1;
  228. dmaengine_slave_config(dma->chan, &dma->conf);
  229. desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
  230. dma->period_size * 2,
  231. dma->period_size, DMA_DEV_TO_MEM,
  232. DMA_PREP_INTERRUPT);
  233. if (!desc)
  234. return -EBUSY;
  235. desc->callback = tiadc_dma_rx_complete;
  236. desc->callback_param = indio_dev;
  237. dma->cookie = dmaengine_submit(desc);
  238. dma_async_issue_pending(dma->chan);
  239. tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
  240. tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
  241. tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
  242. return 0;
  243. }
  244. static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
  245. {
  246. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  247. int i, fifo1count;
  248. tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
  249. IRQENB_FIFO1OVRRUN |
  250. IRQENB_FIFO1UNDRFLW));
  251. /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */
  252. fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
  253. for (i = 0; i < fifo1count; i++)
  254. tiadc_readl(adc_dev, REG_FIFO1);
  255. return 0;
  256. }
  257. static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
  258. {
  259. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  260. struct tiadc_dma *dma = &adc_dev->dma;
  261. unsigned int irq_enable;
  262. unsigned int enb = 0;
  263. u8 bit;
  264. tiadc_step_config(indio_dev);
  265. for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
  266. enb |= (get_adc_step_bit(adc_dev, bit) << 1);
  267. adc_dev->total_ch_enabled++;
  268. }
  269. adc_dev->buffer_en_ch_steps = enb;
  270. if (dma->chan)
  271. tiadc_start_dma(indio_dev);
  272. am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
  273. tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES
  274. | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW);
  275. irq_enable = IRQENB_FIFO1OVRRUN;
  276. if (!dma->chan)
  277. irq_enable |= IRQENB_FIFO1THRES;
  278. tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable);
  279. return 0;
  280. }
  281. static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
  282. {
  283. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  284. struct tiadc_dma *dma = &adc_dev->dma;
  285. int fifo1count, i;
  286. tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
  287. IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW));
  288. am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps);
  289. adc_dev->buffer_en_ch_steps = 0;
  290. adc_dev->total_ch_enabled = 0;
  291. if (dma->chan) {
  292. tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2);
  293. dmaengine_terminate_async(dma->chan);
  294. }
  295. /* Flush FIFO of leftover data in the time it takes to disable adc */
  296. fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
  297. for (i = 0; i < fifo1count; i++)
  298. tiadc_readl(adc_dev, REG_FIFO1);
  299. return 0;
  300. }
  301. static int tiadc_buffer_postdisable(struct iio_dev *indio_dev)
  302. {
  303. tiadc_step_config(indio_dev);
  304. return 0;
  305. }
  306. static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = {
  307. .preenable = &tiadc_buffer_preenable,
  308. .postenable = &tiadc_buffer_postenable,
  309. .predisable = &tiadc_buffer_predisable,
  310. .postdisable = &tiadc_buffer_postdisable,
  311. };
  312. static int tiadc_iio_buffered_hardware_setup(struct device *dev,
  313. struct iio_dev *indio_dev,
  314. irqreturn_t (*pollfunc_bh)(int irq, void *p),
  315. irqreturn_t (*pollfunc_th)(int irq, void *p),
  316. int irq,
  317. unsigned long flags,
  318. const struct iio_buffer_setup_ops *setup_ops)
  319. {
  320. struct iio_buffer *buffer;
  321. int ret;
  322. buffer = devm_iio_kfifo_allocate(dev);
  323. if (!buffer)
  324. return -ENOMEM;
  325. iio_device_attach_buffer(indio_dev, buffer);
  326. ret = devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh,
  327. flags, indio_dev->name, indio_dev);
  328. if (ret)
  329. return ret;
  330. indio_dev->setup_ops = setup_ops;
  331. indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
  332. return 0;
  333. }
  334. static const char * const chan_name_ain[] = {
  335. "AIN0",
  336. "AIN1",
  337. "AIN2",
  338. "AIN3",
  339. "AIN4",
  340. "AIN5",
  341. "AIN6",
  342. "AIN7",
  343. };
  344. static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev,
  345. int channels)
  346. {
  347. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  348. struct iio_chan_spec *chan_array;
  349. struct iio_chan_spec *chan;
  350. int i;
  351. indio_dev->num_channels = channels;
  352. chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array),
  353. GFP_KERNEL);
  354. if (chan_array == NULL)
  355. return -ENOMEM;
  356. chan = chan_array;
  357. for (i = 0; i < channels; i++, chan++) {
  358. chan->type = IIO_VOLTAGE;
  359. chan->indexed = 1;
  360. chan->channel = adc_dev->channel_line[i];
  361. chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
  362. chan->datasheet_name = chan_name_ain[chan->channel];
  363. chan->scan_index = i;
  364. chan->scan_type.sign = 'u';
  365. chan->scan_type.realbits = 12;
  366. chan->scan_type.storagebits = 16;
  367. }
  368. indio_dev->channels = chan_array;
  369. return 0;
  370. }
  371. static int tiadc_read_raw(struct iio_dev *indio_dev,
  372. struct iio_chan_spec const *chan,
  373. int *val, int *val2, long mask)
  374. {
  375. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  376. int ret = IIO_VAL_INT;
  377. int i, map_val;
  378. unsigned int fifo1count, read, stepid;
  379. bool found = false;
  380. u32 step_en;
  381. unsigned long timeout;
  382. if (iio_buffer_enabled(indio_dev))
  383. return -EBUSY;
  384. step_en = get_adc_chan_step_mask(adc_dev, chan);
  385. if (!step_en)
  386. return -EINVAL;
  387. mutex_lock(&adc_dev->fifo1_lock);
  388. fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
  389. while (fifo1count--)
  390. tiadc_readl(adc_dev, REG_FIFO1);
  391. am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
  392. timeout = jiffies + msecs_to_jiffies
  393. (IDLE_TIMEOUT * adc_dev->channels);
  394. /* Wait for Fifo threshold interrupt */
  395. while (1) {
  396. fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
  397. if (fifo1count)
  398. break;
  399. if (time_after(jiffies, timeout)) {
  400. am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
  401. ret = -EAGAIN;
  402. goto err_unlock;
  403. }
  404. }
  405. map_val = adc_dev->channel_step[chan->scan_index];
  406. /*
  407. * We check the complete FIFO. We programmed just one entry but in case
  408. * something went wrong we left empty handed (-EAGAIN previously) and
  409. * then the value apeared somehow in the FIFO we would have two entries.
  410. * Therefore we read every item and keep only the latest version of the
  411. * requested channel.
  412. */
  413. for (i = 0; i < fifo1count; i++) {
  414. read = tiadc_readl(adc_dev, REG_FIFO1);
  415. stepid = read & FIFOREAD_CHNLID_MASK;
  416. stepid = stepid >> 0x10;
  417. if (stepid == map_val) {
  418. read = read & FIFOREAD_DATA_MASK;
  419. found = true;
  420. *val = (u16) read;
  421. }
  422. }
  423. am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
  424. if (!found)
  425. ret = -EBUSY;
  426. err_unlock:
  427. mutex_unlock(&adc_dev->fifo1_lock);
  428. return ret;
  429. }
  430. static const struct iio_info tiadc_info = {
  431. .read_raw = &tiadc_read_raw,
  432. };
  433. static int tiadc_request_dma(struct platform_device *pdev,
  434. struct tiadc_device *adc_dev)
  435. {
  436. struct tiadc_dma *dma = &adc_dev->dma;
  437. dma_cap_mask_t mask;
  438. /* Default slave configuration parameters */
  439. dma->conf.direction = DMA_DEV_TO_MEM;
  440. dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  441. dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
  442. dma_cap_zero(mask);
  443. dma_cap_set(DMA_CYCLIC, mask);
  444. /* Get a channel for RX */
  445. dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
  446. if (IS_ERR(dma->chan)) {
  447. int ret = PTR_ERR(dma->chan);
  448. dma->chan = NULL;
  449. return ret;
  450. }
  451. /* RX buffer */
  452. dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
  453. &dma->addr, GFP_KERNEL);
  454. if (!dma->buf)
  455. goto err;
  456. return 0;
  457. err:
  458. dma_release_channel(dma->chan);
  459. return -ENOMEM;
  460. }
  461. static int tiadc_parse_dt(struct platform_device *pdev,
  462. struct tiadc_device *adc_dev)
  463. {
  464. struct device_node *node = pdev->dev.of_node;
  465. struct property *prop;
  466. const __be32 *cur;
  467. int channels = 0;
  468. u32 val;
  469. of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
  470. adc_dev->channel_line[channels] = val;
  471. /* Set Default values for optional DT parameters */
  472. adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY;
  473. adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY;
  474. adc_dev->step_avg[channels] = 16;
  475. channels++;
  476. }
  477. of_property_read_u32_array(node, "ti,chan-step-avg",
  478. adc_dev->step_avg, channels);
  479. of_property_read_u32_array(node, "ti,chan-step-opendelay",
  480. adc_dev->open_delay, channels);
  481. of_property_read_u32_array(node, "ti,chan-step-sampledelay",
  482. adc_dev->sample_delay, channels);
  483. adc_dev->channels = channels;
  484. return 0;
  485. }
  486. static int tiadc_probe(struct platform_device *pdev)
  487. {
  488. struct iio_dev *indio_dev;
  489. struct tiadc_device *adc_dev;
  490. struct device_node *node = pdev->dev.of_node;
  491. int err;
  492. if (!node) {
  493. dev_err(&pdev->dev, "Could not find valid DT data.\n");
  494. return -EINVAL;
  495. }
  496. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
  497. if (indio_dev == NULL) {
  498. dev_err(&pdev->dev, "failed to allocate iio device\n");
  499. return -ENOMEM;
  500. }
  501. adc_dev = iio_priv(indio_dev);
  502. adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev);
  503. tiadc_parse_dt(pdev, adc_dev);
  504. indio_dev->name = dev_name(&pdev->dev);
  505. indio_dev->modes = INDIO_DIRECT_MODE;
  506. indio_dev->info = &tiadc_info;
  507. tiadc_step_config(indio_dev);
  508. tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD);
  509. mutex_init(&adc_dev->fifo1_lock);
  510. err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels);
  511. if (err < 0)
  512. return err;
  513. err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev,
  514. &tiadc_worker_h,
  515. &tiadc_irq_h,
  516. adc_dev->mfd_tscadc->irq,
  517. IRQF_SHARED,
  518. &tiadc_buffer_setup_ops);
  519. if (err)
  520. goto err_free_channels;
  521. err = iio_device_register(indio_dev);
  522. if (err)
  523. goto err_buffer_unregister;
  524. platform_set_drvdata(pdev, indio_dev);
  525. err = tiadc_request_dma(pdev, adc_dev);
  526. if (err && err == -EPROBE_DEFER)
  527. goto err_dma;
  528. return 0;
  529. err_dma:
  530. iio_device_unregister(indio_dev);
  531. err_buffer_unregister:
  532. err_free_channels:
  533. return err;
  534. }
  535. static int tiadc_remove(struct platform_device *pdev)
  536. {
  537. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  538. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  539. struct tiadc_dma *dma = &adc_dev->dma;
  540. u32 step_en;
  541. if (dma->chan) {
  542. dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
  543. dma->buf, dma->addr);
  544. dma_release_channel(dma->chan);
  545. }
  546. iio_device_unregister(indio_dev);
  547. step_en = get_adc_step_mask(adc_dev);
  548. am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en);
  549. return 0;
  550. }
  551. static int __maybe_unused tiadc_suspend(struct device *dev)
  552. {
  553. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  554. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  555. unsigned int idle;
  556. idle = tiadc_readl(adc_dev, REG_CTRL);
  557. idle &= ~(CNTRLREG_TSCSSENB);
  558. tiadc_writel(adc_dev, REG_CTRL, (idle |
  559. CNTRLREG_POWERDOWN));
  560. return 0;
  561. }
  562. static int __maybe_unused tiadc_resume(struct device *dev)
  563. {
  564. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  565. struct tiadc_device *adc_dev = iio_priv(indio_dev);
  566. unsigned int restore;
  567. /* Make sure ADC is powered up */
  568. restore = tiadc_readl(adc_dev, REG_CTRL);
  569. restore &= ~(CNTRLREG_POWERDOWN);
  570. tiadc_writel(adc_dev, REG_CTRL, restore);
  571. tiadc_step_config(indio_dev);
  572. am335x_tsc_se_set_cache(adc_dev->mfd_tscadc,
  573. adc_dev->buffer_en_ch_steps);
  574. return 0;
  575. }
  576. static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume);
  577. static const struct of_device_id ti_adc_dt_ids[] = {
  578. { .compatible = "ti,am3359-adc", },
  579. { }
  580. };
  581. MODULE_DEVICE_TABLE(of, ti_adc_dt_ids);
  582. static struct platform_driver tiadc_driver = {
  583. .driver = {
  584. .name = "TI-am335x-adc",
  585. .pm = &tiadc_pm_ops,
  586. .of_match_table = ti_adc_dt_ids,
  587. },
  588. .probe = tiadc_probe,
  589. .remove = tiadc_remove,
  590. };
  591. module_platform_driver(tiadc_driver);
  592. MODULE_DESCRIPTION("TI ADC controller driver");
  593. MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
  594. MODULE_LICENSE("GPL");