ti-ads8688.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Prevas A/S
  4. */
  5. #include <linux/device.h>
  6. #include <linux/kernel.h>
  7. #include <linux/slab.h>
  8. #include <linux/sysfs.h>
  9. #include <linux/spi/spi.h>
  10. #include <linux/regulator/consumer.h>
  11. #include <linux/err.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/iio/iio.h>
  15. #include <linux/iio/buffer.h>
  16. #include <linux/iio/trigger_consumer.h>
  17. #include <linux/iio/triggered_buffer.h>
  18. #include <linux/iio/sysfs.h>
  19. #define ADS8688_CMD_REG(x) (x << 8)
  20. #define ADS8688_CMD_REG_NOOP 0x00
  21. #define ADS8688_CMD_REG_RST 0x85
  22. #define ADS8688_CMD_REG_MAN_CH(chan) (0xC0 | (4 * chan))
  23. #define ADS8688_CMD_DONT_CARE_BITS 16
  24. #define ADS8688_PROG_REG(x) (x << 9)
  25. #define ADS8688_PROG_REG_RANGE_CH(chan) (0x05 + chan)
  26. #define ADS8688_PROG_WR_BIT BIT(8)
  27. #define ADS8688_PROG_DONT_CARE_BITS 8
  28. #define ADS8688_REG_PLUSMINUS25VREF 0
  29. #define ADS8688_REG_PLUSMINUS125VREF 1
  30. #define ADS8688_REG_PLUSMINUS0625VREF 2
  31. #define ADS8688_REG_PLUS25VREF 5
  32. #define ADS8688_REG_PLUS125VREF 6
  33. #define ADS8688_VREF_MV 4096
  34. #define ADS8688_REALBITS 16
  35. #define ADS8688_MAX_CHANNELS 8
  36. /*
  37. * enum ads8688_range - ADS8688 reference voltage range
  38. * @ADS8688_PLUSMINUS25VREF: Device is configured for input range ±2.5 * VREF
  39. * @ADS8688_PLUSMINUS125VREF: Device is configured for input range ±1.25 * VREF
  40. * @ADS8688_PLUSMINUS0625VREF: Device is configured for input range ±0.625 * VREF
  41. * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF
  42. * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF
  43. */
  44. enum ads8688_range {
  45. ADS8688_PLUSMINUS25VREF,
  46. ADS8688_PLUSMINUS125VREF,
  47. ADS8688_PLUSMINUS0625VREF,
  48. ADS8688_PLUS25VREF,
  49. ADS8688_PLUS125VREF,
  50. };
  51. struct ads8688_chip_info {
  52. const struct iio_chan_spec *channels;
  53. unsigned int num_channels;
  54. };
  55. struct ads8688_state {
  56. struct mutex lock;
  57. const struct ads8688_chip_info *chip_info;
  58. struct spi_device *spi;
  59. struct regulator *reg;
  60. unsigned int vref_mv;
  61. enum ads8688_range range[8];
  62. union {
  63. __be32 d32;
  64. u8 d8[4];
  65. } data[2] ____cacheline_aligned;
  66. };
  67. enum ads8688_id {
  68. ID_ADS8684,
  69. ID_ADS8688,
  70. };
  71. struct ads8688_ranges {
  72. enum ads8688_range range;
  73. unsigned int scale;
  74. int offset;
  75. u8 reg;
  76. };
  77. static const struct ads8688_ranges ads8688_range_def[5] = {
  78. {
  79. .range = ADS8688_PLUSMINUS25VREF,
  80. .scale = 76295,
  81. .offset = -(1 << (ADS8688_REALBITS - 1)),
  82. .reg = ADS8688_REG_PLUSMINUS25VREF,
  83. }, {
  84. .range = ADS8688_PLUSMINUS125VREF,
  85. .scale = 38148,
  86. .offset = -(1 << (ADS8688_REALBITS - 1)),
  87. .reg = ADS8688_REG_PLUSMINUS125VREF,
  88. }, {
  89. .range = ADS8688_PLUSMINUS0625VREF,
  90. .scale = 19074,
  91. .offset = -(1 << (ADS8688_REALBITS - 1)),
  92. .reg = ADS8688_REG_PLUSMINUS0625VREF,
  93. }, {
  94. .range = ADS8688_PLUS25VREF,
  95. .scale = 38148,
  96. .offset = 0,
  97. .reg = ADS8688_REG_PLUS25VREF,
  98. }, {
  99. .range = ADS8688_PLUS125VREF,
  100. .scale = 19074,
  101. .offset = 0,
  102. .reg = ADS8688_REG_PLUS125VREF,
  103. }
  104. };
  105. static ssize_t ads8688_show_scales(struct device *dev,
  106. struct device_attribute *attr, char *buf)
  107. {
  108. struct ads8688_state *st = iio_priv(dev_to_iio_dev(dev));
  109. return sprintf(buf, "0.%09u 0.%09u 0.%09u\n",
  110. ads8688_range_def[0].scale * st->vref_mv,
  111. ads8688_range_def[1].scale * st->vref_mv,
  112. ads8688_range_def[2].scale * st->vref_mv);
  113. }
  114. static ssize_t ads8688_show_offsets(struct device *dev,
  115. struct device_attribute *attr, char *buf)
  116. {
  117. return sprintf(buf, "%d %d\n", ads8688_range_def[0].offset,
  118. ads8688_range_def[3].offset);
  119. }
  120. static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
  121. ads8688_show_scales, NULL, 0);
  122. static IIO_DEVICE_ATTR(in_voltage_offset_available, S_IRUGO,
  123. ads8688_show_offsets, NULL, 0);
  124. static struct attribute *ads8688_attributes[] = {
  125. &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
  126. &iio_dev_attr_in_voltage_offset_available.dev_attr.attr,
  127. NULL,
  128. };
  129. static const struct attribute_group ads8688_attribute_group = {
  130. .attrs = ads8688_attributes,
  131. };
  132. #define ADS8688_CHAN(index) \
  133. { \
  134. .type = IIO_VOLTAGE, \
  135. .indexed = 1, \
  136. .channel = index, \
  137. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
  138. | BIT(IIO_CHAN_INFO_SCALE) \
  139. | BIT(IIO_CHAN_INFO_OFFSET), \
  140. .scan_index = index, \
  141. .scan_type = { \
  142. .sign = 'u', \
  143. .realbits = 16, \
  144. .storagebits = 16, \
  145. .endianness = IIO_BE, \
  146. }, \
  147. }
  148. static const struct iio_chan_spec ads8684_channels[] = {
  149. ADS8688_CHAN(0),
  150. ADS8688_CHAN(1),
  151. ADS8688_CHAN(2),
  152. ADS8688_CHAN(3),
  153. };
  154. static const struct iio_chan_spec ads8688_channels[] = {
  155. ADS8688_CHAN(0),
  156. ADS8688_CHAN(1),
  157. ADS8688_CHAN(2),
  158. ADS8688_CHAN(3),
  159. ADS8688_CHAN(4),
  160. ADS8688_CHAN(5),
  161. ADS8688_CHAN(6),
  162. ADS8688_CHAN(7),
  163. };
  164. static int ads8688_prog_write(struct iio_dev *indio_dev, unsigned int addr,
  165. unsigned int val)
  166. {
  167. struct ads8688_state *st = iio_priv(indio_dev);
  168. u32 tmp;
  169. tmp = ADS8688_PROG_REG(addr) | ADS8688_PROG_WR_BIT | val;
  170. tmp <<= ADS8688_PROG_DONT_CARE_BITS;
  171. st->data[0].d32 = cpu_to_be32(tmp);
  172. return spi_write(st->spi, &st->data[0].d8[1], 3);
  173. }
  174. static int ads8688_reset(struct iio_dev *indio_dev)
  175. {
  176. struct ads8688_state *st = iio_priv(indio_dev);
  177. u32 tmp;
  178. tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_RST);
  179. tmp <<= ADS8688_CMD_DONT_CARE_BITS;
  180. st->data[0].d32 = cpu_to_be32(tmp);
  181. return spi_write(st->spi, &st->data[0].d8[0], 4);
  182. }
  183. static int ads8688_read(struct iio_dev *indio_dev, unsigned int chan)
  184. {
  185. struct ads8688_state *st = iio_priv(indio_dev);
  186. int ret;
  187. u32 tmp;
  188. struct spi_transfer t[] = {
  189. {
  190. .tx_buf = &st->data[0].d8[0],
  191. .len = 4,
  192. .cs_change = 1,
  193. }, {
  194. .tx_buf = &st->data[1].d8[0],
  195. .rx_buf = &st->data[1].d8[0],
  196. .len = 4,
  197. },
  198. };
  199. tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_MAN_CH(chan));
  200. tmp <<= ADS8688_CMD_DONT_CARE_BITS;
  201. st->data[0].d32 = cpu_to_be32(tmp);
  202. tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_NOOP);
  203. tmp <<= ADS8688_CMD_DONT_CARE_BITS;
  204. st->data[1].d32 = cpu_to_be32(tmp);
  205. ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
  206. if (ret < 0)
  207. return ret;
  208. return be32_to_cpu(st->data[1].d32) & 0xffff;
  209. }
  210. static int ads8688_read_raw(struct iio_dev *indio_dev,
  211. struct iio_chan_spec const *chan,
  212. int *val, int *val2, long m)
  213. {
  214. int ret, offset;
  215. unsigned long scale_mv;
  216. struct ads8688_state *st = iio_priv(indio_dev);
  217. mutex_lock(&st->lock);
  218. switch (m) {
  219. case IIO_CHAN_INFO_RAW:
  220. ret = ads8688_read(indio_dev, chan->channel);
  221. mutex_unlock(&st->lock);
  222. if (ret < 0)
  223. return ret;
  224. *val = ret;
  225. return IIO_VAL_INT;
  226. case IIO_CHAN_INFO_SCALE:
  227. scale_mv = st->vref_mv;
  228. scale_mv *= ads8688_range_def[st->range[chan->channel]].scale;
  229. *val = 0;
  230. *val2 = scale_mv;
  231. mutex_unlock(&st->lock);
  232. return IIO_VAL_INT_PLUS_NANO;
  233. case IIO_CHAN_INFO_OFFSET:
  234. offset = ads8688_range_def[st->range[chan->channel]].offset;
  235. *val = offset;
  236. mutex_unlock(&st->lock);
  237. return IIO_VAL_INT;
  238. }
  239. mutex_unlock(&st->lock);
  240. return -EINVAL;
  241. }
  242. static int ads8688_write_reg_range(struct iio_dev *indio_dev,
  243. struct iio_chan_spec const *chan,
  244. enum ads8688_range range)
  245. {
  246. unsigned int tmp;
  247. int ret;
  248. tmp = ADS8688_PROG_REG_RANGE_CH(chan->channel);
  249. ret = ads8688_prog_write(indio_dev, tmp, range);
  250. return ret;
  251. }
  252. static int ads8688_write_raw(struct iio_dev *indio_dev,
  253. struct iio_chan_spec const *chan,
  254. int val, int val2, long mask)
  255. {
  256. struct ads8688_state *st = iio_priv(indio_dev);
  257. unsigned int scale = 0;
  258. int ret = -EINVAL, i, offset = 0;
  259. mutex_lock(&st->lock);
  260. switch (mask) {
  261. case IIO_CHAN_INFO_SCALE:
  262. /* If the offset is 0 the ±2.5 * VREF mode is not available */
  263. offset = ads8688_range_def[st->range[chan->channel]].offset;
  264. if (offset == 0 && val2 == ads8688_range_def[0].scale * st->vref_mv) {
  265. mutex_unlock(&st->lock);
  266. return -EINVAL;
  267. }
  268. /* Lookup new mode */
  269. for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
  270. if (val2 == ads8688_range_def[i].scale * st->vref_mv &&
  271. offset == ads8688_range_def[i].offset) {
  272. ret = ads8688_write_reg_range(indio_dev, chan,
  273. ads8688_range_def[i].reg);
  274. break;
  275. }
  276. break;
  277. case IIO_CHAN_INFO_OFFSET:
  278. /*
  279. * There are only two available offsets:
  280. * 0 and -(1 << (ADS8688_REALBITS - 1))
  281. */
  282. if (!(ads8688_range_def[0].offset == val ||
  283. ads8688_range_def[3].offset == val)) {
  284. mutex_unlock(&st->lock);
  285. return -EINVAL;
  286. }
  287. /*
  288. * If the device are in ±2.5 * VREF mode, it's not allowed to
  289. * switch to a mode where the offset is 0
  290. */
  291. if (val == 0 &&
  292. st->range[chan->channel] == ADS8688_PLUSMINUS25VREF) {
  293. mutex_unlock(&st->lock);
  294. return -EINVAL;
  295. }
  296. scale = ads8688_range_def[st->range[chan->channel]].scale;
  297. /* Lookup new mode */
  298. for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
  299. if (val == ads8688_range_def[i].offset &&
  300. scale == ads8688_range_def[i].scale) {
  301. ret = ads8688_write_reg_range(indio_dev, chan,
  302. ads8688_range_def[i].reg);
  303. break;
  304. }
  305. break;
  306. }
  307. if (!ret)
  308. st->range[chan->channel] = ads8688_range_def[i].range;
  309. mutex_unlock(&st->lock);
  310. return ret;
  311. }
  312. static int ads8688_write_raw_get_fmt(struct iio_dev *indio_dev,
  313. struct iio_chan_spec const *chan,
  314. long mask)
  315. {
  316. switch (mask) {
  317. case IIO_CHAN_INFO_SCALE:
  318. return IIO_VAL_INT_PLUS_NANO;
  319. case IIO_CHAN_INFO_OFFSET:
  320. return IIO_VAL_INT;
  321. }
  322. return -EINVAL;
  323. }
  324. static const struct iio_info ads8688_info = {
  325. .read_raw = &ads8688_read_raw,
  326. .write_raw = &ads8688_write_raw,
  327. .write_raw_get_fmt = &ads8688_write_raw_get_fmt,
  328. .attrs = &ads8688_attribute_group,
  329. };
  330. static irqreturn_t ads8688_trigger_handler(int irq, void *p)
  331. {
  332. struct iio_poll_func *pf = p;
  333. struct iio_dev *indio_dev = pf->indio_dev;
  334. /* Ensure naturally aligned timestamp */
  335. u16 buffer[ADS8688_MAX_CHANNELS + sizeof(s64)/sizeof(u16)] __aligned(8);
  336. int i, j = 0;
  337. for (i = 0; i < indio_dev->masklength; i++) {
  338. if (!test_bit(i, indio_dev->active_scan_mask))
  339. continue;
  340. buffer[j] = ads8688_read(indio_dev, i);
  341. j++;
  342. }
  343. iio_push_to_buffers_with_timestamp(indio_dev, buffer,
  344. iio_get_time_ns(indio_dev));
  345. iio_trigger_notify_done(indio_dev->trig);
  346. return IRQ_HANDLED;
  347. }
  348. static const struct ads8688_chip_info ads8688_chip_info_tbl[] = {
  349. [ID_ADS8684] = {
  350. .channels = ads8684_channels,
  351. .num_channels = ARRAY_SIZE(ads8684_channels),
  352. },
  353. [ID_ADS8688] = {
  354. .channels = ads8688_channels,
  355. .num_channels = ARRAY_SIZE(ads8688_channels),
  356. },
  357. };
  358. static int ads8688_probe(struct spi_device *spi)
  359. {
  360. struct ads8688_state *st;
  361. struct iio_dev *indio_dev;
  362. int ret;
  363. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  364. if (indio_dev == NULL)
  365. return -ENOMEM;
  366. st = iio_priv(indio_dev);
  367. st->reg = devm_regulator_get_optional(&spi->dev, "vref");
  368. if (!IS_ERR(st->reg)) {
  369. ret = regulator_enable(st->reg);
  370. if (ret)
  371. return ret;
  372. ret = regulator_get_voltage(st->reg);
  373. if (ret < 0)
  374. goto err_regulator_disable;
  375. st->vref_mv = ret / 1000;
  376. } else {
  377. /* Use internal reference */
  378. st->vref_mv = ADS8688_VREF_MV;
  379. }
  380. st->chip_info = &ads8688_chip_info_tbl[spi_get_device_id(spi)->driver_data];
  381. spi->mode = SPI_MODE_1;
  382. spi_set_drvdata(spi, indio_dev);
  383. st->spi = spi;
  384. indio_dev->name = spi_get_device_id(spi)->name;
  385. indio_dev->modes = INDIO_DIRECT_MODE;
  386. indio_dev->channels = st->chip_info->channels;
  387. indio_dev->num_channels = st->chip_info->num_channels;
  388. indio_dev->info = &ads8688_info;
  389. ads8688_reset(indio_dev);
  390. mutex_init(&st->lock);
  391. ret = iio_triggered_buffer_setup(indio_dev, NULL, ads8688_trigger_handler, NULL);
  392. if (ret < 0) {
  393. dev_err(&spi->dev, "iio triggered buffer setup failed\n");
  394. goto err_regulator_disable;
  395. }
  396. ret = iio_device_register(indio_dev);
  397. if (ret)
  398. goto err_buffer_cleanup;
  399. return 0;
  400. err_buffer_cleanup:
  401. iio_triggered_buffer_cleanup(indio_dev);
  402. err_regulator_disable:
  403. if (!IS_ERR(st->reg))
  404. regulator_disable(st->reg);
  405. return ret;
  406. }
  407. static int ads8688_remove(struct spi_device *spi)
  408. {
  409. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  410. struct ads8688_state *st = iio_priv(indio_dev);
  411. iio_device_unregister(indio_dev);
  412. iio_triggered_buffer_cleanup(indio_dev);
  413. if (!IS_ERR(st->reg))
  414. regulator_disable(st->reg);
  415. return 0;
  416. }
  417. static const struct spi_device_id ads8688_id[] = {
  418. {"ads8684", ID_ADS8684},
  419. {"ads8688", ID_ADS8688},
  420. {}
  421. };
  422. MODULE_DEVICE_TABLE(spi, ads8688_id);
  423. static const struct of_device_id ads8688_of_match[] = {
  424. { .compatible = "ti,ads8684" },
  425. { .compatible = "ti,ads8688" },
  426. { }
  427. };
  428. MODULE_DEVICE_TABLE(of, ads8688_of_match);
  429. static struct spi_driver ads8688_driver = {
  430. .driver = {
  431. .name = "ads8688",
  432. },
  433. .probe = ads8688_probe,
  434. .remove = ads8688_remove,
  435. .id_table = ads8688_id,
  436. };
  437. module_spi_driver(ads8688_driver);
  438. MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.dk>");
  439. MODULE_DESCRIPTION("Texas Instruments ADS8688 driver");
  440. MODULE_LICENSE("GPL v2");