ti-ads7950.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments ADS7950 SPI ADC driver
  4. *
  5. * Copyright 2016 David Lechner <david@lechnology.com>
  6. *
  7. * Based on iio/ad7923.c:
  8. * Copyright 2011 Analog Devices Inc
  9. * Copyright 2012 CS Systemes d'Information
  10. *
  11. * And also on hwmon/ads79xx.c
  12. * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  13. * Nishanth Menon
  14. */
  15. #include <linux/acpi.h>
  16. #include <linux/bitops.h>
  17. #include <linux/device.h>
  18. #include <linux/err.h>
  19. #include <linux/gpio/driver.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/slab.h>
  25. #include <linux/spi/spi.h>
  26. #include <linux/iio/buffer.h>
  27. #include <linux/iio/iio.h>
  28. #include <linux/iio/sysfs.h>
  29. #include <linux/iio/trigger_consumer.h>
  30. #include <linux/iio/triggered_buffer.h>
  31. /*
  32. * In case of ACPI, we use the 5000 mV as default for the reference pin.
  33. * Device tree users encode that via the vref-supply regulator.
  34. */
  35. #define TI_ADS7950_VA_MV_ACPI_DEFAULT 5000
  36. #define TI_ADS7950_CR_GPIO BIT(14)
  37. #define TI_ADS7950_CR_MANUAL BIT(12)
  38. #define TI_ADS7950_CR_WRITE BIT(11)
  39. #define TI_ADS7950_CR_CHAN(ch) ((ch) << 7)
  40. #define TI_ADS7950_CR_RANGE_5V BIT(6)
  41. #define TI_ADS7950_CR_GPIO_DATA BIT(4)
  42. #define TI_ADS7950_MAX_CHAN 16
  43. #define TI_ADS7950_NUM_GPIOS 4
  44. #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
  45. /* val = value, dec = left shift, bits = number of bits of the mask */
  46. #define TI_ADS7950_EXTRACT(val, dec, bits) \
  47. (((val) >> (dec)) & ((1 << (bits)) - 1))
  48. #define TI_ADS7950_MAN_CMD(cmd) (TI_ADS7950_CR_MANUAL | (cmd))
  49. #define TI_ADS7950_GPIO_CMD(cmd) (TI_ADS7950_CR_GPIO | (cmd))
  50. /* Manual mode configuration */
  51. #define TI_ADS7950_MAN_CMD_SETTINGS(st) \
  52. (TI_ADS7950_MAN_CMD(TI_ADS7950_CR_WRITE | st->cmd_settings_bitmask))
  53. /* GPIO mode configuration */
  54. #define TI_ADS7950_GPIO_CMD_SETTINGS(st) \
  55. (TI_ADS7950_GPIO_CMD(st->gpio_cmd_settings_bitmask))
  56. struct ti_ads7950_state {
  57. struct spi_device *spi;
  58. struct spi_transfer ring_xfer;
  59. struct spi_transfer scan_single_xfer[3];
  60. struct spi_message ring_msg;
  61. struct spi_message scan_single_msg;
  62. /* Lock to protect the spi xfer buffers */
  63. struct mutex slock;
  64. struct gpio_chip chip;
  65. struct regulator *reg;
  66. unsigned int vref_mv;
  67. /*
  68. * Bitmask of lower 7 bits used for configuration
  69. * These bits only can be written when TI_ADS7950_CR_WRITE
  70. * is set, otherwise it retains its original state.
  71. * [0-3] GPIO signal
  72. * [4] Set following frame to return GPIO signal values
  73. * [5] Powers down device
  74. * [6] Sets Vref range1(2.5v) or range2(5v)
  75. *
  76. * Bits present on Manual/Auto1/Auto2 commands
  77. */
  78. unsigned int cmd_settings_bitmask;
  79. /*
  80. * Bitmask of GPIO command
  81. * [0-3] GPIO direction
  82. * [4-6] Different GPIO alarm mode configurations
  83. * [7] GPIO 2 as device range input
  84. * [8] GPIO 3 as device power down input
  85. * [9] Reset all registers
  86. * [10-11] N/A
  87. */
  88. unsigned int gpio_cmd_settings_bitmask;
  89. /*
  90. * DMA (thus cache coherency maintenance) requires the
  91. * transfer buffers to live in their own cache lines.
  92. */
  93. u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]
  94. ____cacheline_aligned;
  95. u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];
  96. u16 single_tx;
  97. u16 single_rx;
  98. };
  99. struct ti_ads7950_chip_info {
  100. const struct iio_chan_spec *channels;
  101. unsigned int num_channels;
  102. };
  103. enum ti_ads7950_id {
  104. TI_ADS7950,
  105. TI_ADS7951,
  106. TI_ADS7952,
  107. TI_ADS7953,
  108. TI_ADS7954,
  109. TI_ADS7955,
  110. TI_ADS7956,
  111. TI_ADS7957,
  112. TI_ADS7958,
  113. TI_ADS7959,
  114. TI_ADS7960,
  115. TI_ADS7961,
  116. };
  117. #define TI_ADS7950_V_CHAN(index, bits) \
  118. { \
  119. .type = IIO_VOLTAGE, \
  120. .indexed = 1, \
  121. .channel = index, \
  122. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  123. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  124. .address = index, \
  125. .datasheet_name = "CH##index", \
  126. .scan_index = index, \
  127. .scan_type = { \
  128. .sign = 'u', \
  129. .realbits = bits, \
  130. .storagebits = 16, \
  131. .shift = 12 - (bits), \
  132. .endianness = IIO_CPU, \
  133. }, \
  134. }
  135. #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
  136. const struct iio_chan_spec name ## _channels[] = { \
  137. TI_ADS7950_V_CHAN(0, bits), \
  138. TI_ADS7950_V_CHAN(1, bits), \
  139. TI_ADS7950_V_CHAN(2, bits), \
  140. TI_ADS7950_V_CHAN(3, bits), \
  141. IIO_CHAN_SOFT_TIMESTAMP(4), \
  142. }
  143. #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
  144. const struct iio_chan_spec name ## _channels[] = { \
  145. TI_ADS7950_V_CHAN(0, bits), \
  146. TI_ADS7950_V_CHAN(1, bits), \
  147. TI_ADS7950_V_CHAN(2, bits), \
  148. TI_ADS7950_V_CHAN(3, bits), \
  149. TI_ADS7950_V_CHAN(4, bits), \
  150. TI_ADS7950_V_CHAN(5, bits), \
  151. TI_ADS7950_V_CHAN(6, bits), \
  152. TI_ADS7950_V_CHAN(7, bits), \
  153. IIO_CHAN_SOFT_TIMESTAMP(8), \
  154. }
  155. #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
  156. const struct iio_chan_spec name ## _channels[] = { \
  157. TI_ADS7950_V_CHAN(0, bits), \
  158. TI_ADS7950_V_CHAN(1, bits), \
  159. TI_ADS7950_V_CHAN(2, bits), \
  160. TI_ADS7950_V_CHAN(3, bits), \
  161. TI_ADS7950_V_CHAN(4, bits), \
  162. TI_ADS7950_V_CHAN(5, bits), \
  163. TI_ADS7950_V_CHAN(6, bits), \
  164. TI_ADS7950_V_CHAN(7, bits), \
  165. TI_ADS7950_V_CHAN(8, bits), \
  166. TI_ADS7950_V_CHAN(9, bits), \
  167. TI_ADS7950_V_CHAN(10, bits), \
  168. TI_ADS7950_V_CHAN(11, bits), \
  169. IIO_CHAN_SOFT_TIMESTAMP(12), \
  170. }
  171. #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
  172. const struct iio_chan_spec name ## _channels[] = { \
  173. TI_ADS7950_V_CHAN(0, bits), \
  174. TI_ADS7950_V_CHAN(1, bits), \
  175. TI_ADS7950_V_CHAN(2, bits), \
  176. TI_ADS7950_V_CHAN(3, bits), \
  177. TI_ADS7950_V_CHAN(4, bits), \
  178. TI_ADS7950_V_CHAN(5, bits), \
  179. TI_ADS7950_V_CHAN(6, bits), \
  180. TI_ADS7950_V_CHAN(7, bits), \
  181. TI_ADS7950_V_CHAN(8, bits), \
  182. TI_ADS7950_V_CHAN(9, bits), \
  183. TI_ADS7950_V_CHAN(10, bits), \
  184. TI_ADS7950_V_CHAN(11, bits), \
  185. TI_ADS7950_V_CHAN(12, bits), \
  186. TI_ADS7950_V_CHAN(13, bits), \
  187. TI_ADS7950_V_CHAN(14, bits), \
  188. TI_ADS7950_V_CHAN(15, bits), \
  189. IIO_CHAN_SOFT_TIMESTAMP(16), \
  190. }
  191. static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
  192. static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
  193. static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
  194. static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
  195. static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
  196. static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
  197. static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
  198. static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
  199. static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
  200. static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
  201. static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
  202. static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
  203. static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
  204. [TI_ADS7950] = {
  205. .channels = ti_ads7950_channels,
  206. .num_channels = ARRAY_SIZE(ti_ads7950_channels),
  207. },
  208. [TI_ADS7951] = {
  209. .channels = ti_ads7951_channels,
  210. .num_channels = ARRAY_SIZE(ti_ads7951_channels),
  211. },
  212. [TI_ADS7952] = {
  213. .channels = ti_ads7952_channels,
  214. .num_channels = ARRAY_SIZE(ti_ads7952_channels),
  215. },
  216. [TI_ADS7953] = {
  217. .channels = ti_ads7953_channels,
  218. .num_channels = ARRAY_SIZE(ti_ads7953_channels),
  219. },
  220. [TI_ADS7954] = {
  221. .channels = ti_ads7954_channels,
  222. .num_channels = ARRAY_SIZE(ti_ads7954_channels),
  223. },
  224. [TI_ADS7955] = {
  225. .channels = ti_ads7955_channels,
  226. .num_channels = ARRAY_SIZE(ti_ads7955_channels),
  227. },
  228. [TI_ADS7956] = {
  229. .channels = ti_ads7956_channels,
  230. .num_channels = ARRAY_SIZE(ti_ads7956_channels),
  231. },
  232. [TI_ADS7957] = {
  233. .channels = ti_ads7957_channels,
  234. .num_channels = ARRAY_SIZE(ti_ads7957_channels),
  235. },
  236. [TI_ADS7958] = {
  237. .channels = ti_ads7958_channels,
  238. .num_channels = ARRAY_SIZE(ti_ads7958_channels),
  239. },
  240. [TI_ADS7959] = {
  241. .channels = ti_ads7959_channels,
  242. .num_channels = ARRAY_SIZE(ti_ads7959_channels),
  243. },
  244. [TI_ADS7960] = {
  245. .channels = ti_ads7960_channels,
  246. .num_channels = ARRAY_SIZE(ti_ads7960_channels),
  247. },
  248. [TI_ADS7961] = {
  249. .channels = ti_ads7961_channels,
  250. .num_channels = ARRAY_SIZE(ti_ads7961_channels),
  251. },
  252. };
  253. /*
  254. * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
  255. * scan mask
  256. */
  257. static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
  258. const unsigned long *active_scan_mask)
  259. {
  260. struct ti_ads7950_state *st = iio_priv(indio_dev);
  261. int i, cmd, len;
  262. len = 0;
  263. for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
  264. cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(i));
  265. st->tx_buf[len++] = cmd;
  266. }
  267. /* Data for the 1st channel is not returned until the 3rd transfer */
  268. st->tx_buf[len++] = 0;
  269. st->tx_buf[len++] = 0;
  270. st->ring_xfer.len = len * 2;
  271. return 0;
  272. }
  273. static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
  274. {
  275. struct iio_poll_func *pf = p;
  276. struct iio_dev *indio_dev = pf->indio_dev;
  277. struct ti_ads7950_state *st = iio_priv(indio_dev);
  278. int ret;
  279. mutex_lock(&st->slock);
  280. ret = spi_sync(st->spi, &st->ring_msg);
  281. if (ret < 0)
  282. goto out;
  283. iio_push_to_buffers_with_timestamp(indio_dev, &st->rx_buf[2],
  284. iio_get_time_ns(indio_dev));
  285. out:
  286. mutex_unlock(&st->slock);
  287. iio_trigger_notify_done(indio_dev->trig);
  288. return IRQ_HANDLED;
  289. }
  290. static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
  291. {
  292. struct ti_ads7950_state *st = iio_priv(indio_dev);
  293. int ret, cmd;
  294. mutex_lock(&st->slock);
  295. cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(ch));
  296. st->single_tx = cmd;
  297. ret = spi_sync(st->spi, &st->scan_single_msg);
  298. if (ret)
  299. goto out;
  300. ret = st->single_rx;
  301. out:
  302. mutex_unlock(&st->slock);
  303. return ret;
  304. }
  305. static int ti_ads7950_get_range(struct ti_ads7950_state *st)
  306. {
  307. int vref;
  308. if (st->vref_mv) {
  309. vref = st->vref_mv;
  310. } else {
  311. vref = regulator_get_voltage(st->reg);
  312. if (vref < 0)
  313. return vref;
  314. vref /= 1000;
  315. }
  316. if (st->cmd_settings_bitmask & TI_ADS7950_CR_RANGE_5V)
  317. vref *= 2;
  318. return vref;
  319. }
  320. static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
  321. struct iio_chan_spec const *chan,
  322. int *val, int *val2, long m)
  323. {
  324. struct ti_ads7950_state *st = iio_priv(indio_dev);
  325. int ret;
  326. switch (m) {
  327. case IIO_CHAN_INFO_RAW:
  328. ret = ti_ads7950_scan_direct(indio_dev, chan->address);
  329. if (ret < 0)
  330. return ret;
  331. if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
  332. return -EIO;
  333. *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
  334. chan->scan_type.realbits);
  335. return IIO_VAL_INT;
  336. case IIO_CHAN_INFO_SCALE:
  337. ret = ti_ads7950_get_range(st);
  338. if (ret < 0)
  339. return ret;
  340. *val = ret;
  341. *val2 = (1 << chan->scan_type.realbits) - 1;
  342. return IIO_VAL_FRACTIONAL;
  343. }
  344. return -EINVAL;
  345. }
  346. static const struct iio_info ti_ads7950_info = {
  347. .read_raw = &ti_ads7950_read_raw,
  348. .update_scan_mode = ti_ads7950_update_scan_mode,
  349. };
  350. static void ti_ads7950_set(struct gpio_chip *chip, unsigned int offset,
  351. int value)
  352. {
  353. struct ti_ads7950_state *st = gpiochip_get_data(chip);
  354. mutex_lock(&st->slock);
  355. if (value)
  356. st->cmd_settings_bitmask |= BIT(offset);
  357. else
  358. st->cmd_settings_bitmask &= ~BIT(offset);
  359. st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
  360. spi_sync(st->spi, &st->scan_single_msg);
  361. mutex_unlock(&st->slock);
  362. }
  363. static int ti_ads7950_get(struct gpio_chip *chip, unsigned int offset)
  364. {
  365. struct ti_ads7950_state *st = gpiochip_get_data(chip);
  366. int ret;
  367. mutex_lock(&st->slock);
  368. /* If set as output, return the output */
  369. if (st->gpio_cmd_settings_bitmask & BIT(offset)) {
  370. ret = st->cmd_settings_bitmask & BIT(offset);
  371. goto out;
  372. }
  373. /* GPIO data bit sets SDO bits 12-15 to GPIO input */
  374. st->cmd_settings_bitmask |= TI_ADS7950_CR_GPIO_DATA;
  375. st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
  376. ret = spi_sync(st->spi, &st->scan_single_msg);
  377. if (ret)
  378. goto out;
  379. ret = ((st->single_rx >> 12) & BIT(offset)) ? 1 : 0;
  380. /* Revert back to original settings */
  381. st->cmd_settings_bitmask &= ~TI_ADS7950_CR_GPIO_DATA;
  382. st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
  383. ret = spi_sync(st->spi, &st->scan_single_msg);
  384. if (ret)
  385. goto out;
  386. out:
  387. mutex_unlock(&st->slock);
  388. return ret;
  389. }
  390. static int ti_ads7950_get_direction(struct gpio_chip *chip,
  391. unsigned int offset)
  392. {
  393. struct ti_ads7950_state *st = gpiochip_get_data(chip);
  394. /* Bitmask is inverted from GPIO framework 0=input/1=output */
  395. return !(st->gpio_cmd_settings_bitmask & BIT(offset));
  396. }
  397. static int _ti_ads7950_set_direction(struct gpio_chip *chip, int offset,
  398. int input)
  399. {
  400. struct ti_ads7950_state *st = gpiochip_get_data(chip);
  401. int ret = 0;
  402. mutex_lock(&st->slock);
  403. /* Only change direction if needed */
  404. if (input && (st->gpio_cmd_settings_bitmask & BIT(offset)))
  405. st->gpio_cmd_settings_bitmask &= ~BIT(offset);
  406. else if (!input && !(st->gpio_cmd_settings_bitmask & BIT(offset)))
  407. st->gpio_cmd_settings_bitmask |= BIT(offset);
  408. else
  409. goto out;
  410. st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);
  411. ret = spi_sync(st->spi, &st->scan_single_msg);
  412. out:
  413. mutex_unlock(&st->slock);
  414. return ret;
  415. }
  416. static int ti_ads7950_direction_input(struct gpio_chip *chip,
  417. unsigned int offset)
  418. {
  419. return _ti_ads7950_set_direction(chip, offset, 1);
  420. }
  421. static int ti_ads7950_direction_output(struct gpio_chip *chip,
  422. unsigned int offset, int value)
  423. {
  424. ti_ads7950_set(chip, offset, value);
  425. return _ti_ads7950_set_direction(chip, offset, 0);
  426. }
  427. static int ti_ads7950_init_hw(struct ti_ads7950_state *st)
  428. {
  429. int ret = 0;
  430. mutex_lock(&st->slock);
  431. /* Settings for Manual/Auto1/Auto2 commands */
  432. /* Default to 5v ref */
  433. st->cmd_settings_bitmask = TI_ADS7950_CR_RANGE_5V;
  434. st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
  435. ret = spi_sync(st->spi, &st->scan_single_msg);
  436. if (ret)
  437. goto out;
  438. /* Settings for GPIO command */
  439. st->gpio_cmd_settings_bitmask = 0x0;
  440. st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);
  441. ret = spi_sync(st->spi, &st->scan_single_msg);
  442. out:
  443. mutex_unlock(&st->slock);
  444. return ret;
  445. }
  446. static int ti_ads7950_probe(struct spi_device *spi)
  447. {
  448. struct ti_ads7950_state *st;
  449. struct iio_dev *indio_dev;
  450. const struct ti_ads7950_chip_info *info;
  451. int ret;
  452. spi->bits_per_word = 16;
  453. spi->mode |= SPI_CS_WORD;
  454. ret = spi_setup(spi);
  455. if (ret < 0) {
  456. dev_err(&spi->dev, "Error in spi setup\n");
  457. return ret;
  458. }
  459. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  460. if (!indio_dev)
  461. return -ENOMEM;
  462. st = iio_priv(indio_dev);
  463. spi_set_drvdata(spi, indio_dev);
  464. st->spi = spi;
  465. info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
  466. indio_dev->name = spi_get_device_id(spi)->name;
  467. indio_dev->modes = INDIO_DIRECT_MODE;
  468. indio_dev->channels = info->channels;
  469. indio_dev->num_channels = info->num_channels;
  470. indio_dev->info = &ti_ads7950_info;
  471. /* build spi ring message */
  472. spi_message_init(&st->ring_msg);
  473. st->ring_xfer.tx_buf = &st->tx_buf[0];
  474. st->ring_xfer.rx_buf = &st->rx_buf[0];
  475. /* len will be set later */
  476. spi_message_add_tail(&st->ring_xfer, &st->ring_msg);
  477. /*
  478. * Setup default message. The sample is read at the end of the first
  479. * transfer, then it takes one full cycle to convert the sample and one
  480. * more cycle to send the value. The conversion process is driven by
  481. * the SPI clock, which is why we have 3 transfers. The middle one is
  482. * just dummy data sent while the chip is converting the sample that
  483. * was read at the end of the first transfer.
  484. */
  485. st->scan_single_xfer[0].tx_buf = &st->single_tx;
  486. st->scan_single_xfer[0].len = 2;
  487. st->scan_single_xfer[0].cs_change = 1;
  488. st->scan_single_xfer[1].tx_buf = &st->single_tx;
  489. st->scan_single_xfer[1].len = 2;
  490. st->scan_single_xfer[1].cs_change = 1;
  491. st->scan_single_xfer[2].rx_buf = &st->single_rx;
  492. st->scan_single_xfer[2].len = 2;
  493. spi_message_init_with_transfers(&st->scan_single_msg,
  494. st->scan_single_xfer, 3);
  495. /* Use hard coded value for reference voltage in ACPI case */
  496. if (ACPI_COMPANION(&spi->dev))
  497. st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;
  498. mutex_init(&st->slock);
  499. st->reg = devm_regulator_get(&spi->dev, "vref");
  500. if (IS_ERR(st->reg)) {
  501. dev_err(&spi->dev, "Failed to get regulator \"vref\"\n");
  502. ret = PTR_ERR(st->reg);
  503. goto error_destroy_mutex;
  504. }
  505. ret = regulator_enable(st->reg);
  506. if (ret) {
  507. dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
  508. goto error_destroy_mutex;
  509. }
  510. ret = iio_triggered_buffer_setup(indio_dev, NULL,
  511. &ti_ads7950_trigger_handler, NULL);
  512. if (ret) {
  513. dev_err(&spi->dev, "Failed to setup triggered buffer\n");
  514. goto error_disable_reg;
  515. }
  516. ret = ti_ads7950_init_hw(st);
  517. if (ret) {
  518. dev_err(&spi->dev, "Failed to init adc chip\n");
  519. goto error_cleanup_ring;
  520. }
  521. ret = iio_device_register(indio_dev);
  522. if (ret) {
  523. dev_err(&spi->dev, "Failed to register iio device\n");
  524. goto error_cleanup_ring;
  525. }
  526. /* Add GPIO chip */
  527. st->chip.label = dev_name(&st->spi->dev);
  528. st->chip.parent = &st->spi->dev;
  529. st->chip.owner = THIS_MODULE;
  530. st->chip.base = -1;
  531. st->chip.ngpio = TI_ADS7950_NUM_GPIOS;
  532. st->chip.get_direction = ti_ads7950_get_direction;
  533. st->chip.direction_input = ti_ads7950_direction_input;
  534. st->chip.direction_output = ti_ads7950_direction_output;
  535. st->chip.get = ti_ads7950_get;
  536. st->chip.set = ti_ads7950_set;
  537. ret = gpiochip_add_data(&st->chip, st);
  538. if (ret) {
  539. dev_err(&spi->dev, "Failed to init GPIOs\n");
  540. goto error_iio_device;
  541. }
  542. return 0;
  543. error_iio_device:
  544. iio_device_unregister(indio_dev);
  545. error_cleanup_ring:
  546. iio_triggered_buffer_cleanup(indio_dev);
  547. error_disable_reg:
  548. regulator_disable(st->reg);
  549. error_destroy_mutex:
  550. mutex_destroy(&st->slock);
  551. return ret;
  552. }
  553. static int ti_ads7950_remove(struct spi_device *spi)
  554. {
  555. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  556. struct ti_ads7950_state *st = iio_priv(indio_dev);
  557. gpiochip_remove(&st->chip);
  558. iio_device_unregister(indio_dev);
  559. iio_triggered_buffer_cleanup(indio_dev);
  560. regulator_disable(st->reg);
  561. mutex_destroy(&st->slock);
  562. return 0;
  563. }
  564. static const struct spi_device_id ti_ads7950_id[] = {
  565. { "ads7950", TI_ADS7950 },
  566. { "ads7951", TI_ADS7951 },
  567. { "ads7952", TI_ADS7952 },
  568. { "ads7953", TI_ADS7953 },
  569. { "ads7954", TI_ADS7954 },
  570. { "ads7955", TI_ADS7955 },
  571. { "ads7956", TI_ADS7956 },
  572. { "ads7957", TI_ADS7957 },
  573. { "ads7958", TI_ADS7958 },
  574. { "ads7959", TI_ADS7959 },
  575. { "ads7960", TI_ADS7960 },
  576. { "ads7961", TI_ADS7961 },
  577. { }
  578. };
  579. MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
  580. static const struct of_device_id ads7950_of_table[] = {
  581. { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },
  582. { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },
  583. { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },
  584. { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },
  585. { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },
  586. { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },
  587. { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },
  588. { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },
  589. { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },
  590. { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },
  591. { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },
  592. { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },
  593. { },
  594. };
  595. MODULE_DEVICE_TABLE(of, ads7950_of_table);
  596. static struct spi_driver ti_ads7950_driver = {
  597. .driver = {
  598. .name = "ads7950",
  599. .of_match_table = ads7950_of_table,
  600. },
  601. .probe = ti_ads7950_probe,
  602. .remove = ti_ads7950_remove,
  603. .id_table = ti_ads7950_id,
  604. };
  605. module_spi_driver(ti_ads7950_driver);
  606. MODULE_AUTHOR("David Lechner <david@lechnology.com>");
  607. MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
  608. MODULE_LICENSE("GPL v2");