ti-ads1015.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ADS1015 - Texas Instruments Analog-to-Digital Converter
  4. *
  5. * Copyright (c) 2016, Intel Corporation.
  6. *
  7. * IIO driver for ADS1015 ADC 7-bit I2C slave address:
  8. * * 0x48 - ADDR connected to Ground
  9. * * 0x49 - ADDR connected to Vdd
  10. * * 0x4A - ADDR connected to SDA
  11. * * 0x4B - ADDR connected to SCL
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/irq.h>
  16. #include <linux/i2c.h>
  17. #include <linux/property.h>
  18. #include <linux/regmap.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/mutex.h>
  21. #include <linux/delay.h>
  22. #include <linux/iio/iio.h>
  23. #include <linux/iio/types.h>
  24. #include <linux/iio/sysfs.h>
  25. #include <linux/iio/events.h>
  26. #include <linux/iio/buffer.h>
  27. #include <linux/iio/triggered_buffer.h>
  28. #include <linux/iio/trigger_consumer.h>
  29. #define ADS1015_DRV_NAME "ads1015"
  30. #define ADS1015_CHANNELS 8
  31. #define ADS1015_CONV_REG 0x00
  32. #define ADS1015_CFG_REG 0x01
  33. #define ADS1015_LO_THRESH_REG 0x02
  34. #define ADS1015_HI_THRESH_REG 0x03
  35. #define ADS1015_CFG_COMP_QUE_SHIFT 0
  36. #define ADS1015_CFG_COMP_LAT_SHIFT 2
  37. #define ADS1015_CFG_COMP_POL_SHIFT 3
  38. #define ADS1015_CFG_COMP_MODE_SHIFT 4
  39. #define ADS1015_CFG_DR_SHIFT 5
  40. #define ADS1015_CFG_MOD_SHIFT 8
  41. #define ADS1015_CFG_PGA_SHIFT 9
  42. #define ADS1015_CFG_MUX_SHIFT 12
  43. #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
  44. #define ADS1015_CFG_COMP_LAT_MASK BIT(2)
  45. #define ADS1015_CFG_COMP_POL_MASK BIT(3)
  46. #define ADS1015_CFG_COMP_MODE_MASK BIT(4)
  47. #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
  48. #define ADS1015_CFG_MOD_MASK BIT(8)
  49. #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
  50. #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
  51. /* Comparator queue and disable field */
  52. #define ADS1015_CFG_COMP_DISABLE 3
  53. /* Comparator polarity field */
  54. #define ADS1015_CFG_COMP_POL_LOW 0
  55. #define ADS1015_CFG_COMP_POL_HIGH 1
  56. /* Comparator mode field */
  57. #define ADS1015_CFG_COMP_MODE_TRAD 0
  58. #define ADS1015_CFG_COMP_MODE_WINDOW 1
  59. /* device operating modes */
  60. #define ADS1015_CONTINUOUS 0
  61. #define ADS1015_SINGLESHOT 1
  62. #define ADS1015_SLEEP_DELAY_MS 2000
  63. #define ADS1015_DEFAULT_PGA 2
  64. #define ADS1015_DEFAULT_DATA_RATE 4
  65. #define ADS1015_DEFAULT_CHAN 0
  66. enum chip_ids {
  67. ADSXXXX = 0,
  68. ADS1015,
  69. ADS1115,
  70. };
  71. enum ads1015_channels {
  72. ADS1015_AIN0_AIN1 = 0,
  73. ADS1015_AIN0_AIN3,
  74. ADS1015_AIN1_AIN3,
  75. ADS1015_AIN2_AIN3,
  76. ADS1015_AIN0,
  77. ADS1015_AIN1,
  78. ADS1015_AIN2,
  79. ADS1015_AIN3,
  80. ADS1015_TIMESTAMP,
  81. };
  82. static const unsigned int ads1015_data_rate[] = {
  83. 128, 250, 490, 920, 1600, 2400, 3300, 3300
  84. };
  85. static const unsigned int ads1115_data_rate[] = {
  86. 8, 16, 32, 64, 128, 250, 475, 860
  87. };
  88. /*
  89. * Translation from PGA bits to full-scale positive and negative input voltage
  90. * range in mV
  91. */
  92. static int ads1015_fullscale_range[] = {
  93. 6144, 4096, 2048, 1024, 512, 256, 256, 256
  94. };
  95. /*
  96. * Translation from COMP_QUE field value to the number of successive readings
  97. * exceed the threshold values before an interrupt is generated
  98. */
  99. static const int ads1015_comp_queue[] = { 1, 2, 4 };
  100. static const struct iio_event_spec ads1015_events[] = {
  101. {
  102. .type = IIO_EV_TYPE_THRESH,
  103. .dir = IIO_EV_DIR_RISING,
  104. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  105. BIT(IIO_EV_INFO_ENABLE),
  106. }, {
  107. .type = IIO_EV_TYPE_THRESH,
  108. .dir = IIO_EV_DIR_FALLING,
  109. .mask_separate = BIT(IIO_EV_INFO_VALUE),
  110. }, {
  111. .type = IIO_EV_TYPE_THRESH,
  112. .dir = IIO_EV_DIR_EITHER,
  113. .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
  114. BIT(IIO_EV_INFO_PERIOD),
  115. },
  116. };
  117. #define ADS1015_V_CHAN(_chan, _addr) { \
  118. .type = IIO_VOLTAGE, \
  119. .indexed = 1, \
  120. .address = _addr, \
  121. .channel = _chan, \
  122. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  123. BIT(IIO_CHAN_INFO_SCALE) | \
  124. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  125. .scan_index = _addr, \
  126. .scan_type = { \
  127. .sign = 's', \
  128. .realbits = 12, \
  129. .storagebits = 16, \
  130. .shift = 4, \
  131. .endianness = IIO_CPU, \
  132. }, \
  133. .event_spec = ads1015_events, \
  134. .num_event_specs = ARRAY_SIZE(ads1015_events), \
  135. .datasheet_name = "AIN"#_chan, \
  136. }
  137. #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
  138. .type = IIO_VOLTAGE, \
  139. .differential = 1, \
  140. .indexed = 1, \
  141. .address = _addr, \
  142. .channel = _chan, \
  143. .channel2 = _chan2, \
  144. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  145. BIT(IIO_CHAN_INFO_SCALE) | \
  146. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  147. .scan_index = _addr, \
  148. .scan_type = { \
  149. .sign = 's', \
  150. .realbits = 12, \
  151. .storagebits = 16, \
  152. .shift = 4, \
  153. .endianness = IIO_CPU, \
  154. }, \
  155. .event_spec = ads1015_events, \
  156. .num_event_specs = ARRAY_SIZE(ads1015_events), \
  157. .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
  158. }
  159. #define ADS1115_V_CHAN(_chan, _addr) { \
  160. .type = IIO_VOLTAGE, \
  161. .indexed = 1, \
  162. .address = _addr, \
  163. .channel = _chan, \
  164. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  165. BIT(IIO_CHAN_INFO_SCALE) | \
  166. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  167. .scan_index = _addr, \
  168. .scan_type = { \
  169. .sign = 's', \
  170. .realbits = 16, \
  171. .storagebits = 16, \
  172. .endianness = IIO_CPU, \
  173. }, \
  174. .event_spec = ads1015_events, \
  175. .num_event_specs = ARRAY_SIZE(ads1015_events), \
  176. .datasheet_name = "AIN"#_chan, \
  177. }
  178. #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
  179. .type = IIO_VOLTAGE, \
  180. .differential = 1, \
  181. .indexed = 1, \
  182. .address = _addr, \
  183. .channel = _chan, \
  184. .channel2 = _chan2, \
  185. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  186. BIT(IIO_CHAN_INFO_SCALE) | \
  187. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  188. .scan_index = _addr, \
  189. .scan_type = { \
  190. .sign = 's', \
  191. .realbits = 16, \
  192. .storagebits = 16, \
  193. .endianness = IIO_CPU, \
  194. }, \
  195. .event_spec = ads1015_events, \
  196. .num_event_specs = ARRAY_SIZE(ads1015_events), \
  197. .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
  198. }
  199. struct ads1015_channel_data {
  200. bool enabled;
  201. unsigned int pga;
  202. unsigned int data_rate;
  203. };
  204. struct ads1015_thresh_data {
  205. unsigned int comp_queue;
  206. int high_thresh;
  207. int low_thresh;
  208. };
  209. struct ads1015_data {
  210. struct regmap *regmap;
  211. /*
  212. * Protects ADC ops, e.g: concurrent sysfs/buffered
  213. * data reads, configuration updates
  214. */
  215. struct mutex lock;
  216. struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
  217. unsigned int event_channel;
  218. unsigned int comp_mode;
  219. struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
  220. unsigned int *data_rate;
  221. /*
  222. * Set to true when the ADC is switched to the continuous-conversion
  223. * mode and exits from a power-down state. This flag is used to avoid
  224. * getting the stale result from the conversion register.
  225. */
  226. bool conv_invalid;
  227. };
  228. static bool ads1015_event_channel_enabled(struct ads1015_data *data)
  229. {
  230. return (data->event_channel != ADS1015_CHANNELS);
  231. }
  232. static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
  233. int comp_mode)
  234. {
  235. WARN_ON(ads1015_event_channel_enabled(data));
  236. data->event_channel = chan;
  237. data->comp_mode = comp_mode;
  238. }
  239. static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
  240. {
  241. data->event_channel = ADS1015_CHANNELS;
  242. }
  243. static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
  244. {
  245. switch (reg) {
  246. case ADS1015_CFG_REG:
  247. case ADS1015_LO_THRESH_REG:
  248. case ADS1015_HI_THRESH_REG:
  249. return true;
  250. default:
  251. return false;
  252. }
  253. }
  254. static const struct regmap_config ads1015_regmap_config = {
  255. .reg_bits = 8,
  256. .val_bits = 16,
  257. .max_register = ADS1015_HI_THRESH_REG,
  258. .writeable_reg = ads1015_is_writeable_reg,
  259. };
  260. static const struct iio_chan_spec ads1015_channels[] = {
  261. ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
  262. ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
  263. ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
  264. ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
  265. ADS1015_V_CHAN(0, ADS1015_AIN0),
  266. ADS1015_V_CHAN(1, ADS1015_AIN1),
  267. ADS1015_V_CHAN(2, ADS1015_AIN2),
  268. ADS1015_V_CHAN(3, ADS1015_AIN3),
  269. IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
  270. };
  271. static const struct iio_chan_spec ads1115_channels[] = {
  272. ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
  273. ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
  274. ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
  275. ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
  276. ADS1115_V_CHAN(0, ADS1015_AIN0),
  277. ADS1115_V_CHAN(1, ADS1015_AIN1),
  278. ADS1115_V_CHAN(2, ADS1015_AIN2),
  279. ADS1115_V_CHAN(3, ADS1015_AIN3),
  280. IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
  281. };
  282. #ifdef CONFIG_PM
  283. static int ads1015_set_power_state(struct ads1015_data *data, bool on)
  284. {
  285. int ret;
  286. struct device *dev = regmap_get_device(data->regmap);
  287. if (on) {
  288. ret = pm_runtime_get_sync(dev);
  289. if (ret < 0)
  290. pm_runtime_put_noidle(dev);
  291. } else {
  292. pm_runtime_mark_last_busy(dev);
  293. ret = pm_runtime_put_autosuspend(dev);
  294. }
  295. return ret < 0 ? ret : 0;
  296. }
  297. #else /* !CONFIG_PM */
  298. static int ads1015_set_power_state(struct ads1015_data *data, bool on)
  299. {
  300. return 0;
  301. }
  302. #endif /* !CONFIG_PM */
  303. static
  304. int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
  305. {
  306. int ret, pga, dr, dr_old, conv_time;
  307. unsigned int old, mask, cfg;
  308. if (chan < 0 || chan >= ADS1015_CHANNELS)
  309. return -EINVAL;
  310. ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
  311. if (ret)
  312. return ret;
  313. pga = data->channel_data[chan].pga;
  314. dr = data->channel_data[chan].data_rate;
  315. mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
  316. ADS1015_CFG_DR_MASK;
  317. cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
  318. dr << ADS1015_CFG_DR_SHIFT;
  319. if (ads1015_event_channel_enabled(data)) {
  320. mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
  321. cfg |= data->thresh_data[chan].comp_queue <<
  322. ADS1015_CFG_COMP_QUE_SHIFT |
  323. data->comp_mode <<
  324. ADS1015_CFG_COMP_MODE_SHIFT;
  325. }
  326. cfg = (old & ~mask) | (cfg & mask);
  327. if (old != cfg) {
  328. ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
  329. if (ret)
  330. return ret;
  331. data->conv_invalid = true;
  332. }
  333. if (data->conv_invalid) {
  334. dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
  335. conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
  336. conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
  337. conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
  338. usleep_range(conv_time, conv_time + 1);
  339. data->conv_invalid = false;
  340. }
  341. return regmap_read(data->regmap, ADS1015_CONV_REG, val);
  342. }
  343. static irqreturn_t ads1015_trigger_handler(int irq, void *p)
  344. {
  345. struct iio_poll_func *pf = p;
  346. struct iio_dev *indio_dev = pf->indio_dev;
  347. struct ads1015_data *data = iio_priv(indio_dev);
  348. /* Ensure natural alignment of timestamp */
  349. struct {
  350. s16 chan;
  351. s64 timestamp __aligned(8);
  352. } scan;
  353. int chan, ret, res;
  354. memset(&scan, 0, sizeof(scan));
  355. mutex_lock(&data->lock);
  356. chan = find_first_bit(indio_dev->active_scan_mask,
  357. indio_dev->masklength);
  358. ret = ads1015_get_adc_result(data, chan, &res);
  359. if (ret < 0) {
  360. mutex_unlock(&data->lock);
  361. goto err;
  362. }
  363. scan.chan = res;
  364. mutex_unlock(&data->lock);
  365. iio_push_to_buffers_with_timestamp(indio_dev, &scan,
  366. iio_get_time_ns(indio_dev));
  367. err:
  368. iio_trigger_notify_done(indio_dev->trig);
  369. return IRQ_HANDLED;
  370. }
  371. static int ads1015_set_scale(struct ads1015_data *data,
  372. struct iio_chan_spec const *chan,
  373. int scale, int uscale)
  374. {
  375. int i;
  376. int fullscale = div_s64((scale * 1000000LL + uscale) <<
  377. (chan->scan_type.realbits - 1), 1000000);
  378. for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
  379. if (ads1015_fullscale_range[i] == fullscale) {
  380. data->channel_data[chan->address].pga = i;
  381. return 0;
  382. }
  383. }
  384. return -EINVAL;
  385. }
  386. static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
  387. {
  388. int i;
  389. for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
  390. if (data->data_rate[i] == rate) {
  391. data->channel_data[chan].data_rate = i;
  392. return 0;
  393. }
  394. }
  395. return -EINVAL;
  396. }
  397. static int ads1015_read_raw(struct iio_dev *indio_dev,
  398. struct iio_chan_spec const *chan, int *val,
  399. int *val2, long mask)
  400. {
  401. int ret, idx;
  402. struct ads1015_data *data = iio_priv(indio_dev);
  403. mutex_lock(&data->lock);
  404. switch (mask) {
  405. case IIO_CHAN_INFO_RAW: {
  406. int shift = chan->scan_type.shift;
  407. ret = iio_device_claim_direct_mode(indio_dev);
  408. if (ret)
  409. break;
  410. if (ads1015_event_channel_enabled(data) &&
  411. data->event_channel != chan->address) {
  412. ret = -EBUSY;
  413. goto release_direct;
  414. }
  415. ret = ads1015_set_power_state(data, true);
  416. if (ret < 0)
  417. goto release_direct;
  418. ret = ads1015_get_adc_result(data, chan->address, val);
  419. if (ret < 0) {
  420. ads1015_set_power_state(data, false);
  421. goto release_direct;
  422. }
  423. *val = sign_extend32(*val >> shift, 15 - shift);
  424. ret = ads1015_set_power_state(data, false);
  425. if (ret < 0)
  426. goto release_direct;
  427. ret = IIO_VAL_INT;
  428. release_direct:
  429. iio_device_release_direct_mode(indio_dev);
  430. break;
  431. }
  432. case IIO_CHAN_INFO_SCALE:
  433. idx = data->channel_data[chan->address].pga;
  434. *val = ads1015_fullscale_range[idx];
  435. *val2 = chan->scan_type.realbits - 1;
  436. ret = IIO_VAL_FRACTIONAL_LOG2;
  437. break;
  438. case IIO_CHAN_INFO_SAMP_FREQ:
  439. idx = data->channel_data[chan->address].data_rate;
  440. *val = data->data_rate[idx];
  441. ret = IIO_VAL_INT;
  442. break;
  443. default:
  444. ret = -EINVAL;
  445. break;
  446. }
  447. mutex_unlock(&data->lock);
  448. return ret;
  449. }
  450. static int ads1015_write_raw(struct iio_dev *indio_dev,
  451. struct iio_chan_spec const *chan, int val,
  452. int val2, long mask)
  453. {
  454. struct ads1015_data *data = iio_priv(indio_dev);
  455. int ret;
  456. mutex_lock(&data->lock);
  457. switch (mask) {
  458. case IIO_CHAN_INFO_SCALE:
  459. ret = ads1015_set_scale(data, chan, val, val2);
  460. break;
  461. case IIO_CHAN_INFO_SAMP_FREQ:
  462. ret = ads1015_set_data_rate(data, chan->address, val);
  463. break;
  464. default:
  465. ret = -EINVAL;
  466. break;
  467. }
  468. mutex_unlock(&data->lock);
  469. return ret;
  470. }
  471. static int ads1015_read_event(struct iio_dev *indio_dev,
  472. const struct iio_chan_spec *chan, enum iio_event_type type,
  473. enum iio_event_direction dir, enum iio_event_info info, int *val,
  474. int *val2)
  475. {
  476. struct ads1015_data *data = iio_priv(indio_dev);
  477. int ret;
  478. unsigned int comp_queue;
  479. int period;
  480. int dr;
  481. mutex_lock(&data->lock);
  482. switch (info) {
  483. case IIO_EV_INFO_VALUE:
  484. *val = (dir == IIO_EV_DIR_RISING) ?
  485. data->thresh_data[chan->address].high_thresh :
  486. data->thresh_data[chan->address].low_thresh;
  487. ret = IIO_VAL_INT;
  488. break;
  489. case IIO_EV_INFO_PERIOD:
  490. dr = data->channel_data[chan->address].data_rate;
  491. comp_queue = data->thresh_data[chan->address].comp_queue;
  492. period = ads1015_comp_queue[comp_queue] *
  493. USEC_PER_SEC / data->data_rate[dr];
  494. *val = period / USEC_PER_SEC;
  495. *val2 = period % USEC_PER_SEC;
  496. ret = IIO_VAL_INT_PLUS_MICRO;
  497. break;
  498. default:
  499. ret = -EINVAL;
  500. break;
  501. }
  502. mutex_unlock(&data->lock);
  503. return ret;
  504. }
  505. static int ads1015_write_event(struct iio_dev *indio_dev,
  506. const struct iio_chan_spec *chan, enum iio_event_type type,
  507. enum iio_event_direction dir, enum iio_event_info info, int val,
  508. int val2)
  509. {
  510. struct ads1015_data *data = iio_priv(indio_dev);
  511. int realbits = chan->scan_type.realbits;
  512. int ret = 0;
  513. long long period;
  514. int i;
  515. int dr;
  516. mutex_lock(&data->lock);
  517. switch (info) {
  518. case IIO_EV_INFO_VALUE:
  519. if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
  520. ret = -EINVAL;
  521. break;
  522. }
  523. if (dir == IIO_EV_DIR_RISING)
  524. data->thresh_data[chan->address].high_thresh = val;
  525. else
  526. data->thresh_data[chan->address].low_thresh = val;
  527. break;
  528. case IIO_EV_INFO_PERIOD:
  529. dr = data->channel_data[chan->address].data_rate;
  530. period = val * USEC_PER_SEC + val2;
  531. for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
  532. if (period <= ads1015_comp_queue[i] *
  533. USEC_PER_SEC / data->data_rate[dr])
  534. break;
  535. }
  536. data->thresh_data[chan->address].comp_queue = i;
  537. break;
  538. default:
  539. ret = -EINVAL;
  540. break;
  541. }
  542. mutex_unlock(&data->lock);
  543. return ret;
  544. }
  545. static int ads1015_read_event_config(struct iio_dev *indio_dev,
  546. const struct iio_chan_spec *chan, enum iio_event_type type,
  547. enum iio_event_direction dir)
  548. {
  549. struct ads1015_data *data = iio_priv(indio_dev);
  550. int ret = 0;
  551. mutex_lock(&data->lock);
  552. if (data->event_channel == chan->address) {
  553. switch (dir) {
  554. case IIO_EV_DIR_RISING:
  555. ret = 1;
  556. break;
  557. case IIO_EV_DIR_EITHER:
  558. ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
  559. break;
  560. default:
  561. ret = -EINVAL;
  562. break;
  563. }
  564. }
  565. mutex_unlock(&data->lock);
  566. return ret;
  567. }
  568. static int ads1015_enable_event_config(struct ads1015_data *data,
  569. const struct iio_chan_spec *chan, int comp_mode)
  570. {
  571. int low_thresh = data->thresh_data[chan->address].low_thresh;
  572. int high_thresh = data->thresh_data[chan->address].high_thresh;
  573. int ret;
  574. unsigned int val;
  575. if (ads1015_event_channel_enabled(data)) {
  576. if (data->event_channel != chan->address ||
  577. (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
  578. comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
  579. return -EBUSY;
  580. return 0;
  581. }
  582. if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
  583. low_thresh = max(-1 << (chan->scan_type.realbits - 1),
  584. high_thresh - 1);
  585. }
  586. ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
  587. low_thresh << chan->scan_type.shift);
  588. if (ret)
  589. return ret;
  590. ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
  591. high_thresh << chan->scan_type.shift);
  592. if (ret)
  593. return ret;
  594. ret = ads1015_set_power_state(data, true);
  595. if (ret < 0)
  596. return ret;
  597. ads1015_event_channel_enable(data, chan->address, comp_mode);
  598. ret = ads1015_get_adc_result(data, chan->address, &val);
  599. if (ret) {
  600. ads1015_event_channel_disable(data, chan->address);
  601. ads1015_set_power_state(data, false);
  602. }
  603. return ret;
  604. }
  605. static int ads1015_disable_event_config(struct ads1015_data *data,
  606. const struct iio_chan_spec *chan, int comp_mode)
  607. {
  608. int ret;
  609. if (!ads1015_event_channel_enabled(data))
  610. return 0;
  611. if (data->event_channel != chan->address)
  612. return 0;
  613. if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
  614. comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
  615. return 0;
  616. ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  617. ADS1015_CFG_COMP_QUE_MASK,
  618. ADS1015_CFG_COMP_DISABLE <<
  619. ADS1015_CFG_COMP_QUE_SHIFT);
  620. if (ret)
  621. return ret;
  622. ads1015_event_channel_disable(data, chan->address);
  623. return ads1015_set_power_state(data, false);
  624. }
  625. static int ads1015_write_event_config(struct iio_dev *indio_dev,
  626. const struct iio_chan_spec *chan, enum iio_event_type type,
  627. enum iio_event_direction dir, int state)
  628. {
  629. struct ads1015_data *data = iio_priv(indio_dev);
  630. int ret;
  631. int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
  632. ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
  633. mutex_lock(&data->lock);
  634. /* Prevent from enabling both buffer and event at a time */
  635. ret = iio_device_claim_direct_mode(indio_dev);
  636. if (ret) {
  637. mutex_unlock(&data->lock);
  638. return ret;
  639. }
  640. if (state)
  641. ret = ads1015_enable_event_config(data, chan, comp_mode);
  642. else
  643. ret = ads1015_disable_event_config(data, chan, comp_mode);
  644. iio_device_release_direct_mode(indio_dev);
  645. mutex_unlock(&data->lock);
  646. return ret;
  647. }
  648. static irqreturn_t ads1015_event_handler(int irq, void *priv)
  649. {
  650. struct iio_dev *indio_dev = priv;
  651. struct ads1015_data *data = iio_priv(indio_dev);
  652. int val;
  653. int ret;
  654. /* Clear the latched ALERT/RDY pin */
  655. ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
  656. if (ret)
  657. return IRQ_HANDLED;
  658. if (ads1015_event_channel_enabled(data)) {
  659. enum iio_event_direction dir;
  660. u64 code;
  661. dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
  662. IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
  663. code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
  664. IIO_EV_TYPE_THRESH, dir);
  665. iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
  666. }
  667. return IRQ_HANDLED;
  668. }
  669. static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
  670. {
  671. struct ads1015_data *data = iio_priv(indio_dev);
  672. /* Prevent from enabling both buffer and event at a time */
  673. if (ads1015_event_channel_enabled(data))
  674. return -EBUSY;
  675. return ads1015_set_power_state(iio_priv(indio_dev), true);
  676. }
  677. static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
  678. {
  679. return ads1015_set_power_state(iio_priv(indio_dev), false);
  680. }
  681. static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
  682. .preenable = ads1015_buffer_preenable,
  683. .postdisable = ads1015_buffer_postdisable,
  684. .validate_scan_mask = &iio_validate_scan_mask_onehot,
  685. };
  686. static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
  687. "3 2 1 0.5 0.25 0.125");
  688. static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
  689. "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
  690. static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
  691. sampling_frequency_available, "128 250 490 920 1600 2400 3300");
  692. static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
  693. sampling_frequency_available, "8 16 32 64 128 250 475 860");
  694. static struct attribute *ads1015_attributes[] = {
  695. &iio_const_attr_ads1015_scale_available.dev_attr.attr,
  696. &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
  697. NULL,
  698. };
  699. static const struct attribute_group ads1015_attribute_group = {
  700. .attrs = ads1015_attributes,
  701. };
  702. static struct attribute *ads1115_attributes[] = {
  703. &iio_const_attr_ads1115_scale_available.dev_attr.attr,
  704. &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
  705. NULL,
  706. };
  707. static const struct attribute_group ads1115_attribute_group = {
  708. .attrs = ads1115_attributes,
  709. };
  710. static const struct iio_info ads1015_info = {
  711. .read_raw = ads1015_read_raw,
  712. .write_raw = ads1015_write_raw,
  713. .read_event_value = ads1015_read_event,
  714. .write_event_value = ads1015_write_event,
  715. .read_event_config = ads1015_read_event_config,
  716. .write_event_config = ads1015_write_event_config,
  717. .attrs = &ads1015_attribute_group,
  718. };
  719. static const struct iio_info ads1115_info = {
  720. .read_raw = ads1015_read_raw,
  721. .write_raw = ads1015_write_raw,
  722. .read_event_value = ads1015_read_event,
  723. .write_event_value = ads1015_write_event,
  724. .read_event_config = ads1015_read_event_config,
  725. .write_event_config = ads1015_write_event_config,
  726. .attrs = &ads1115_attribute_group,
  727. };
  728. static int ads1015_client_get_channels_config(struct i2c_client *client)
  729. {
  730. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  731. struct ads1015_data *data = iio_priv(indio_dev);
  732. struct device *dev = &client->dev;
  733. struct fwnode_handle *node;
  734. int i = -1;
  735. device_for_each_child_node(dev, node) {
  736. u32 pval;
  737. unsigned int channel;
  738. unsigned int pga = ADS1015_DEFAULT_PGA;
  739. unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
  740. if (fwnode_property_read_u32(node, "reg", &pval)) {
  741. dev_err(dev, "invalid reg on %pfw\n", node);
  742. continue;
  743. }
  744. channel = pval;
  745. if (channel >= ADS1015_CHANNELS) {
  746. dev_err(dev, "invalid channel index %d on %pfw\n",
  747. channel, node);
  748. continue;
  749. }
  750. if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
  751. pga = pval;
  752. if (pga > 6) {
  753. dev_err(dev, "invalid gain on %pfw\n", node);
  754. fwnode_handle_put(node);
  755. return -EINVAL;
  756. }
  757. }
  758. if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
  759. data_rate = pval;
  760. if (data_rate > 7) {
  761. dev_err(dev, "invalid data_rate on %pfw\n", node);
  762. fwnode_handle_put(node);
  763. return -EINVAL;
  764. }
  765. }
  766. data->channel_data[channel].pga = pga;
  767. data->channel_data[channel].data_rate = data_rate;
  768. i++;
  769. }
  770. return i < 0 ? -EINVAL : 0;
  771. }
  772. static void ads1015_get_channels_config(struct i2c_client *client)
  773. {
  774. unsigned int k;
  775. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  776. struct ads1015_data *data = iio_priv(indio_dev);
  777. if (!ads1015_client_get_channels_config(client))
  778. return;
  779. /* fallback on default configuration */
  780. for (k = 0; k < ADS1015_CHANNELS; ++k) {
  781. data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
  782. data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
  783. }
  784. }
  785. static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
  786. {
  787. return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  788. ADS1015_CFG_MOD_MASK,
  789. mode << ADS1015_CFG_MOD_SHIFT);
  790. }
  791. static int ads1015_probe(struct i2c_client *client,
  792. const struct i2c_device_id *id)
  793. {
  794. struct iio_dev *indio_dev;
  795. struct ads1015_data *data;
  796. int ret;
  797. enum chip_ids chip;
  798. int i;
  799. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  800. if (!indio_dev)
  801. return -ENOMEM;
  802. data = iio_priv(indio_dev);
  803. i2c_set_clientdata(client, indio_dev);
  804. mutex_init(&data->lock);
  805. indio_dev->name = ADS1015_DRV_NAME;
  806. indio_dev->modes = INDIO_DIRECT_MODE;
  807. chip = (enum chip_ids)device_get_match_data(&client->dev);
  808. if (chip == ADSXXXX)
  809. chip = id->driver_data;
  810. switch (chip) {
  811. case ADS1015:
  812. indio_dev->channels = ads1015_channels;
  813. indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
  814. indio_dev->info = &ads1015_info;
  815. data->data_rate = (unsigned int *) &ads1015_data_rate;
  816. break;
  817. case ADS1115:
  818. indio_dev->channels = ads1115_channels;
  819. indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
  820. indio_dev->info = &ads1115_info;
  821. data->data_rate = (unsigned int *) &ads1115_data_rate;
  822. break;
  823. default:
  824. dev_err(&client->dev, "Unknown chip %d\n", chip);
  825. return -EINVAL;
  826. }
  827. data->event_channel = ADS1015_CHANNELS;
  828. /*
  829. * Set default lower and upper threshold to min and max value
  830. * respectively.
  831. */
  832. for (i = 0; i < ADS1015_CHANNELS; i++) {
  833. int realbits = indio_dev->channels[i].scan_type.realbits;
  834. data->thresh_data[i].low_thresh = -1 << (realbits - 1);
  835. data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
  836. }
  837. /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
  838. ads1015_get_channels_config(client);
  839. data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
  840. if (IS_ERR(data->regmap)) {
  841. dev_err(&client->dev, "Failed to allocate register map\n");
  842. return PTR_ERR(data->regmap);
  843. }
  844. ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
  845. ads1015_trigger_handler,
  846. &ads1015_buffer_setup_ops);
  847. if (ret < 0) {
  848. dev_err(&client->dev, "iio triggered buffer setup failed\n");
  849. return ret;
  850. }
  851. if (client->irq) {
  852. unsigned long irq_trig =
  853. irqd_get_trigger_type(irq_get_irq_data(client->irq));
  854. unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
  855. ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
  856. unsigned int cfg_comp =
  857. ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
  858. 1 << ADS1015_CFG_COMP_LAT_SHIFT;
  859. switch (irq_trig) {
  860. case IRQF_TRIGGER_LOW:
  861. cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
  862. ADS1015_CFG_COMP_POL_SHIFT;
  863. break;
  864. case IRQF_TRIGGER_HIGH:
  865. cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
  866. ADS1015_CFG_COMP_POL_SHIFT;
  867. break;
  868. default:
  869. return -EINVAL;
  870. }
  871. ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  872. cfg_comp_mask, cfg_comp);
  873. if (ret)
  874. return ret;
  875. ret = devm_request_threaded_irq(&client->dev, client->irq,
  876. NULL, ads1015_event_handler,
  877. irq_trig | IRQF_ONESHOT,
  878. client->name, indio_dev);
  879. if (ret)
  880. return ret;
  881. }
  882. ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
  883. if (ret)
  884. return ret;
  885. data->conv_invalid = true;
  886. ret = pm_runtime_set_active(&client->dev);
  887. if (ret)
  888. return ret;
  889. pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
  890. pm_runtime_use_autosuspend(&client->dev);
  891. pm_runtime_enable(&client->dev);
  892. ret = iio_device_register(indio_dev);
  893. if (ret < 0) {
  894. dev_err(&client->dev, "Failed to register IIO device\n");
  895. return ret;
  896. }
  897. return 0;
  898. }
  899. static int ads1015_remove(struct i2c_client *client)
  900. {
  901. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  902. struct ads1015_data *data = iio_priv(indio_dev);
  903. iio_device_unregister(indio_dev);
  904. pm_runtime_disable(&client->dev);
  905. pm_runtime_set_suspended(&client->dev);
  906. pm_runtime_put_noidle(&client->dev);
  907. /* power down single shot mode */
  908. return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
  909. }
  910. #ifdef CONFIG_PM
  911. static int ads1015_runtime_suspend(struct device *dev)
  912. {
  913. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  914. struct ads1015_data *data = iio_priv(indio_dev);
  915. return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
  916. }
  917. static int ads1015_runtime_resume(struct device *dev)
  918. {
  919. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  920. struct ads1015_data *data = iio_priv(indio_dev);
  921. int ret;
  922. ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
  923. if (!ret)
  924. data->conv_invalid = true;
  925. return ret;
  926. }
  927. #endif
  928. static const struct dev_pm_ops ads1015_pm_ops = {
  929. SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
  930. ads1015_runtime_resume, NULL)
  931. };
  932. static const struct i2c_device_id ads1015_id[] = {
  933. {"ads1015", ADS1015},
  934. {"ads1115", ADS1115},
  935. {}
  936. };
  937. MODULE_DEVICE_TABLE(i2c, ads1015_id);
  938. static const struct of_device_id ads1015_of_match[] = {
  939. {
  940. .compatible = "ti,ads1015",
  941. .data = (void *)ADS1015
  942. },
  943. {
  944. .compatible = "ti,ads1115",
  945. .data = (void *)ADS1115
  946. },
  947. {}
  948. };
  949. MODULE_DEVICE_TABLE(of, ads1015_of_match);
  950. static struct i2c_driver ads1015_driver = {
  951. .driver = {
  952. .name = ADS1015_DRV_NAME,
  953. .of_match_table = ads1015_of_match,
  954. .pm = &ads1015_pm_ops,
  955. },
  956. .probe = ads1015_probe,
  957. .remove = ads1015_remove,
  958. .id_table = ads1015_id,
  959. };
  960. module_i2c_driver(ads1015_driver);
  961. MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
  962. MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
  963. MODULE_LICENSE("GPL v2");