ti-adc12138.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ADC12130/ADC12132/ADC12138 12-bit plus sign ADC driver
  4. *
  5. * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
  6. *
  7. * Datasheet: http://www.ti.com/lit/ds/symlink/adc12138.pdf
  8. */
  9. #include <linux/module.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/completion.h>
  12. #include <linux/clk.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/iio/iio.h>
  15. #include <linux/iio/buffer.h>
  16. #include <linux/iio/trigger.h>
  17. #include <linux/iio/triggered_buffer.h>
  18. #include <linux/iio/trigger_consumer.h>
  19. #include <linux/regulator/consumer.h>
  20. #define ADC12138_MODE_AUTO_CAL 0x08
  21. #define ADC12138_MODE_READ_STATUS 0x0c
  22. #define ADC12138_MODE_ACQUISITION_TIME_6 0x0e
  23. #define ADC12138_MODE_ACQUISITION_TIME_10 0x4e
  24. #define ADC12138_MODE_ACQUISITION_TIME_18 0x8e
  25. #define ADC12138_MODE_ACQUISITION_TIME_34 0xce
  26. #define ADC12138_STATUS_CAL BIT(6)
  27. enum {
  28. adc12130,
  29. adc12132,
  30. adc12138,
  31. };
  32. struct adc12138 {
  33. struct spi_device *spi;
  34. unsigned int id;
  35. /* conversion clock */
  36. struct clk *cclk;
  37. /* positive analog voltage reference */
  38. struct regulator *vref_p;
  39. /* negative analog voltage reference */
  40. struct regulator *vref_n;
  41. struct mutex lock;
  42. struct completion complete;
  43. /* The number of cclk periods for the S/H's acquisition time */
  44. unsigned int acquisition_time;
  45. /*
  46. * Maximum size needed: 16x 2 bytes ADC data + 8 bytes timestamp.
  47. * Less may be need if not all channels are enabled, as long as
  48. * the 8 byte alignment of the timestamp is maintained.
  49. */
  50. __be16 data[20] __aligned(8);
  51. u8 tx_buf[2] ____cacheline_aligned;
  52. u8 rx_buf[2];
  53. };
  54. #define ADC12138_VOLTAGE_CHANNEL(chan) \
  55. { \
  56. .type = IIO_VOLTAGE, \
  57. .indexed = 1, \
  58. .channel = chan, \
  59. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  60. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
  61. | BIT(IIO_CHAN_INFO_OFFSET), \
  62. .scan_index = chan, \
  63. .scan_type = { \
  64. .sign = 's', \
  65. .realbits = 13, \
  66. .storagebits = 16, \
  67. .shift = 3, \
  68. .endianness = IIO_BE, \
  69. }, \
  70. }
  71. #define ADC12138_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \
  72. { \
  73. .type = IIO_VOLTAGE, \
  74. .indexed = 1, \
  75. .channel = (chan1), \
  76. .channel2 = (chan2), \
  77. .differential = 1, \
  78. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  79. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
  80. | BIT(IIO_CHAN_INFO_OFFSET), \
  81. .scan_index = si, \
  82. .scan_type = { \
  83. .sign = 's', \
  84. .realbits = 13, \
  85. .storagebits = 16, \
  86. .shift = 3, \
  87. .endianness = IIO_BE, \
  88. }, \
  89. }
  90. static const struct iio_chan_spec adc12132_channels[] = {
  91. ADC12138_VOLTAGE_CHANNEL(0),
  92. ADC12138_VOLTAGE_CHANNEL(1),
  93. ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 2),
  94. ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 3),
  95. IIO_CHAN_SOFT_TIMESTAMP(4),
  96. };
  97. static const struct iio_chan_spec adc12138_channels[] = {
  98. ADC12138_VOLTAGE_CHANNEL(0),
  99. ADC12138_VOLTAGE_CHANNEL(1),
  100. ADC12138_VOLTAGE_CHANNEL(2),
  101. ADC12138_VOLTAGE_CHANNEL(3),
  102. ADC12138_VOLTAGE_CHANNEL(4),
  103. ADC12138_VOLTAGE_CHANNEL(5),
  104. ADC12138_VOLTAGE_CHANNEL(6),
  105. ADC12138_VOLTAGE_CHANNEL(7),
  106. ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
  107. ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 9),
  108. ADC12138_VOLTAGE_CHANNEL_DIFF(2, 3, 10),
  109. ADC12138_VOLTAGE_CHANNEL_DIFF(3, 2, 11),
  110. ADC12138_VOLTAGE_CHANNEL_DIFF(4, 5, 12),
  111. ADC12138_VOLTAGE_CHANNEL_DIFF(5, 4, 13),
  112. ADC12138_VOLTAGE_CHANNEL_DIFF(6, 7, 14),
  113. ADC12138_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
  114. IIO_CHAN_SOFT_TIMESTAMP(16),
  115. };
  116. static int adc12138_mode_programming(struct adc12138 *adc, u8 mode,
  117. void *rx_buf, int len)
  118. {
  119. struct spi_transfer xfer = {
  120. .tx_buf = adc->tx_buf,
  121. .rx_buf = adc->rx_buf,
  122. .len = len,
  123. };
  124. int ret;
  125. /* Skip unused bits for ADC12130 and ADC12132 */
  126. if (adc->id != adc12138)
  127. mode = (mode & 0xc0) | ((mode & 0x0f) << 2);
  128. adc->tx_buf[0] = mode;
  129. ret = spi_sync_transfer(adc->spi, &xfer, 1);
  130. if (ret)
  131. return ret;
  132. memcpy(rx_buf, adc->rx_buf, len);
  133. return 0;
  134. }
  135. static int adc12138_read_status(struct adc12138 *adc)
  136. {
  137. u8 rx_buf[2];
  138. int ret;
  139. ret = adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,
  140. rx_buf, 2);
  141. if (ret)
  142. return ret;
  143. return (rx_buf[0] << 1) | (rx_buf[1] >> 7);
  144. }
  145. static int __adc12138_start_conv(struct adc12138 *adc,
  146. struct iio_chan_spec const *channel,
  147. void *data, int len)
  148. {
  149. static const u8 ch_to_mux[] = { 0, 4, 1, 5, 2, 6, 3, 7 };
  150. u8 mode = (ch_to_mux[channel->channel] << 4) |
  151. (channel->differential ? 0 : 0x80);
  152. return adc12138_mode_programming(adc, mode, data, len);
  153. }
  154. static int adc12138_start_conv(struct adc12138 *adc,
  155. struct iio_chan_spec const *channel)
  156. {
  157. u8 trash;
  158. return __adc12138_start_conv(adc, channel, &trash, 1);
  159. }
  160. static int adc12138_start_and_read_conv(struct adc12138 *adc,
  161. struct iio_chan_spec const *channel,
  162. __be16 *data)
  163. {
  164. return __adc12138_start_conv(adc, channel, data, 2);
  165. }
  166. static int adc12138_read_conv_data(struct adc12138 *adc, __be16 *value)
  167. {
  168. /* Issue a read status instruction and read previous conversion data */
  169. return adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,
  170. value, sizeof(*value));
  171. }
  172. static int adc12138_wait_eoc(struct adc12138 *adc, unsigned long timeout)
  173. {
  174. if (!wait_for_completion_timeout(&adc->complete, timeout))
  175. return -ETIMEDOUT;
  176. return 0;
  177. }
  178. static int adc12138_adc_conversion(struct adc12138 *adc,
  179. struct iio_chan_spec const *channel,
  180. __be16 *value)
  181. {
  182. int ret;
  183. reinit_completion(&adc->complete);
  184. ret = adc12138_start_conv(adc, channel);
  185. if (ret)
  186. return ret;
  187. ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));
  188. if (ret)
  189. return ret;
  190. return adc12138_read_conv_data(adc, value);
  191. }
  192. static int adc12138_read_raw(struct iio_dev *iio,
  193. struct iio_chan_spec const *channel, int *value,
  194. int *shift, long mask)
  195. {
  196. struct adc12138 *adc = iio_priv(iio);
  197. int ret;
  198. __be16 data;
  199. switch (mask) {
  200. case IIO_CHAN_INFO_RAW:
  201. mutex_lock(&adc->lock);
  202. ret = adc12138_adc_conversion(adc, channel, &data);
  203. mutex_unlock(&adc->lock);
  204. if (ret)
  205. return ret;
  206. *value = sign_extend32(be16_to_cpu(data) >> 3, 12);
  207. return IIO_VAL_INT;
  208. case IIO_CHAN_INFO_SCALE:
  209. ret = regulator_get_voltage(adc->vref_p);
  210. if (ret < 0)
  211. return ret;
  212. *value = ret;
  213. if (!IS_ERR(adc->vref_n)) {
  214. ret = regulator_get_voltage(adc->vref_n);
  215. if (ret < 0)
  216. return ret;
  217. *value -= ret;
  218. }
  219. /* convert regulator output voltage to mV */
  220. *value /= 1000;
  221. *shift = channel->scan_type.realbits - 1;
  222. return IIO_VAL_FRACTIONAL_LOG2;
  223. case IIO_CHAN_INFO_OFFSET:
  224. if (!IS_ERR(adc->vref_n)) {
  225. *value = regulator_get_voltage(adc->vref_n);
  226. if (*value < 0)
  227. return *value;
  228. } else {
  229. *value = 0;
  230. }
  231. /* convert regulator output voltage to mV */
  232. *value /= 1000;
  233. return IIO_VAL_INT;
  234. }
  235. return -EINVAL;
  236. }
  237. static const struct iio_info adc12138_info = {
  238. .read_raw = adc12138_read_raw,
  239. };
  240. static int adc12138_init(struct adc12138 *adc)
  241. {
  242. int ret;
  243. int status;
  244. u8 mode;
  245. u8 trash;
  246. reinit_completion(&adc->complete);
  247. ret = adc12138_mode_programming(adc, ADC12138_MODE_AUTO_CAL, &trash, 1);
  248. if (ret)
  249. return ret;
  250. /* data output at this time has no significance */
  251. status = adc12138_read_status(adc);
  252. if (status < 0)
  253. return status;
  254. adc12138_wait_eoc(adc, msecs_to_jiffies(100));
  255. status = adc12138_read_status(adc);
  256. if (status & ADC12138_STATUS_CAL) {
  257. dev_warn(&adc->spi->dev,
  258. "Auto Cal sequence is still in progress: %#x\n",
  259. status);
  260. return -EIO;
  261. }
  262. switch (adc->acquisition_time) {
  263. case 6:
  264. mode = ADC12138_MODE_ACQUISITION_TIME_6;
  265. break;
  266. case 10:
  267. mode = ADC12138_MODE_ACQUISITION_TIME_10;
  268. break;
  269. case 18:
  270. mode = ADC12138_MODE_ACQUISITION_TIME_18;
  271. break;
  272. case 34:
  273. mode = ADC12138_MODE_ACQUISITION_TIME_34;
  274. break;
  275. default:
  276. return -EINVAL;
  277. }
  278. return adc12138_mode_programming(adc, mode, &trash, 1);
  279. }
  280. static irqreturn_t adc12138_trigger_handler(int irq, void *p)
  281. {
  282. struct iio_poll_func *pf = p;
  283. struct iio_dev *indio_dev = pf->indio_dev;
  284. struct adc12138 *adc = iio_priv(indio_dev);
  285. __be16 trash;
  286. int ret;
  287. int scan_index;
  288. int i = 0;
  289. mutex_lock(&adc->lock);
  290. for_each_set_bit(scan_index, indio_dev->active_scan_mask,
  291. indio_dev->masklength) {
  292. const struct iio_chan_spec *scan_chan =
  293. &indio_dev->channels[scan_index];
  294. reinit_completion(&adc->complete);
  295. ret = adc12138_start_and_read_conv(adc, scan_chan,
  296. i ? &adc->data[i - 1] : &trash);
  297. if (ret) {
  298. dev_warn(&adc->spi->dev,
  299. "failed to start conversion\n");
  300. goto out;
  301. }
  302. ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));
  303. if (ret) {
  304. dev_warn(&adc->spi->dev, "wait eoc timeout\n");
  305. goto out;
  306. }
  307. i++;
  308. }
  309. if (i) {
  310. ret = adc12138_read_conv_data(adc, &adc->data[i - 1]);
  311. if (ret) {
  312. dev_warn(&adc->spi->dev,
  313. "failed to get conversion data\n");
  314. goto out;
  315. }
  316. }
  317. iio_push_to_buffers_with_timestamp(indio_dev, adc->data,
  318. iio_get_time_ns(indio_dev));
  319. out:
  320. mutex_unlock(&adc->lock);
  321. iio_trigger_notify_done(indio_dev->trig);
  322. return IRQ_HANDLED;
  323. }
  324. static irqreturn_t adc12138_eoc_handler(int irq, void *p)
  325. {
  326. struct iio_dev *indio_dev = p;
  327. struct adc12138 *adc = iio_priv(indio_dev);
  328. complete(&adc->complete);
  329. return IRQ_HANDLED;
  330. }
  331. static int adc12138_probe(struct spi_device *spi)
  332. {
  333. struct iio_dev *indio_dev;
  334. struct adc12138 *adc;
  335. int ret;
  336. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
  337. if (!indio_dev)
  338. return -ENOMEM;
  339. adc = iio_priv(indio_dev);
  340. adc->spi = spi;
  341. adc->id = spi_get_device_id(spi)->driver_data;
  342. mutex_init(&adc->lock);
  343. init_completion(&adc->complete);
  344. indio_dev->name = spi_get_device_id(spi)->name;
  345. indio_dev->info = &adc12138_info;
  346. indio_dev->modes = INDIO_DIRECT_MODE;
  347. switch (adc->id) {
  348. case adc12130:
  349. case adc12132:
  350. indio_dev->channels = adc12132_channels;
  351. indio_dev->num_channels = ARRAY_SIZE(adc12132_channels);
  352. break;
  353. case adc12138:
  354. indio_dev->channels = adc12138_channels;
  355. indio_dev->num_channels = ARRAY_SIZE(adc12138_channels);
  356. break;
  357. default:
  358. return -EINVAL;
  359. }
  360. ret = of_property_read_u32(spi->dev.of_node, "ti,acquisition-time",
  361. &adc->acquisition_time);
  362. if (ret)
  363. adc->acquisition_time = 10;
  364. adc->cclk = devm_clk_get(&spi->dev, NULL);
  365. if (IS_ERR(adc->cclk))
  366. return PTR_ERR(adc->cclk);
  367. adc->vref_p = devm_regulator_get(&spi->dev, "vref-p");
  368. if (IS_ERR(adc->vref_p))
  369. return PTR_ERR(adc->vref_p);
  370. adc->vref_n = devm_regulator_get_optional(&spi->dev, "vref-n");
  371. if (IS_ERR(adc->vref_n)) {
  372. /*
  373. * Assume vref_n is 0V if an optional regulator is not
  374. * specified, otherwise return the error code.
  375. */
  376. ret = PTR_ERR(adc->vref_n);
  377. if (ret != -ENODEV)
  378. return ret;
  379. }
  380. ret = devm_request_irq(&spi->dev, spi->irq, adc12138_eoc_handler,
  381. IRQF_TRIGGER_RISING, indio_dev->name, indio_dev);
  382. if (ret)
  383. return ret;
  384. ret = clk_prepare_enable(adc->cclk);
  385. if (ret)
  386. return ret;
  387. ret = regulator_enable(adc->vref_p);
  388. if (ret)
  389. goto err_clk_disable;
  390. if (!IS_ERR(adc->vref_n)) {
  391. ret = regulator_enable(adc->vref_n);
  392. if (ret)
  393. goto err_vref_p_disable;
  394. }
  395. ret = adc12138_init(adc);
  396. if (ret)
  397. goto err_vref_n_disable;
  398. spi_set_drvdata(spi, indio_dev);
  399. ret = iio_triggered_buffer_setup(indio_dev, NULL,
  400. adc12138_trigger_handler, NULL);
  401. if (ret)
  402. goto err_vref_n_disable;
  403. ret = iio_device_register(indio_dev);
  404. if (ret)
  405. goto err_buffer_cleanup;
  406. return 0;
  407. err_buffer_cleanup:
  408. iio_triggered_buffer_cleanup(indio_dev);
  409. err_vref_n_disable:
  410. if (!IS_ERR(adc->vref_n))
  411. regulator_disable(adc->vref_n);
  412. err_vref_p_disable:
  413. regulator_disable(adc->vref_p);
  414. err_clk_disable:
  415. clk_disable_unprepare(adc->cclk);
  416. return ret;
  417. }
  418. static int adc12138_remove(struct spi_device *spi)
  419. {
  420. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  421. struct adc12138 *adc = iio_priv(indio_dev);
  422. iio_device_unregister(indio_dev);
  423. iio_triggered_buffer_cleanup(indio_dev);
  424. if (!IS_ERR(adc->vref_n))
  425. regulator_disable(adc->vref_n);
  426. regulator_disable(adc->vref_p);
  427. clk_disable_unprepare(adc->cclk);
  428. return 0;
  429. }
  430. #ifdef CONFIG_OF
  431. static const struct of_device_id adc12138_dt_ids[] = {
  432. { .compatible = "ti,adc12130", },
  433. { .compatible = "ti,adc12132", },
  434. { .compatible = "ti,adc12138", },
  435. {}
  436. };
  437. MODULE_DEVICE_TABLE(of, adc12138_dt_ids);
  438. #endif
  439. static const struct spi_device_id adc12138_id[] = {
  440. { "adc12130", adc12130 },
  441. { "adc12132", adc12132 },
  442. { "adc12138", adc12138 },
  443. {}
  444. };
  445. MODULE_DEVICE_TABLE(spi, adc12138_id);
  446. static struct spi_driver adc12138_driver = {
  447. .driver = {
  448. .name = "adc12138",
  449. .of_match_table = of_match_ptr(adc12138_dt_ids),
  450. },
  451. .probe = adc12138_probe,
  452. .remove = adc12138_remove,
  453. .id_table = adc12138_id,
  454. };
  455. module_spi_driver(adc12138_driver);
  456. MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
  457. MODULE_DESCRIPTION("ADC12130/ADC12132/ADC12138 driver");
  458. MODULE_LICENSE("GPL v2");