stm32-dfsdm.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * This file is part of STM32 DFSDM driver
  4. *
  5. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  6. * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>.
  7. */
  8. #ifndef MDF_STM32_DFSDM__H
  9. #define MDF_STM32_DFSDM__H
  10. #include <linux/bitfield.h>
  11. /*
  12. * STM32 DFSDM - global register map
  13. * ________________________________________________________
  14. * | Offset | Registers block |
  15. * --------------------------------------------------------
  16. * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
  17. * --------------------------------------------------------
  18. * | 0x020 | CHANNEL 1 |
  19. * --------------------------------------------------------
  20. * | ... | ..... |
  21. * --------------------------------------------------------
  22. * | 0x0E0 | CHANNEL 7 |
  23. * --------------------------------------------------------
  24. * | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
  25. * --------------------------------------------------------
  26. * | 0x200 | FILTER 1 |
  27. * --------------------------------------------------------
  28. * | 0x300 | FILTER 2 |
  29. * --------------------------------------------------------
  30. * | 0x400 | FILTER 3 |
  31. * --------------------------------------------------------
  32. */
  33. /*
  34. * Channels register definitions
  35. */
  36. #define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)
  37. #define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)
  38. #define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)
  39. #define DFSDM_CHWDATR(y) ((y) * 0x20 + 0x0C)
  40. #define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10)
  41. /* CHCFGR1: Channel configuration register 1 */
  42. #define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0)
  43. #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
  44. #define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)
  45. #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
  46. #define DFSDM_CHCFGR1_SCDEN_MASK BIT(5)
  47. #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
  48. #define DFSDM_CHCFGR1_CKABEN_MASK BIT(6)
  49. #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
  50. #define DFSDM_CHCFGR1_CHEN_MASK BIT(7)
  51. #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
  52. #define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8)
  53. #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
  54. #define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12)
  55. #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
  56. #define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)
  57. #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
  58. #define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)
  59. #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
  60. #define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30)
  61. #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
  62. #define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31)
  63. #define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)
  64. /* CHCFGR2: Channel configuration register 2 */
  65. #define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3)
  66. #define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)
  67. #define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8)
  68. #define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)
  69. /* AWSCDR: Channel analog watchdog and short circuit detector */
  70. #define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0)
  71. #define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)
  72. #define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12)
  73. #define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)
  74. #define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16)
  75. #define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)
  76. #define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22)
  77. #define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)
  78. /*
  79. * Filters register definitions
  80. */
  81. #define DFSDM_FILTER_BASE_ADR 0x100
  82. #define DFSDM_FILTER_REG_MASK 0x7F
  83. #define DFSDM_FILTER_X_BASE_ADR(x) ((x) * 0x80 + DFSDM_FILTER_BASE_ADR)
  84. #define DFSDM_CR1(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x00)
  85. #define DFSDM_CR2(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x04)
  86. #define DFSDM_ISR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x08)
  87. #define DFSDM_ICR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x0C)
  88. #define DFSDM_JCHGR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x10)
  89. #define DFSDM_FCR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x14)
  90. #define DFSDM_JDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x18)
  91. #define DFSDM_RDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x1C)
  92. #define DFSDM_AWHTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x20)
  93. #define DFSDM_AWLTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x24)
  94. #define DFSDM_AWSR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x28)
  95. #define DFSDM_AWCFR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x2C)
  96. #define DFSDM_EXMAX(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x30)
  97. #define DFSDM_EXMIN(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x34)
  98. #define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x38)
  99. /* CR1 Control register 1 */
  100. #define DFSDM_CR1_DFEN_MASK BIT(0)
  101. #define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
  102. #define DFSDM_CR1_JSWSTART_MASK BIT(1)
  103. #define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)
  104. #define DFSDM_CR1_JSYNC_MASK BIT(3)
  105. #define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)
  106. #define DFSDM_CR1_JSCAN_MASK BIT(4)
  107. #define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)
  108. #define DFSDM_CR1_JDMAEN_MASK BIT(5)
  109. #define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)
  110. #define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8)
  111. #define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)
  112. #define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13)
  113. #define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)
  114. #define DFSDM_CR1_RSWSTART_MASK BIT(17)
  115. #define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)
  116. #define DFSDM_CR1_RCONT_MASK BIT(18)
  117. #define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)
  118. #define DFSDM_CR1_RSYNC_MASK BIT(19)
  119. #define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)
  120. #define DFSDM_CR1_RDMAEN_MASK BIT(21)
  121. #define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)
  122. #define DFSDM_CR1_RCH_MASK GENMASK(26, 24)
  123. #define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
  124. #define DFSDM_CR1_FAST_MASK BIT(29)
  125. #define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
  126. #define DFSDM_CR1_AWFSEL_MASK BIT(30)
  127. #define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)
  128. /* CR2: Control register 2 */
  129. #define DFSDM_CR2_IE_MASK GENMASK(6, 0)
  130. #define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
  131. #define DFSDM_CR2_JEOCIE_MASK BIT(0)
  132. #define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)
  133. #define DFSDM_CR2_REOCIE_MASK BIT(1)
  134. #define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)
  135. #define DFSDM_CR2_JOVRIE_MASK BIT(2)
  136. #define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)
  137. #define DFSDM_CR2_ROVRIE_MASK BIT(3)
  138. #define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)
  139. #define DFSDM_CR2_AWDIE_MASK BIT(4)
  140. #define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)
  141. #define DFSDM_CR2_SCDIE_MASK BIT(5)
  142. #define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)
  143. #define DFSDM_CR2_CKABIE_MASK BIT(6)
  144. #define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)
  145. #define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)
  146. #define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
  147. #define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16)
  148. #define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)
  149. /* ISR: Interrupt status register */
  150. #define DFSDM_ISR_JEOCF_MASK BIT(0)
  151. #define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)
  152. #define DFSDM_ISR_REOCF_MASK BIT(1)
  153. #define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)
  154. #define DFSDM_ISR_JOVRF_MASK BIT(2)
  155. #define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)
  156. #define DFSDM_ISR_ROVRF_MASK BIT(3)
  157. #define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)
  158. #define DFSDM_ISR_AWDF_MASK BIT(4)
  159. #define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
  160. #define DFSDM_ISR_JCIP_MASK BIT(13)
  161. #define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
  162. #define DFSDM_ISR_RCIP_MASK BIT(14)
  163. #define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
  164. #define DFSDM_ISR_CKABF_MASK GENMASK(23, 16)
  165. #define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)
  166. #define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)
  167. #define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
  168. /* ICR: Interrupt flag clear register */
  169. #define DFSDM_ICR_CLRJOVRF_MASK BIT(2)
  170. #define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)
  171. #define DFSDM_ICR_CLRROVRF_MASK BIT(3)
  172. #define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)
  173. #define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16)
  174. #define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)
  175. #define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y))
  176. #define DFSDM_ICR_CLRCKABF_CH(v, y) \
  177. (((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))
  178. #define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24)
  179. #define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)
  180. #define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y))
  181. #define DFSDM_ICR_CLRSCDF_CH(v, y) \
  182. (((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))
  183. /* FCR: Filter control register */
  184. #define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)
  185. #define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
  186. #define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)
  187. #define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)
  188. #define DFSDM_FCR_FORD_MASK GENMASK(31, 29)
  189. #define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v)
  190. /* RDATAR: Filter data register for regular channel */
  191. #define DFSDM_DATAR_CH_MASK GENMASK(2, 0)
  192. #define DFSDM_DATAR_DATA_OFFSET 8
  193. #define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET)
  194. /* AWLTR: Filter analog watchdog low threshold register */
  195. #define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0)
  196. #define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)
  197. #define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8)
  198. #define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)
  199. /* AWHTR: Filter analog watchdog low threshold register */
  200. #define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0)
  201. #define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)
  202. #define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8)
  203. #define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)
  204. /* AWSR: Filter watchdog status register */
  205. #define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0)
  206. #define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)
  207. #define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8)
  208. #define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)
  209. /* AWCFR: Filter watchdog status register */
  210. #define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0)
  211. #define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
  212. #define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)
  213. #define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
  214. /* DFSDM filter order */
  215. enum stm32_dfsdm_sinc_order {
  216. DFSDM_FASTSINC_ORDER, /* FastSinc filter type */
  217. DFSDM_SINC1_ORDER, /* Sinc 1 filter type */
  218. DFSDM_SINC2_ORDER, /* Sinc 2 filter type */
  219. DFSDM_SINC3_ORDER, /* Sinc 3 filter type */
  220. DFSDM_SINC4_ORDER, /* Sinc 4 filter type (N.A. for watchdog) */
  221. DFSDM_SINC5_ORDER, /* Sinc 5 filter type (N.A. for watchdog) */
  222. DFSDM_NB_SINC_ORDER,
  223. };
  224. /**
  225. * struct stm32_dfsdm_filter_osr - DFSDM filter settings linked to oversampling
  226. * @iosr: integrator oversampling
  227. * @fosr: filter oversampling
  228. * @rshift: output sample right shift (hardware shift)
  229. * @lshift: output sample left shift (software shift)
  230. * @res: output sample resolution
  231. * @bits: output sample resolution in bits
  232. * @max: output sample maximum positive value
  233. */
  234. struct stm32_dfsdm_filter_osr {
  235. unsigned int iosr;
  236. unsigned int fosr;
  237. unsigned int rshift;
  238. unsigned int lshift;
  239. u64 res;
  240. u32 bits;
  241. s32 max;
  242. };
  243. /**
  244. * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter
  245. * @ford: filter order
  246. * @flo: filter oversampling data table indexed by fast mode flag
  247. * @sync_mode: filter synchronized with filter 0
  248. * @fast: filter fast mode
  249. */
  250. struct stm32_dfsdm_filter {
  251. enum stm32_dfsdm_sinc_order ford;
  252. struct stm32_dfsdm_filter_osr flo[2];
  253. unsigned int sync_mode;
  254. unsigned int fast;
  255. };
  256. /**
  257. * struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel
  258. * @id: id of the channel
  259. * @type: interface type linked to stm32_dfsdm_chan_type
  260. * @src: interface type linked to stm32_dfsdm_chan_src
  261. * @alt_si: alternative serial input interface
  262. */
  263. struct stm32_dfsdm_channel {
  264. unsigned int id;
  265. unsigned int type;
  266. unsigned int src;
  267. unsigned int alt_si;
  268. };
  269. /**
  270. * struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances)
  271. * @base: control registers base cpu addr
  272. * @phys_base: DFSDM IP register physical address
  273. * @regmap: regmap for register read/write
  274. * @fl_list: filter resources list
  275. * @num_fls: number of filter resources available
  276. * @ch_list: channel resources list
  277. * @num_chs: number of channel resources available
  278. * @spi_master_freq: SPI clock out frequency
  279. */
  280. struct stm32_dfsdm {
  281. void __iomem *base;
  282. phys_addr_t phys_base;
  283. struct regmap *regmap;
  284. struct stm32_dfsdm_filter *fl_list;
  285. unsigned int num_fls;
  286. struct stm32_dfsdm_channel *ch_list;
  287. unsigned int num_chs;
  288. unsigned int spi_master_freq;
  289. };
  290. /* DFSDM channel serial spi clock source */
  291. enum stm32_dfsdm_spi_clk_src {
  292. DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL,
  293. DFSDM_CHANNEL_SPI_CLOCK_INTERNAL,
  294. DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING,
  295. DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
  296. };
  297. int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm);
  298. int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm);
  299. #endif