stm32-dfsdm-core.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This file is part the core part STM32 DFSDM driver
  4. *
  5. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  6. * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/iio/iio.h>
  10. #include <linux/iio/sysfs.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/module.h>
  13. #include <linux/of_device.h>
  14. #include <linux/pinctrl/consumer.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include "stm32-dfsdm.h"
  19. struct stm32_dfsdm_dev_data {
  20. unsigned int num_filters;
  21. unsigned int num_channels;
  22. const struct regmap_config *regmap_cfg;
  23. };
  24. #define STM32H7_DFSDM_NUM_FILTERS 4
  25. #define STM32H7_DFSDM_NUM_CHANNELS 8
  26. #define STM32MP1_DFSDM_NUM_FILTERS 6
  27. #define STM32MP1_DFSDM_NUM_CHANNELS 8
  28. static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
  29. {
  30. if (reg < DFSDM_FILTER_BASE_ADR)
  31. return false;
  32. /*
  33. * Mask is done on register to avoid to list registers of all
  34. * filter instances.
  35. */
  36. switch (reg & DFSDM_FILTER_REG_MASK) {
  37. case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
  38. case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
  39. case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
  40. case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
  41. return true;
  42. }
  43. return false;
  44. }
  45. static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
  46. .reg_bits = 32,
  47. .val_bits = 32,
  48. .reg_stride = sizeof(u32),
  49. .max_register = 0x2B8,
  50. .volatile_reg = stm32_dfsdm_volatile_reg,
  51. .fast_io = true,
  52. };
  53. static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
  54. .num_filters = STM32H7_DFSDM_NUM_FILTERS,
  55. .num_channels = STM32H7_DFSDM_NUM_CHANNELS,
  56. .regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
  57. };
  58. static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = {
  59. .reg_bits = 32,
  60. .val_bits = 32,
  61. .reg_stride = sizeof(u32),
  62. .max_register = 0x7fc,
  63. .volatile_reg = stm32_dfsdm_volatile_reg,
  64. .fast_io = true,
  65. };
  66. static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = {
  67. .num_filters = STM32MP1_DFSDM_NUM_FILTERS,
  68. .num_channels = STM32MP1_DFSDM_NUM_CHANNELS,
  69. .regmap_cfg = &stm32mp1_dfsdm_regmap_cfg,
  70. };
  71. struct dfsdm_priv {
  72. struct platform_device *pdev; /* platform device */
  73. struct stm32_dfsdm dfsdm; /* common data exported for all instances */
  74. unsigned int spi_clk_out_div; /* SPI clkout divider value */
  75. atomic_t n_active_ch; /* number of current active channels */
  76. struct clk *clk; /* DFSDM clock */
  77. struct clk *aclk; /* audio clock */
  78. };
  79. static inline struct dfsdm_priv *to_stm32_dfsdm_priv(struct stm32_dfsdm *dfsdm)
  80. {
  81. return container_of(dfsdm, struct dfsdm_priv, dfsdm);
  82. }
  83. static int stm32_dfsdm_clk_prepare_enable(struct stm32_dfsdm *dfsdm)
  84. {
  85. struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
  86. int ret;
  87. ret = clk_prepare_enable(priv->clk);
  88. if (ret || !priv->aclk)
  89. return ret;
  90. ret = clk_prepare_enable(priv->aclk);
  91. if (ret)
  92. clk_disable_unprepare(priv->clk);
  93. return ret;
  94. }
  95. static void stm32_dfsdm_clk_disable_unprepare(struct stm32_dfsdm *dfsdm)
  96. {
  97. struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
  98. if (priv->aclk)
  99. clk_disable_unprepare(priv->aclk);
  100. clk_disable_unprepare(priv->clk);
  101. }
  102. /**
  103. * stm32_dfsdm_start_dfsdm - start global dfsdm interface.
  104. *
  105. * Enable interface if n_active_ch is not null.
  106. * @dfsdm: Handle used to retrieve dfsdm context.
  107. */
  108. int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
  109. {
  110. struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
  111. struct device *dev = &priv->pdev->dev;
  112. unsigned int clk_div = priv->spi_clk_out_div, clk_src;
  113. int ret;
  114. if (atomic_inc_return(&priv->n_active_ch) == 1) {
  115. ret = pm_runtime_get_sync(dev);
  116. if (ret < 0) {
  117. pm_runtime_put_noidle(dev);
  118. goto error_ret;
  119. }
  120. /* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
  121. clk_src = priv->aclk ? 1 : 0;
  122. ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
  123. DFSDM_CHCFGR1_CKOUTSRC_MASK,
  124. DFSDM_CHCFGR1_CKOUTSRC(clk_src));
  125. if (ret < 0)
  126. goto pm_put;
  127. /* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
  128. ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
  129. DFSDM_CHCFGR1_CKOUTDIV_MASK,
  130. DFSDM_CHCFGR1_CKOUTDIV(clk_div));
  131. if (ret < 0)
  132. goto pm_put;
  133. /* Global enable of DFSDM interface */
  134. ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
  135. DFSDM_CHCFGR1_DFSDMEN_MASK,
  136. DFSDM_CHCFGR1_DFSDMEN(1));
  137. if (ret < 0)
  138. goto pm_put;
  139. }
  140. dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
  141. atomic_read(&priv->n_active_ch));
  142. return 0;
  143. pm_put:
  144. pm_runtime_put_sync(dev);
  145. error_ret:
  146. atomic_dec(&priv->n_active_ch);
  147. return ret;
  148. }
  149. EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
  150. /**
  151. * stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
  152. *
  153. * Disable interface if n_active_ch is null
  154. * @dfsdm: Handle used to retrieve dfsdm context.
  155. */
  156. int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
  157. {
  158. struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
  159. int ret;
  160. if (atomic_dec_and_test(&priv->n_active_ch)) {
  161. /* Global disable of DFSDM interface */
  162. ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
  163. DFSDM_CHCFGR1_DFSDMEN_MASK,
  164. DFSDM_CHCFGR1_DFSDMEN(0));
  165. if (ret < 0)
  166. return ret;
  167. /* Stop SPI CLKOUT */
  168. ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
  169. DFSDM_CHCFGR1_CKOUTDIV_MASK,
  170. DFSDM_CHCFGR1_CKOUTDIV(0));
  171. if (ret < 0)
  172. return ret;
  173. pm_runtime_put_sync(&priv->pdev->dev);
  174. }
  175. dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
  176. atomic_read(&priv->n_active_ch));
  177. return 0;
  178. }
  179. EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
  180. static int stm32_dfsdm_parse_of(struct platform_device *pdev,
  181. struct dfsdm_priv *priv)
  182. {
  183. struct device_node *node = pdev->dev.of_node;
  184. struct resource *res;
  185. unsigned long clk_freq, divider;
  186. unsigned int spi_freq, rem;
  187. int ret;
  188. if (!node)
  189. return -EINVAL;
  190. priv->dfsdm.base = devm_platform_get_and_ioremap_resource(pdev, 0,
  191. &res);
  192. if (IS_ERR(priv->dfsdm.base))
  193. return PTR_ERR(priv->dfsdm.base);
  194. priv->dfsdm.phys_base = res->start;
  195. /*
  196. * "dfsdm" clock is mandatory for DFSDM peripheral clocking.
  197. * "dfsdm" or "audio" clocks can be used as source clock for
  198. * the SPI clock out signal and internal processing, depending
  199. * on use case.
  200. */
  201. priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
  202. if (IS_ERR(priv->clk))
  203. return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
  204. "Failed to get clock\n");
  205. priv->aclk = devm_clk_get(&pdev->dev, "audio");
  206. if (IS_ERR(priv->aclk))
  207. priv->aclk = NULL;
  208. if (priv->aclk)
  209. clk_freq = clk_get_rate(priv->aclk);
  210. else
  211. clk_freq = clk_get_rate(priv->clk);
  212. /* SPI clock out frequency */
  213. ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
  214. &spi_freq);
  215. if (ret < 0) {
  216. /* No SPI master mode */
  217. return 0;
  218. }
  219. divider = div_u64_rem(clk_freq, spi_freq, &rem);
  220. /* Round up divider when ckout isn't precise, not to exceed spi_freq */
  221. if (rem)
  222. divider++;
  223. /* programmable divider is in range of [2:256] */
  224. if (divider < 2 || divider > 256) {
  225. dev_err(&pdev->dev, "spi-max-frequency not achievable\n");
  226. return -EINVAL;
  227. }
  228. /* SPI clock output divider is: divider = CKOUTDIV + 1 */
  229. priv->spi_clk_out_div = divider - 1;
  230. priv->dfsdm.spi_master_freq = clk_freq / (priv->spi_clk_out_div + 1);
  231. if (rem) {
  232. dev_warn(&pdev->dev, "SPI clock not accurate\n");
  233. dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
  234. clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
  235. }
  236. return 0;
  237. };
  238. static const struct of_device_id stm32_dfsdm_of_match[] = {
  239. {
  240. .compatible = "st,stm32h7-dfsdm",
  241. .data = &stm32h7_dfsdm_data,
  242. },
  243. {
  244. .compatible = "st,stm32mp1-dfsdm",
  245. .data = &stm32mp1_dfsdm_data,
  246. },
  247. {}
  248. };
  249. MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
  250. static int stm32_dfsdm_probe(struct platform_device *pdev)
  251. {
  252. struct dfsdm_priv *priv;
  253. const struct stm32_dfsdm_dev_data *dev_data;
  254. struct stm32_dfsdm *dfsdm;
  255. int ret;
  256. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  257. if (!priv)
  258. return -ENOMEM;
  259. priv->pdev = pdev;
  260. dev_data = of_device_get_match_data(&pdev->dev);
  261. dfsdm = &priv->dfsdm;
  262. dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
  263. sizeof(*dfsdm->fl_list), GFP_KERNEL);
  264. if (!dfsdm->fl_list)
  265. return -ENOMEM;
  266. dfsdm->num_fls = dev_data->num_filters;
  267. dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
  268. sizeof(*dfsdm->ch_list),
  269. GFP_KERNEL);
  270. if (!dfsdm->ch_list)
  271. return -ENOMEM;
  272. dfsdm->num_chs = dev_data->num_channels;
  273. ret = stm32_dfsdm_parse_of(pdev, priv);
  274. if (ret < 0)
  275. return ret;
  276. dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
  277. dfsdm->base,
  278. dev_data->regmap_cfg);
  279. if (IS_ERR(dfsdm->regmap)) {
  280. ret = PTR_ERR(dfsdm->regmap);
  281. dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
  282. __func__, ret);
  283. return ret;
  284. }
  285. platform_set_drvdata(pdev, dfsdm);
  286. ret = stm32_dfsdm_clk_prepare_enable(dfsdm);
  287. if (ret) {
  288. dev_err(&pdev->dev, "Failed to start clock\n");
  289. return ret;
  290. }
  291. pm_runtime_get_noresume(&pdev->dev);
  292. pm_runtime_set_active(&pdev->dev);
  293. pm_runtime_enable(&pdev->dev);
  294. ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
  295. if (ret)
  296. goto pm_put;
  297. pm_runtime_put(&pdev->dev);
  298. return 0;
  299. pm_put:
  300. pm_runtime_disable(&pdev->dev);
  301. pm_runtime_set_suspended(&pdev->dev);
  302. pm_runtime_put_noidle(&pdev->dev);
  303. stm32_dfsdm_clk_disable_unprepare(dfsdm);
  304. return ret;
  305. }
  306. static int stm32_dfsdm_core_remove(struct platform_device *pdev)
  307. {
  308. struct stm32_dfsdm *dfsdm = platform_get_drvdata(pdev);
  309. pm_runtime_get_sync(&pdev->dev);
  310. of_platform_depopulate(&pdev->dev);
  311. pm_runtime_disable(&pdev->dev);
  312. pm_runtime_set_suspended(&pdev->dev);
  313. pm_runtime_put_noidle(&pdev->dev);
  314. stm32_dfsdm_clk_disable_unprepare(dfsdm);
  315. return 0;
  316. }
  317. static int __maybe_unused stm32_dfsdm_core_suspend(struct device *dev)
  318. {
  319. struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
  320. struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
  321. int ret;
  322. ret = pm_runtime_force_suspend(dev);
  323. if (ret)
  324. return ret;
  325. /* Balance devm_regmap_init_mmio_clk() clk_prepare() */
  326. clk_unprepare(priv->clk);
  327. return pinctrl_pm_select_sleep_state(dev);
  328. }
  329. static int __maybe_unused stm32_dfsdm_core_resume(struct device *dev)
  330. {
  331. struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
  332. struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
  333. int ret;
  334. ret = pinctrl_pm_select_default_state(dev);
  335. if (ret)
  336. return ret;
  337. ret = clk_prepare(priv->clk);
  338. if (ret)
  339. return ret;
  340. return pm_runtime_force_resume(dev);
  341. }
  342. static int __maybe_unused stm32_dfsdm_core_runtime_suspend(struct device *dev)
  343. {
  344. struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
  345. stm32_dfsdm_clk_disable_unprepare(dfsdm);
  346. return 0;
  347. }
  348. static int __maybe_unused stm32_dfsdm_core_runtime_resume(struct device *dev)
  349. {
  350. struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
  351. return stm32_dfsdm_clk_prepare_enable(dfsdm);
  352. }
  353. static const struct dev_pm_ops stm32_dfsdm_core_pm_ops = {
  354. SET_SYSTEM_SLEEP_PM_OPS(stm32_dfsdm_core_suspend,
  355. stm32_dfsdm_core_resume)
  356. SET_RUNTIME_PM_OPS(stm32_dfsdm_core_runtime_suspend,
  357. stm32_dfsdm_core_runtime_resume,
  358. NULL)
  359. };
  360. static struct platform_driver stm32_dfsdm_driver = {
  361. .probe = stm32_dfsdm_probe,
  362. .remove = stm32_dfsdm_core_remove,
  363. .driver = {
  364. .name = "stm32-dfsdm",
  365. .of_match_table = stm32_dfsdm_of_match,
  366. .pm = &stm32_dfsdm_core_pm_ops,
  367. },
  368. };
  369. module_platform_driver(stm32_dfsdm_driver);
  370. MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
  371. MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
  372. MODULE_LICENSE("GPL v2");