stm32-dfsdm-adc.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This file is the ADC part of the STM32 DFSDM driver
  4. *
  5. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  6. * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
  7. */
  8. #include <linux/dmaengine.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/iio/adc/stm32-dfsdm-adc.h>
  11. #include <linux/iio/buffer.h>
  12. #include <linux/iio/hw-consumer.h>
  13. #include <linux/iio/sysfs.h>
  14. #include <linux/iio/timer/stm32-lptim-trigger.h>
  15. #include <linux/iio/timer/stm32-timer-trigger.h>
  16. #include <linux/iio/trigger.h>
  17. #include <linux/iio/trigger_consumer.h>
  18. #include <linux/iio/triggered_buffer.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/module.h>
  21. #include <linux/of_device.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/regmap.h>
  24. #include <linux/slab.h>
  25. #include "stm32-dfsdm.h"
  26. #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
  27. /* Conversion timeout */
  28. #define DFSDM_TIMEOUT_US 100000
  29. #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
  30. /* Oversampling attribute default */
  31. #define DFSDM_DEFAULT_OVERSAMPLING 100
  32. /* Oversampling max values */
  33. #define DFSDM_MAX_INT_OVERSAMPLING 256
  34. #define DFSDM_MAX_FL_OVERSAMPLING 1024
  35. /* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
  36. #define DFSDM_DATA_MAX BIT(30)
  37. /*
  38. * Data are output as two's complement data in a 24 bit field.
  39. * Data from filters are in the range +/-2^(n-1)
  40. * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
  41. * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
  42. * So, the resolution of samples from filter is actually limited to 23 bits
  43. */
  44. #define DFSDM_DATA_RES 24
  45. /* Filter configuration */
  46. #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
  47. DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
  48. DFSDM_CR1_JSCAN_MASK)
  49. enum sd_converter_type {
  50. DFSDM_AUDIO,
  51. DFSDM_IIO,
  52. };
  53. struct stm32_dfsdm_dev_data {
  54. int type;
  55. int (*init)(struct device *dev, struct iio_dev *indio_dev);
  56. unsigned int num_channels;
  57. const struct regmap_config *regmap_cfg;
  58. };
  59. struct stm32_dfsdm_adc {
  60. struct stm32_dfsdm *dfsdm;
  61. const struct stm32_dfsdm_dev_data *dev_data;
  62. unsigned int fl_id;
  63. unsigned int nconv;
  64. unsigned long smask;
  65. /* ADC specific */
  66. unsigned int oversamp;
  67. struct iio_hw_consumer *hwc;
  68. struct completion completion;
  69. u32 *buffer;
  70. /* Audio specific */
  71. unsigned int spi_freq; /* SPI bus clock frequency */
  72. unsigned int sample_freq; /* Sample frequency after filter decimation */
  73. int (*cb)(const void *data, size_t size, void *cb_priv);
  74. void *cb_priv;
  75. /* DMA */
  76. u8 *rx_buf;
  77. unsigned int bufi; /* Buffer current position */
  78. unsigned int buf_sz; /* Buffer size */
  79. struct dma_chan *dma_chan;
  80. dma_addr_t dma_buf;
  81. };
  82. struct stm32_dfsdm_str2field {
  83. const char *name;
  84. unsigned int val;
  85. };
  86. /* DFSDM channel serial interface type */
  87. static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
  88. { "SPI_R", 0 }, /* SPI with data on rising edge */
  89. { "SPI_F", 1 }, /* SPI with data on falling edge */
  90. { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
  91. { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
  92. {},
  93. };
  94. /* DFSDM channel clock source */
  95. static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
  96. /* External SPI clock (CLKIN x) */
  97. { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
  98. /* Internal SPI clock (CLKOUT) */
  99. { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
  100. /* Internal SPI clock divided by 2 (falling edge) */
  101. { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
  102. /* Internal SPI clock divided by 2 (falling edge) */
  103. { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
  104. {},
  105. };
  106. static int stm32_dfsdm_str2val(const char *str,
  107. const struct stm32_dfsdm_str2field *list)
  108. {
  109. const struct stm32_dfsdm_str2field *p = list;
  110. for (p = list; p && p->name; p++)
  111. if (!strcmp(p->name, str))
  112. return p->val;
  113. return -EINVAL;
  114. }
  115. /**
  116. * struct stm32_dfsdm_trig_info - DFSDM trigger info
  117. * @name: name of the trigger, corresponding to its source
  118. * @jextsel: trigger signal selection
  119. */
  120. struct stm32_dfsdm_trig_info {
  121. const char *name;
  122. unsigned int jextsel;
  123. };
  124. /* hardware injected trigger enable, edge selection */
  125. enum stm32_dfsdm_jexten {
  126. STM32_DFSDM_JEXTEN_DISABLED,
  127. STM32_DFSDM_JEXTEN_RISING_EDGE,
  128. STM32_DFSDM_JEXTEN_FALLING_EDGE,
  129. STM32_DFSDM_EXTEN_BOTH_EDGES,
  130. };
  131. static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
  132. { TIM1_TRGO, 0 },
  133. { TIM1_TRGO2, 1 },
  134. { TIM8_TRGO, 2 },
  135. { TIM8_TRGO2, 3 },
  136. { TIM3_TRGO, 4 },
  137. { TIM4_TRGO, 5 },
  138. { TIM16_OC1, 6 },
  139. { TIM6_TRGO, 7 },
  140. { TIM7_TRGO, 8 },
  141. { LPTIM1_OUT, 26 },
  142. { LPTIM2_OUT, 27 },
  143. { LPTIM3_OUT, 28 },
  144. {},
  145. };
  146. static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
  147. struct iio_trigger *trig)
  148. {
  149. int i;
  150. /* lookup triggers registered by stm32 timer trigger driver */
  151. for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
  152. /**
  153. * Checking both stm32 timer trigger type and trig name
  154. * should be safe against arbitrary trigger names.
  155. */
  156. if ((is_stm32_timer_trigger(trig) ||
  157. is_stm32_lptim_trigger(trig)) &&
  158. !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
  159. return stm32_dfsdm_trigs[i].jextsel;
  160. }
  161. }
  162. return -EINVAL;
  163. }
  164. static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
  165. unsigned int fast, unsigned int oversamp)
  166. {
  167. unsigned int i, d, fosr, iosr;
  168. u64 res, max;
  169. int bits, shift;
  170. unsigned int m = 1; /* multiplication factor */
  171. unsigned int p = fl->ford; /* filter order (ford) */
  172. struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
  173. pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
  174. /*
  175. * This function tries to compute filter oversampling and integrator
  176. * oversampling, base on oversampling ratio requested by user.
  177. *
  178. * Decimation d depends on the filter order and the oversampling ratios.
  179. * ford: filter order
  180. * fosr: filter over sampling ratio
  181. * iosr: integrator over sampling ratio
  182. */
  183. if (fl->ford == DFSDM_FASTSINC_ORDER) {
  184. m = 2;
  185. p = 2;
  186. }
  187. /*
  188. * Look for filter and integrator oversampling ratios which allows
  189. * to maximize data output resolution.
  190. */
  191. for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
  192. for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
  193. if (fast)
  194. d = fosr * iosr;
  195. else if (fl->ford == DFSDM_FASTSINC_ORDER)
  196. d = fosr * (iosr + 3) + 2;
  197. else
  198. d = fosr * (iosr - 1 + p) + p;
  199. if (d > oversamp)
  200. break;
  201. else if (d != oversamp)
  202. continue;
  203. /*
  204. * Check resolution (limited to signed 32 bits)
  205. * res <= 2^31
  206. * Sincx filters:
  207. * res = m * fosr^p x iosr (with m=1, p=ford)
  208. * FastSinc filter
  209. * res = m * fosr^p x iosr (with m=2, p=2)
  210. */
  211. res = fosr;
  212. for (i = p - 1; i > 0; i--) {
  213. res = res * (u64)fosr;
  214. if (res > DFSDM_DATA_MAX)
  215. break;
  216. }
  217. if (res > DFSDM_DATA_MAX)
  218. continue;
  219. res = res * (u64)m * (u64)iosr;
  220. if (res > DFSDM_DATA_MAX)
  221. continue;
  222. if (res >= flo->res) {
  223. flo->res = res;
  224. flo->fosr = fosr;
  225. flo->iosr = iosr;
  226. bits = fls(flo->res);
  227. /* 8 LBSs in data register contain chan info */
  228. max = flo->res << 8;
  229. /* if resolution is not a power of two */
  230. if (flo->res > BIT(bits - 1))
  231. bits++;
  232. else
  233. max--;
  234. shift = DFSDM_DATA_RES - bits;
  235. /*
  236. * Compute right/left shift
  237. * Right shift is performed by hardware
  238. * when transferring samples to data register.
  239. * Left shift is done by software on buffer
  240. */
  241. if (shift > 0) {
  242. /* Resolution is lower than 24 bits */
  243. flo->rshift = 0;
  244. flo->lshift = shift;
  245. } else {
  246. /*
  247. * If resolution is 24 bits or more,
  248. * max positive value may be ambiguous
  249. * (equal to max negative value as sign
  250. * bit is dropped).
  251. * Reduce resolution to 23 bits (rshift)
  252. * to keep the sign on bit 23 and treat
  253. * saturation before rescaling on 24
  254. * bits (lshift).
  255. */
  256. flo->rshift = 1 - shift;
  257. flo->lshift = 1;
  258. max >>= flo->rshift;
  259. }
  260. flo->max = (s32)max;
  261. flo->bits = bits;
  262. pr_debug("%s: fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
  263. __func__, fast, flo->fosr, flo->iosr,
  264. flo->res, bits, flo->rshift,
  265. flo->lshift);
  266. }
  267. }
  268. }
  269. if (!flo->res)
  270. return -EINVAL;
  271. return 0;
  272. }
  273. static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
  274. unsigned int oversamp)
  275. {
  276. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  277. struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
  278. int ret0, ret1;
  279. memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
  280. memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
  281. ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
  282. ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
  283. if (ret0 < 0 && ret1 < 0) {
  284. dev_err(&indio_dev->dev,
  285. "Filter parameters not found: errors %d/%d\n",
  286. ret0, ret1);
  287. return -EINVAL;
  288. }
  289. return 0;
  290. }
  291. static int stm32_dfsdm_start_channel(struct iio_dev *indio_dev)
  292. {
  293. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  294. struct regmap *regmap = adc->dfsdm->regmap;
  295. const struct iio_chan_spec *chan;
  296. unsigned int bit;
  297. int ret;
  298. for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
  299. chan = indio_dev->channels + bit;
  300. ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
  301. DFSDM_CHCFGR1_CHEN_MASK,
  302. DFSDM_CHCFGR1_CHEN(1));
  303. if (ret < 0)
  304. return ret;
  305. }
  306. return 0;
  307. }
  308. static void stm32_dfsdm_stop_channel(struct iio_dev *indio_dev)
  309. {
  310. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  311. struct regmap *regmap = adc->dfsdm->regmap;
  312. const struct iio_chan_spec *chan;
  313. unsigned int bit;
  314. for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
  315. chan = indio_dev->channels + bit;
  316. regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
  317. DFSDM_CHCFGR1_CHEN_MASK,
  318. DFSDM_CHCFGR1_CHEN(0));
  319. }
  320. }
  321. static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
  322. struct stm32_dfsdm_channel *ch)
  323. {
  324. unsigned int id = ch->id;
  325. struct regmap *regmap = dfsdm->regmap;
  326. int ret;
  327. ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
  328. DFSDM_CHCFGR1_SITP_MASK,
  329. DFSDM_CHCFGR1_SITP(ch->type));
  330. if (ret < 0)
  331. return ret;
  332. ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
  333. DFSDM_CHCFGR1_SPICKSEL_MASK,
  334. DFSDM_CHCFGR1_SPICKSEL(ch->src));
  335. if (ret < 0)
  336. return ret;
  337. return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
  338. DFSDM_CHCFGR1_CHINSEL_MASK,
  339. DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
  340. }
  341. static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
  342. unsigned int fl_id,
  343. struct iio_trigger *trig)
  344. {
  345. struct stm32_dfsdm *dfsdm = adc->dfsdm;
  346. int ret;
  347. /* Enable filter */
  348. ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
  349. DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
  350. if (ret < 0)
  351. return ret;
  352. /* Nothing more to do for injected (scan mode/triggered) conversions */
  353. if (adc->nconv > 1 || trig)
  354. return 0;
  355. /* Software start (single or continuous) regular conversion */
  356. return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
  357. DFSDM_CR1_RSWSTART_MASK,
  358. DFSDM_CR1_RSWSTART(1));
  359. }
  360. static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
  361. unsigned int fl_id)
  362. {
  363. /* Disable conversion */
  364. regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
  365. DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
  366. }
  367. static int stm32_dfsdm_filter_set_trig(struct iio_dev *indio_dev,
  368. unsigned int fl_id,
  369. struct iio_trigger *trig)
  370. {
  371. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  372. struct regmap *regmap = adc->dfsdm->regmap;
  373. u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
  374. int ret;
  375. if (trig) {
  376. ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
  377. if (ret < 0)
  378. return ret;
  379. /* set trigger source and polarity (default to rising edge) */
  380. jextsel = ret;
  381. jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
  382. }
  383. ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
  384. DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
  385. DFSDM_CR1_JEXTSEL(jextsel) |
  386. DFSDM_CR1_JEXTEN(jexten));
  387. if (ret < 0)
  388. return ret;
  389. return 0;
  390. }
  391. static int stm32_dfsdm_channels_configure(struct iio_dev *indio_dev,
  392. unsigned int fl_id,
  393. struct iio_trigger *trig)
  394. {
  395. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  396. struct regmap *regmap = adc->dfsdm->regmap;
  397. struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
  398. struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
  399. const struct iio_chan_spec *chan;
  400. unsigned int bit;
  401. int ret;
  402. fl->fast = 0;
  403. /*
  404. * In continuous mode, use fast mode configuration,
  405. * if it provides a better resolution.
  406. */
  407. if (adc->nconv == 1 && !trig &&
  408. (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)) {
  409. if (fl->flo[1].res >= fl->flo[0].res) {
  410. fl->fast = 1;
  411. flo = &fl->flo[1];
  412. }
  413. }
  414. if (!flo->res)
  415. return -EINVAL;
  416. dev_dbg(&indio_dev->dev, "Samples actual resolution: %d bits",
  417. min(flo->bits, (u32)DFSDM_DATA_RES - 1));
  418. for_each_set_bit(bit, &adc->smask,
  419. sizeof(adc->smask) * BITS_PER_BYTE) {
  420. chan = indio_dev->channels + bit;
  421. ret = regmap_update_bits(regmap,
  422. DFSDM_CHCFGR2(chan->channel),
  423. DFSDM_CHCFGR2_DTRBS_MASK,
  424. DFSDM_CHCFGR2_DTRBS(flo->rshift));
  425. if (ret)
  426. return ret;
  427. }
  428. return 0;
  429. }
  430. static int stm32_dfsdm_filter_configure(struct iio_dev *indio_dev,
  431. unsigned int fl_id,
  432. struct iio_trigger *trig)
  433. {
  434. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  435. struct regmap *regmap = adc->dfsdm->regmap;
  436. struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
  437. struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
  438. u32 cr1;
  439. const struct iio_chan_spec *chan;
  440. unsigned int bit, jchg = 0;
  441. int ret;
  442. /* Average integrator oversampling */
  443. ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
  444. DFSDM_FCR_IOSR(flo->iosr - 1));
  445. if (ret)
  446. return ret;
  447. /* Filter order and Oversampling */
  448. ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
  449. DFSDM_FCR_FOSR(flo->fosr - 1));
  450. if (ret)
  451. return ret;
  452. ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
  453. DFSDM_FCR_FORD(fl->ford));
  454. if (ret)
  455. return ret;
  456. ret = stm32_dfsdm_filter_set_trig(indio_dev, fl_id, trig);
  457. if (ret)
  458. return ret;
  459. ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
  460. DFSDM_CR1_FAST_MASK,
  461. DFSDM_CR1_FAST(fl->fast));
  462. if (ret)
  463. return ret;
  464. /*
  465. * DFSDM modes configuration W.R.T audio/iio type modes
  466. * ----------------------------------------------------------------
  467. * Modes | regular | regular | injected | injected |
  468. * | | continuous | | + scan |
  469. * --------------|---------|--------------|----------|------------|
  470. * single conv | x | | | |
  471. * (1 chan) | | | | |
  472. * --------------|---------|--------------|----------|------------|
  473. * 1 Audio chan | | sample freq | | |
  474. * | | or sync_mode | | |
  475. * --------------|---------|--------------|----------|------------|
  476. * 1 IIO chan | | sample freq | trigger | |
  477. * | | or sync_mode | | |
  478. * --------------|---------|--------------|----------|------------|
  479. * 2+ IIO chans | | | | trigger or |
  480. * | | | | sync_mode |
  481. * ----------------------------------------------------------------
  482. */
  483. if (adc->nconv == 1 && !trig) {
  484. bit = __ffs(adc->smask);
  485. chan = indio_dev->channels + bit;
  486. /* Use regular conversion for single channel without trigger */
  487. cr1 = DFSDM_CR1_RCH(chan->channel);
  488. /* Continuous conversions triggered by SPI clk in buffer mode */
  489. if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)
  490. cr1 |= DFSDM_CR1_RCONT(1);
  491. cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
  492. } else {
  493. /* Use injected conversion for multiple channels */
  494. for_each_set_bit(bit, &adc->smask,
  495. sizeof(adc->smask) * BITS_PER_BYTE) {
  496. chan = indio_dev->channels + bit;
  497. jchg |= BIT(chan->channel);
  498. }
  499. ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
  500. if (ret < 0)
  501. return ret;
  502. /* Use scan mode for multiple channels */
  503. cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
  504. /*
  505. * Continuous conversions not supported in injected mode,
  506. * either use:
  507. * - conversions in sync with filter 0
  508. * - triggered conversions
  509. */
  510. if (!fl->sync_mode && !trig)
  511. return -EINVAL;
  512. cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
  513. }
  514. return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
  515. cr1);
  516. }
  517. static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
  518. struct iio_dev *indio_dev,
  519. struct iio_chan_spec *ch)
  520. {
  521. struct stm32_dfsdm_channel *df_ch;
  522. const char *of_str;
  523. int chan_idx = ch->scan_index;
  524. int ret, val;
  525. ret = of_property_read_u32_index(indio_dev->dev.of_node,
  526. "st,adc-channels", chan_idx,
  527. &ch->channel);
  528. if (ret < 0) {
  529. dev_err(&indio_dev->dev,
  530. " Error parsing 'st,adc-channels' for idx %d\n",
  531. chan_idx);
  532. return ret;
  533. }
  534. if (ch->channel >= dfsdm->num_chs) {
  535. dev_err(&indio_dev->dev,
  536. " Error bad channel number %d (max = %d)\n",
  537. ch->channel, dfsdm->num_chs);
  538. return -EINVAL;
  539. }
  540. ret = of_property_read_string_index(indio_dev->dev.of_node,
  541. "st,adc-channel-names", chan_idx,
  542. &ch->datasheet_name);
  543. if (ret < 0) {
  544. dev_err(&indio_dev->dev,
  545. " Error parsing 'st,adc-channel-names' for idx %d\n",
  546. chan_idx);
  547. return ret;
  548. }
  549. df_ch = &dfsdm->ch_list[ch->channel];
  550. df_ch->id = ch->channel;
  551. ret = of_property_read_string_index(indio_dev->dev.of_node,
  552. "st,adc-channel-types", chan_idx,
  553. &of_str);
  554. if (!ret) {
  555. val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
  556. if (val < 0)
  557. return val;
  558. } else {
  559. val = 0;
  560. }
  561. df_ch->type = val;
  562. ret = of_property_read_string_index(indio_dev->dev.of_node,
  563. "st,adc-channel-clk-src", chan_idx,
  564. &of_str);
  565. if (!ret) {
  566. val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
  567. if (val < 0)
  568. return val;
  569. } else {
  570. val = 0;
  571. }
  572. df_ch->src = val;
  573. ret = of_property_read_u32_index(indio_dev->dev.of_node,
  574. "st,adc-alt-channel", chan_idx,
  575. &df_ch->alt_si);
  576. if (ret < 0)
  577. df_ch->alt_si = 0;
  578. return 0;
  579. }
  580. static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
  581. uintptr_t priv,
  582. const struct iio_chan_spec *chan,
  583. char *buf)
  584. {
  585. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  586. return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
  587. }
  588. static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
  589. unsigned int sample_freq,
  590. unsigned int spi_freq)
  591. {
  592. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  593. unsigned int oversamp;
  594. int ret;
  595. oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
  596. if (spi_freq % sample_freq)
  597. dev_dbg(&indio_dev->dev,
  598. "Rate not accurate. requested (%u), actual (%u)\n",
  599. sample_freq, spi_freq / oversamp);
  600. ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
  601. if (ret < 0)
  602. return ret;
  603. adc->sample_freq = spi_freq / oversamp;
  604. adc->oversamp = oversamp;
  605. return 0;
  606. }
  607. static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
  608. uintptr_t priv,
  609. const struct iio_chan_spec *chan,
  610. const char *buf, size_t len)
  611. {
  612. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  613. struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
  614. unsigned int sample_freq = adc->sample_freq;
  615. unsigned int spi_freq;
  616. int ret;
  617. dev_err(&indio_dev->dev, "enter %s\n", __func__);
  618. /* If DFSDM is master on SPI, SPI freq can not be updated */
  619. if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
  620. return -EPERM;
  621. ret = kstrtoint(buf, 0, &spi_freq);
  622. if (ret)
  623. return ret;
  624. if (!spi_freq)
  625. return -EINVAL;
  626. if (sample_freq) {
  627. ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
  628. if (ret < 0)
  629. return ret;
  630. }
  631. adc->spi_freq = spi_freq;
  632. return len;
  633. }
  634. static int stm32_dfsdm_start_conv(struct iio_dev *indio_dev,
  635. struct iio_trigger *trig)
  636. {
  637. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  638. struct regmap *regmap = adc->dfsdm->regmap;
  639. int ret;
  640. ret = stm32_dfsdm_channels_configure(indio_dev, adc->fl_id, trig);
  641. if (ret < 0)
  642. return ret;
  643. ret = stm32_dfsdm_start_channel(indio_dev);
  644. if (ret < 0)
  645. return ret;
  646. ret = stm32_dfsdm_filter_configure(indio_dev, adc->fl_id, trig);
  647. if (ret < 0)
  648. goto stop_channels;
  649. ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
  650. if (ret < 0)
  651. goto filter_unconfigure;
  652. return 0;
  653. filter_unconfigure:
  654. regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
  655. DFSDM_CR1_CFG_MASK, 0);
  656. stop_channels:
  657. stm32_dfsdm_stop_channel(indio_dev);
  658. return ret;
  659. }
  660. static void stm32_dfsdm_stop_conv(struct iio_dev *indio_dev)
  661. {
  662. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  663. struct regmap *regmap = adc->dfsdm->regmap;
  664. stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
  665. regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
  666. DFSDM_CR1_CFG_MASK, 0);
  667. stm32_dfsdm_stop_channel(indio_dev);
  668. }
  669. static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
  670. unsigned int val)
  671. {
  672. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  673. unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
  674. unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
  675. /*
  676. * DMA cyclic transfers are used, buffer is split into two periods.
  677. * There should be :
  678. * - always one buffer (period) DMA is working on
  679. * - one buffer (period) driver pushed to ASoC side.
  680. */
  681. watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
  682. adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
  683. return 0;
  684. }
  685. static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
  686. {
  687. struct dma_tx_state state;
  688. enum dma_status status;
  689. status = dmaengine_tx_status(adc->dma_chan,
  690. adc->dma_chan->cookie,
  691. &state);
  692. if (status == DMA_IN_PROGRESS) {
  693. /* Residue is size in bytes from end of buffer */
  694. unsigned int i = adc->buf_sz - state.residue;
  695. unsigned int size;
  696. /* Return available bytes */
  697. if (i >= adc->bufi)
  698. size = i - adc->bufi;
  699. else
  700. size = adc->buf_sz + i - adc->bufi;
  701. return size;
  702. }
  703. return 0;
  704. }
  705. static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
  706. s32 *buffer)
  707. {
  708. struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
  709. struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
  710. unsigned int i = adc->nconv;
  711. s32 *ptr = buffer;
  712. while (i--) {
  713. /* Mask 8 LSB that contains the channel ID */
  714. *ptr &= 0xFFFFFF00;
  715. /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
  716. if (*ptr > flo->max)
  717. *ptr -= 1;
  718. /*
  719. * Samples from filter are retrieved with 23 bits resolution
  720. * or less. Shift left to align MSB on 24 bits.
  721. */
  722. *ptr <<= flo->lshift;
  723. ptr++;
  724. }
  725. }
  726. static void stm32_dfsdm_dma_buffer_done(void *data)
  727. {
  728. struct iio_dev *indio_dev = data;
  729. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  730. int available = stm32_dfsdm_adc_dma_residue(adc);
  731. size_t old_pos;
  732. /*
  733. * FIXME: In Kernel interface does not support cyclic DMA buffer,and
  734. * offers only an interface to push data samples per samples.
  735. * For this reason IIO buffer interface is not used and interface is
  736. * bypassed using a private callback registered by ASoC.
  737. * This should be a temporary solution waiting a cyclic DMA engine
  738. * support in IIO.
  739. */
  740. dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
  741. adc->bufi, available);
  742. old_pos = adc->bufi;
  743. while (available >= indio_dev->scan_bytes) {
  744. s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
  745. stm32_dfsdm_process_data(adc, buffer);
  746. available -= indio_dev->scan_bytes;
  747. adc->bufi += indio_dev->scan_bytes;
  748. if (adc->bufi >= adc->buf_sz) {
  749. if (adc->cb)
  750. adc->cb(&adc->rx_buf[old_pos],
  751. adc->buf_sz - old_pos, adc->cb_priv);
  752. adc->bufi = 0;
  753. old_pos = 0;
  754. }
  755. /*
  756. * In DMA mode the trigger services of IIO are not used
  757. * (e.g. no call to iio_trigger_poll).
  758. * Calling irq handler associated to the hardware trigger is not
  759. * relevant as the conversions have already been done. Data
  760. * transfers are performed directly in DMA callback instead.
  761. * This implementation avoids to call trigger irq handler that
  762. * may sleep, in an atomic context (DMA irq handler context).
  763. */
  764. if (adc->dev_data->type == DFSDM_IIO)
  765. iio_push_to_buffers(indio_dev, buffer);
  766. }
  767. if (adc->cb)
  768. adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
  769. adc->cb_priv);
  770. }
  771. static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
  772. {
  773. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  774. /*
  775. * The DFSDM supports half-word transfers. However, for 16 bits record,
  776. * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
  777. * shift is required.
  778. */
  779. struct dma_slave_config config = {
  780. .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
  781. .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  782. };
  783. struct dma_async_tx_descriptor *desc;
  784. dma_cookie_t cookie;
  785. int ret;
  786. if (!adc->dma_chan)
  787. return -EINVAL;
  788. dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
  789. adc->buf_sz, adc->buf_sz / 2);
  790. if (adc->nconv == 1 && !indio_dev->trig)
  791. config.src_addr += DFSDM_RDATAR(adc->fl_id);
  792. else
  793. config.src_addr += DFSDM_JDATAR(adc->fl_id);
  794. ret = dmaengine_slave_config(adc->dma_chan, &config);
  795. if (ret)
  796. return ret;
  797. /* Prepare a DMA cyclic transaction */
  798. desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
  799. adc->dma_buf,
  800. adc->buf_sz, adc->buf_sz / 2,
  801. DMA_DEV_TO_MEM,
  802. DMA_PREP_INTERRUPT);
  803. if (!desc)
  804. return -EBUSY;
  805. desc->callback = stm32_dfsdm_dma_buffer_done;
  806. desc->callback_param = indio_dev;
  807. cookie = dmaengine_submit(desc);
  808. ret = dma_submit_error(cookie);
  809. if (ret)
  810. goto err_stop_dma;
  811. /* Issue pending DMA requests */
  812. dma_async_issue_pending(adc->dma_chan);
  813. if (adc->nconv == 1 && !indio_dev->trig) {
  814. /* Enable regular DMA transfer*/
  815. ret = regmap_update_bits(adc->dfsdm->regmap,
  816. DFSDM_CR1(adc->fl_id),
  817. DFSDM_CR1_RDMAEN_MASK,
  818. DFSDM_CR1_RDMAEN_MASK);
  819. } else {
  820. /* Enable injected DMA transfer*/
  821. ret = regmap_update_bits(adc->dfsdm->regmap,
  822. DFSDM_CR1(adc->fl_id),
  823. DFSDM_CR1_JDMAEN_MASK,
  824. DFSDM_CR1_JDMAEN_MASK);
  825. }
  826. if (ret < 0)
  827. goto err_stop_dma;
  828. return 0;
  829. err_stop_dma:
  830. dmaengine_terminate_all(adc->dma_chan);
  831. return ret;
  832. }
  833. static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
  834. {
  835. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  836. if (!adc->dma_chan)
  837. return;
  838. regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
  839. DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
  840. dmaengine_terminate_all(adc->dma_chan);
  841. }
  842. static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
  843. const unsigned long *scan_mask)
  844. {
  845. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  846. adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
  847. adc->smask = *scan_mask;
  848. dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
  849. return 0;
  850. }
  851. static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
  852. {
  853. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  854. int ret;
  855. /* Reset adc buffer index */
  856. adc->bufi = 0;
  857. if (adc->hwc) {
  858. ret = iio_hw_consumer_enable(adc->hwc);
  859. if (ret < 0)
  860. return ret;
  861. }
  862. ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
  863. if (ret < 0)
  864. goto err_stop_hwc;
  865. ret = stm32_dfsdm_adc_dma_start(indio_dev);
  866. if (ret) {
  867. dev_err(&indio_dev->dev, "Can't start DMA\n");
  868. goto stop_dfsdm;
  869. }
  870. ret = stm32_dfsdm_start_conv(indio_dev, indio_dev->trig);
  871. if (ret) {
  872. dev_err(&indio_dev->dev, "Can't start conversion\n");
  873. goto err_stop_dma;
  874. }
  875. return 0;
  876. err_stop_dma:
  877. stm32_dfsdm_adc_dma_stop(indio_dev);
  878. stop_dfsdm:
  879. stm32_dfsdm_stop_dfsdm(adc->dfsdm);
  880. err_stop_hwc:
  881. if (adc->hwc)
  882. iio_hw_consumer_disable(adc->hwc);
  883. return ret;
  884. }
  885. static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
  886. {
  887. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  888. stm32_dfsdm_stop_conv(indio_dev);
  889. stm32_dfsdm_adc_dma_stop(indio_dev);
  890. stm32_dfsdm_stop_dfsdm(adc->dfsdm);
  891. if (adc->hwc)
  892. iio_hw_consumer_disable(adc->hwc);
  893. return 0;
  894. }
  895. static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
  896. .postenable = &stm32_dfsdm_postenable,
  897. .predisable = &stm32_dfsdm_predisable,
  898. };
  899. /**
  900. * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
  901. * DMA transfer period is achieved.
  902. *
  903. * @iio_dev: Handle to IIO device.
  904. * @cb: Pointer to callback function:
  905. * - data: pointer to data buffer
  906. * - size: size in byte of the data buffer
  907. * - private: pointer to consumer private structure.
  908. * @private: Pointer to consumer private structure.
  909. */
  910. int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
  911. int (*cb)(const void *data, size_t size,
  912. void *private),
  913. void *private)
  914. {
  915. struct stm32_dfsdm_adc *adc;
  916. if (!iio_dev)
  917. return -EINVAL;
  918. adc = iio_priv(iio_dev);
  919. adc->cb = cb;
  920. adc->cb_priv = private;
  921. return 0;
  922. }
  923. EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
  924. /**
  925. * stm32_dfsdm_release_buff_cb - unregister buffer callback
  926. *
  927. * @iio_dev: Handle to IIO device.
  928. */
  929. int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
  930. {
  931. struct stm32_dfsdm_adc *adc;
  932. if (!iio_dev)
  933. return -EINVAL;
  934. adc = iio_priv(iio_dev);
  935. adc->cb = NULL;
  936. adc->cb_priv = NULL;
  937. return 0;
  938. }
  939. EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
  940. static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
  941. const struct iio_chan_spec *chan, int *res)
  942. {
  943. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  944. long timeout;
  945. int ret;
  946. reinit_completion(&adc->completion);
  947. adc->buffer = res;
  948. ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
  949. if (ret < 0)
  950. return ret;
  951. ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
  952. DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
  953. if (ret < 0)
  954. goto stop_dfsdm;
  955. adc->nconv = 1;
  956. adc->smask = BIT(chan->scan_index);
  957. ret = stm32_dfsdm_start_conv(indio_dev, NULL);
  958. if (ret < 0) {
  959. regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
  960. DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
  961. goto stop_dfsdm;
  962. }
  963. timeout = wait_for_completion_interruptible_timeout(&adc->completion,
  964. DFSDM_TIMEOUT);
  965. /* Mask IRQ for regular conversion achievement*/
  966. regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
  967. DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
  968. if (timeout == 0)
  969. ret = -ETIMEDOUT;
  970. else if (timeout < 0)
  971. ret = timeout;
  972. else
  973. ret = IIO_VAL_INT;
  974. stm32_dfsdm_stop_conv(indio_dev);
  975. stm32_dfsdm_process_data(adc, res);
  976. stop_dfsdm:
  977. stm32_dfsdm_stop_dfsdm(adc->dfsdm);
  978. return ret;
  979. }
  980. static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
  981. struct iio_chan_spec const *chan,
  982. int val, int val2, long mask)
  983. {
  984. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  985. struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
  986. unsigned int spi_freq;
  987. int ret = -EINVAL;
  988. switch (ch->src) {
  989. case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
  990. spi_freq = adc->dfsdm->spi_master_freq;
  991. break;
  992. case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
  993. case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
  994. spi_freq = adc->dfsdm->spi_master_freq / 2;
  995. break;
  996. default:
  997. spi_freq = adc->spi_freq;
  998. }
  999. switch (mask) {
  1000. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  1001. ret = iio_device_claim_direct_mode(indio_dev);
  1002. if (ret)
  1003. return ret;
  1004. ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
  1005. if (!ret) {
  1006. dev_dbg(&indio_dev->dev,
  1007. "Sampling rate changed from (%u) to (%u)\n",
  1008. adc->sample_freq, spi_freq / val);
  1009. adc->oversamp = val;
  1010. adc->sample_freq = spi_freq / val;
  1011. }
  1012. iio_device_release_direct_mode(indio_dev);
  1013. return ret;
  1014. case IIO_CHAN_INFO_SAMP_FREQ:
  1015. if (!val)
  1016. return -EINVAL;
  1017. ret = iio_device_claim_direct_mode(indio_dev);
  1018. if (ret)
  1019. return ret;
  1020. ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
  1021. iio_device_release_direct_mode(indio_dev);
  1022. return ret;
  1023. }
  1024. return -EINVAL;
  1025. }
  1026. static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
  1027. struct iio_chan_spec const *chan, int *val,
  1028. int *val2, long mask)
  1029. {
  1030. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1031. int ret;
  1032. switch (mask) {
  1033. case IIO_CHAN_INFO_RAW:
  1034. ret = iio_device_claim_direct_mode(indio_dev);
  1035. if (ret)
  1036. return ret;
  1037. ret = iio_hw_consumer_enable(adc->hwc);
  1038. if (ret < 0) {
  1039. dev_err(&indio_dev->dev,
  1040. "%s: IIO enable failed (channel %d)\n",
  1041. __func__, chan->channel);
  1042. iio_device_release_direct_mode(indio_dev);
  1043. return ret;
  1044. }
  1045. ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
  1046. iio_hw_consumer_disable(adc->hwc);
  1047. if (ret < 0) {
  1048. dev_err(&indio_dev->dev,
  1049. "%s: Conversion failed (channel %d)\n",
  1050. __func__, chan->channel);
  1051. iio_device_release_direct_mode(indio_dev);
  1052. return ret;
  1053. }
  1054. iio_device_release_direct_mode(indio_dev);
  1055. return IIO_VAL_INT;
  1056. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  1057. *val = adc->oversamp;
  1058. return IIO_VAL_INT;
  1059. case IIO_CHAN_INFO_SAMP_FREQ:
  1060. *val = adc->sample_freq;
  1061. return IIO_VAL_INT;
  1062. }
  1063. return -EINVAL;
  1064. }
  1065. static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
  1066. struct iio_trigger *trig)
  1067. {
  1068. return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
  1069. }
  1070. static const struct iio_info stm32_dfsdm_info_audio = {
  1071. .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
  1072. .read_raw = stm32_dfsdm_read_raw,
  1073. .write_raw = stm32_dfsdm_write_raw,
  1074. .update_scan_mode = stm32_dfsdm_update_scan_mode,
  1075. };
  1076. static const struct iio_info stm32_dfsdm_info_adc = {
  1077. .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
  1078. .read_raw = stm32_dfsdm_read_raw,
  1079. .write_raw = stm32_dfsdm_write_raw,
  1080. .update_scan_mode = stm32_dfsdm_update_scan_mode,
  1081. .validate_trigger = stm32_dfsdm_validate_trigger,
  1082. };
  1083. static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
  1084. {
  1085. struct iio_dev *indio_dev = arg;
  1086. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1087. struct regmap *regmap = adc->dfsdm->regmap;
  1088. unsigned int status, int_en;
  1089. regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
  1090. regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
  1091. if (status & DFSDM_ISR_REOCF_MASK) {
  1092. /* Read the data register clean the IRQ status */
  1093. regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
  1094. complete(&adc->completion);
  1095. }
  1096. if (status & DFSDM_ISR_ROVRF_MASK) {
  1097. if (int_en & DFSDM_CR2_ROVRIE_MASK)
  1098. dev_warn(&indio_dev->dev, "Overrun detected\n");
  1099. regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
  1100. DFSDM_ICR_CLRROVRF_MASK,
  1101. DFSDM_ICR_CLRROVRF_MASK);
  1102. }
  1103. return IRQ_HANDLED;
  1104. }
  1105. /*
  1106. * Define external info for SPI Frequency and audio sampling rate that can be
  1107. * configured by ASoC driver through consumer.h API
  1108. */
  1109. static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
  1110. /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
  1111. {
  1112. .name = "spi_clk_freq",
  1113. .shared = IIO_SHARED_BY_TYPE,
  1114. .read = dfsdm_adc_audio_get_spiclk,
  1115. .write = dfsdm_adc_audio_set_spiclk,
  1116. },
  1117. {},
  1118. };
  1119. static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
  1120. {
  1121. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1122. if (adc->dma_chan) {
  1123. dma_free_coherent(adc->dma_chan->device->dev,
  1124. DFSDM_DMA_BUFFER_SIZE,
  1125. adc->rx_buf, adc->dma_buf);
  1126. dma_release_channel(adc->dma_chan);
  1127. }
  1128. }
  1129. static int stm32_dfsdm_dma_request(struct device *dev,
  1130. struct iio_dev *indio_dev)
  1131. {
  1132. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1133. adc->dma_chan = dma_request_chan(dev, "rx");
  1134. if (IS_ERR(adc->dma_chan)) {
  1135. int ret = PTR_ERR(adc->dma_chan);
  1136. adc->dma_chan = NULL;
  1137. return ret;
  1138. }
  1139. adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
  1140. DFSDM_DMA_BUFFER_SIZE,
  1141. &adc->dma_buf, GFP_KERNEL);
  1142. if (!adc->rx_buf) {
  1143. dma_release_channel(adc->dma_chan);
  1144. return -ENOMEM;
  1145. }
  1146. indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
  1147. indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
  1148. return 0;
  1149. }
  1150. static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
  1151. struct iio_chan_spec *ch)
  1152. {
  1153. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1154. int ret;
  1155. ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
  1156. if (ret < 0)
  1157. return ret;
  1158. ch->type = IIO_VOLTAGE;
  1159. ch->indexed = 1;
  1160. /*
  1161. * IIO_CHAN_INFO_RAW: used to compute regular conversion
  1162. * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
  1163. */
  1164. ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
  1165. ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
  1166. BIT(IIO_CHAN_INFO_SAMP_FREQ);
  1167. if (adc->dev_data->type == DFSDM_AUDIO) {
  1168. ch->ext_info = dfsdm_adc_audio_ext_info;
  1169. } else {
  1170. ch->scan_type.shift = 8;
  1171. }
  1172. ch->scan_type.sign = 's';
  1173. ch->scan_type.realbits = 24;
  1174. ch->scan_type.storagebits = 32;
  1175. return stm32_dfsdm_chan_configure(adc->dfsdm,
  1176. &adc->dfsdm->ch_list[ch->channel]);
  1177. }
  1178. static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev)
  1179. {
  1180. struct iio_chan_spec *ch;
  1181. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1182. struct stm32_dfsdm_channel *d_ch;
  1183. int ret;
  1184. ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
  1185. if (!ch)
  1186. return -ENOMEM;
  1187. ch->scan_index = 0;
  1188. ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
  1189. if (ret < 0) {
  1190. dev_err(&indio_dev->dev, "Channels init failed\n");
  1191. return ret;
  1192. }
  1193. ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
  1194. d_ch = &adc->dfsdm->ch_list[ch->channel];
  1195. if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
  1196. adc->spi_freq = adc->dfsdm->spi_master_freq;
  1197. indio_dev->num_channels = 1;
  1198. indio_dev->channels = ch;
  1199. return stm32_dfsdm_dma_request(dev, indio_dev);
  1200. }
  1201. static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev)
  1202. {
  1203. struct iio_chan_spec *ch;
  1204. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1205. int num_ch;
  1206. int ret, chan_idx;
  1207. adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
  1208. ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
  1209. if (ret < 0)
  1210. return ret;
  1211. num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
  1212. "st,adc-channels");
  1213. if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
  1214. dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
  1215. return num_ch < 0 ? num_ch : -EINVAL;
  1216. }
  1217. /* Bind to SD modulator IIO device */
  1218. adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
  1219. if (IS_ERR(adc->hwc))
  1220. return -EPROBE_DEFER;
  1221. ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
  1222. GFP_KERNEL);
  1223. if (!ch)
  1224. return -ENOMEM;
  1225. for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
  1226. ch[chan_idx].scan_index = chan_idx;
  1227. ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
  1228. if (ret < 0) {
  1229. dev_err(&indio_dev->dev, "Channels init failed\n");
  1230. return ret;
  1231. }
  1232. }
  1233. indio_dev->num_channels = num_ch;
  1234. indio_dev->channels = ch;
  1235. init_completion(&adc->completion);
  1236. /* Optionally request DMA */
  1237. ret = stm32_dfsdm_dma_request(dev, indio_dev);
  1238. if (ret) {
  1239. if (ret != -ENODEV)
  1240. return dev_err_probe(dev, ret,
  1241. "DMA channel request failed with\n");
  1242. dev_dbg(dev, "No DMA support\n");
  1243. return 0;
  1244. }
  1245. ret = iio_triggered_buffer_setup(indio_dev,
  1246. &iio_pollfunc_store_time, NULL,
  1247. &stm32_dfsdm_buffer_setup_ops);
  1248. if (ret) {
  1249. stm32_dfsdm_dma_release(indio_dev);
  1250. dev_err(&indio_dev->dev, "buffer setup failed\n");
  1251. return ret;
  1252. }
  1253. /* lptimer/timer hardware triggers */
  1254. indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
  1255. return 0;
  1256. }
  1257. static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
  1258. .type = DFSDM_IIO,
  1259. .init = stm32_dfsdm_adc_init,
  1260. };
  1261. static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
  1262. .type = DFSDM_AUDIO,
  1263. .init = stm32_dfsdm_audio_init,
  1264. };
  1265. static const struct of_device_id stm32_dfsdm_adc_match[] = {
  1266. {
  1267. .compatible = "st,stm32-dfsdm-adc",
  1268. .data = &stm32h7_dfsdm_adc_data,
  1269. },
  1270. {
  1271. .compatible = "st,stm32-dfsdm-dmic",
  1272. .data = &stm32h7_dfsdm_audio_data,
  1273. },
  1274. {}
  1275. };
  1276. static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
  1277. {
  1278. struct device *dev = &pdev->dev;
  1279. struct stm32_dfsdm_adc *adc;
  1280. struct device_node *np = dev->of_node;
  1281. const struct stm32_dfsdm_dev_data *dev_data;
  1282. struct iio_dev *iio;
  1283. char *name;
  1284. int ret, irq, val;
  1285. dev_data = of_device_get_match_data(dev);
  1286. iio = devm_iio_device_alloc(dev, sizeof(*adc));
  1287. if (!iio) {
  1288. dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
  1289. return -ENOMEM;
  1290. }
  1291. adc = iio_priv(iio);
  1292. adc->dfsdm = dev_get_drvdata(dev->parent);
  1293. iio->dev.of_node = np;
  1294. iio->modes = INDIO_DIRECT_MODE;
  1295. platform_set_drvdata(pdev, iio);
  1296. ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
  1297. if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
  1298. dev_err(dev, "Missing or bad reg property\n");
  1299. return -EINVAL;
  1300. }
  1301. name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
  1302. if (!name)
  1303. return -ENOMEM;
  1304. if (dev_data->type == DFSDM_AUDIO) {
  1305. iio->info = &stm32_dfsdm_info_audio;
  1306. snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
  1307. } else {
  1308. iio->info = &stm32_dfsdm_info_adc;
  1309. snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
  1310. }
  1311. iio->name = name;
  1312. /*
  1313. * In a first step IRQs generated for channels are not treated.
  1314. * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
  1315. */
  1316. irq = platform_get_irq(pdev, 0);
  1317. if (irq < 0)
  1318. return irq;
  1319. ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
  1320. 0, pdev->name, iio);
  1321. if (ret < 0) {
  1322. dev_err(dev, "Failed to request IRQ\n");
  1323. return ret;
  1324. }
  1325. ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
  1326. if (ret < 0) {
  1327. dev_err(dev, "Failed to set filter order\n");
  1328. return ret;
  1329. }
  1330. adc->dfsdm->fl_list[adc->fl_id].ford = val;
  1331. ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
  1332. if (!ret)
  1333. adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
  1334. adc->dev_data = dev_data;
  1335. ret = dev_data->init(dev, iio);
  1336. if (ret < 0)
  1337. return ret;
  1338. ret = iio_device_register(iio);
  1339. if (ret < 0)
  1340. goto err_cleanup;
  1341. if (dev_data->type == DFSDM_AUDIO) {
  1342. ret = of_platform_populate(np, NULL, NULL, dev);
  1343. if (ret < 0) {
  1344. dev_err(dev, "Failed to find an audio DAI\n");
  1345. goto err_unregister;
  1346. }
  1347. }
  1348. return 0;
  1349. err_unregister:
  1350. iio_device_unregister(iio);
  1351. err_cleanup:
  1352. stm32_dfsdm_dma_release(iio);
  1353. return ret;
  1354. }
  1355. static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
  1356. {
  1357. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  1358. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1359. if (adc->dev_data->type == DFSDM_AUDIO)
  1360. of_platform_depopulate(&pdev->dev);
  1361. iio_device_unregister(indio_dev);
  1362. stm32_dfsdm_dma_release(indio_dev);
  1363. return 0;
  1364. }
  1365. static int __maybe_unused stm32_dfsdm_adc_suspend(struct device *dev)
  1366. {
  1367. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1368. if (iio_buffer_enabled(indio_dev))
  1369. stm32_dfsdm_predisable(indio_dev);
  1370. return 0;
  1371. }
  1372. static int __maybe_unused stm32_dfsdm_adc_resume(struct device *dev)
  1373. {
  1374. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1375. struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
  1376. const struct iio_chan_spec *chan;
  1377. struct stm32_dfsdm_channel *ch;
  1378. int i, ret;
  1379. /* restore channels configuration */
  1380. for (i = 0; i < indio_dev->num_channels; i++) {
  1381. chan = indio_dev->channels + i;
  1382. ch = &adc->dfsdm->ch_list[chan->channel];
  1383. ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
  1384. if (ret)
  1385. return ret;
  1386. }
  1387. if (iio_buffer_enabled(indio_dev))
  1388. stm32_dfsdm_postenable(indio_dev);
  1389. return 0;
  1390. }
  1391. static SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
  1392. stm32_dfsdm_adc_suspend, stm32_dfsdm_adc_resume);
  1393. static struct platform_driver stm32_dfsdm_adc_driver = {
  1394. .driver = {
  1395. .name = "stm32-dfsdm-adc",
  1396. .of_match_table = stm32_dfsdm_adc_match,
  1397. .pm = &stm32_dfsdm_adc_pm_ops,
  1398. },
  1399. .probe = stm32_dfsdm_adc_probe,
  1400. .remove = stm32_dfsdm_adc_remove,
  1401. };
  1402. module_platform_driver(stm32_dfsdm_adc_driver);
  1403. MODULE_DESCRIPTION("STM32 sigma delta ADC");
  1404. MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
  1405. MODULE_LICENSE("GPL v2");