stm32-adc.c 58 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This file is part of STM32 ADC driver
  4. *
  5. * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  6. * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/iio/iio.h>
  13. #include <linux/iio/buffer.h>
  14. #include <linux/iio/timer/stm32-lptim-trigger.h>
  15. #include <linux/iio/timer/stm32-timer-trigger.h>
  16. #include <linux/iio/trigger.h>
  17. #include <linux/iio/trigger_consumer.h>
  18. #include <linux/iio/triggered_buffer.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/iopoll.h>
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/of.h>
  26. #include <linux/of_device.h>
  27. #include "stm32-adc-core.h"
  28. /* Number of linear calibration shadow registers / LINCALRDYW control bits */
  29. #define STM32H7_LINCALFACT_NUM 6
  30. /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
  31. #define STM32H7_BOOST_CLKRATE 20000000UL
  32. #define STM32_ADC_CH_MAX 20 /* max number of channels */
  33. #define STM32_ADC_CH_SZ 10 /* max channel name size */
  34. #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
  35. #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */
  36. #define STM32_ADC_TIMEOUT_US 100000
  37. #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
  38. #define STM32_ADC_HW_STOP_DELAY_MS 100
  39. #define STM32_DMA_BUFFER_SIZE PAGE_SIZE
  40. /* External trigger enable */
  41. enum stm32_adc_exten {
  42. STM32_EXTEN_SWTRIG,
  43. STM32_EXTEN_HWTRIG_RISING_EDGE,
  44. STM32_EXTEN_HWTRIG_FALLING_EDGE,
  45. STM32_EXTEN_HWTRIG_BOTH_EDGES,
  46. };
  47. /* extsel - trigger mux selection value */
  48. enum stm32_adc_extsel {
  49. STM32_EXT0,
  50. STM32_EXT1,
  51. STM32_EXT2,
  52. STM32_EXT3,
  53. STM32_EXT4,
  54. STM32_EXT5,
  55. STM32_EXT6,
  56. STM32_EXT7,
  57. STM32_EXT8,
  58. STM32_EXT9,
  59. STM32_EXT10,
  60. STM32_EXT11,
  61. STM32_EXT12,
  62. STM32_EXT13,
  63. STM32_EXT14,
  64. STM32_EXT15,
  65. STM32_EXT16,
  66. STM32_EXT17,
  67. STM32_EXT18,
  68. STM32_EXT19,
  69. STM32_EXT20,
  70. };
  71. /**
  72. * struct stm32_adc_trig_info - ADC trigger info
  73. * @name: name of the trigger, corresponding to its source
  74. * @extsel: trigger selection
  75. */
  76. struct stm32_adc_trig_info {
  77. const char *name;
  78. enum stm32_adc_extsel extsel;
  79. };
  80. /**
  81. * struct stm32_adc_calib - optional adc calibration data
  82. * @calfact_s: Calibration offset for single ended channels
  83. * @calfact_d: Calibration offset in differential
  84. * @lincalfact: Linearity calibration factor
  85. * @calibrated: Indicates calibration status
  86. */
  87. struct stm32_adc_calib {
  88. u32 calfact_s;
  89. u32 calfact_d;
  90. u32 lincalfact[STM32H7_LINCALFACT_NUM];
  91. bool calibrated;
  92. };
  93. /**
  94. * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
  95. * @reg: register offset
  96. * @mask: bitfield mask
  97. * @shift: left shift
  98. */
  99. struct stm32_adc_regs {
  100. int reg;
  101. int mask;
  102. int shift;
  103. };
  104. /**
  105. * struct stm32_adc_regspec - stm32 registers definition
  106. * @dr: data register offset
  107. * @ier_eoc: interrupt enable register & eocie bitfield
  108. * @ier_ovr: interrupt enable register & overrun bitfield
  109. * @isr_eoc: interrupt status register & eoc bitfield
  110. * @isr_ovr: interrupt status register & overrun bitfield
  111. * @sqr: reference to sequence registers array
  112. * @exten: trigger control register & bitfield
  113. * @extsel: trigger selection register & bitfield
  114. * @res: resolution selection register & bitfield
  115. * @smpr: smpr1 & smpr2 registers offset array
  116. * @smp_bits: smpr1 & smpr2 index and bitfields
  117. */
  118. struct stm32_adc_regspec {
  119. const u32 dr;
  120. const struct stm32_adc_regs ier_eoc;
  121. const struct stm32_adc_regs ier_ovr;
  122. const struct stm32_adc_regs isr_eoc;
  123. const struct stm32_adc_regs isr_ovr;
  124. const struct stm32_adc_regs *sqr;
  125. const struct stm32_adc_regs exten;
  126. const struct stm32_adc_regs extsel;
  127. const struct stm32_adc_regs res;
  128. const u32 smpr[2];
  129. const struct stm32_adc_regs *smp_bits;
  130. };
  131. struct stm32_adc;
  132. /**
  133. * struct stm32_adc_cfg - stm32 compatible configuration data
  134. * @regs: registers descriptions
  135. * @adc_info: per instance input channels definitions
  136. * @trigs: external trigger sources
  137. * @clk_required: clock is required
  138. * @has_vregready: vregready status flag presence
  139. * @prepare: optional prepare routine (power-up, enable)
  140. * @start_conv: routine to start conversions
  141. * @stop_conv: routine to stop conversions
  142. * @unprepare: optional unprepare routine (disable, power-down)
  143. * @irq_clear: routine to clear irqs
  144. * @smp_cycles: programmable sampling time (ADC clock cycles)
  145. */
  146. struct stm32_adc_cfg {
  147. const struct stm32_adc_regspec *regs;
  148. const struct stm32_adc_info *adc_info;
  149. struct stm32_adc_trig_info *trigs;
  150. bool clk_required;
  151. bool has_vregready;
  152. int (*prepare)(struct iio_dev *);
  153. void (*start_conv)(struct iio_dev *, bool dma);
  154. void (*stop_conv)(struct iio_dev *);
  155. void (*unprepare)(struct iio_dev *);
  156. void (*irq_clear)(struct iio_dev *indio_dev, u32 msk);
  157. const unsigned int *smp_cycles;
  158. };
  159. /**
  160. * struct stm32_adc - private data of each ADC IIO instance
  161. * @common: reference to ADC block common data
  162. * @offset: ADC instance register offset in ADC block
  163. * @cfg: compatible configuration data
  164. * @completion: end of single conversion completion
  165. * @buffer: data buffer
  166. * @clk: clock for this adc instance
  167. * @irq: interrupt for this adc instance
  168. * @lock: spinlock
  169. * @bufi: data buffer index
  170. * @num_conv: expected number of scan conversions
  171. * @res: data resolution (e.g. RES bitfield value)
  172. * @trigger_polarity: external trigger polarity (e.g. exten)
  173. * @dma_chan: dma channel
  174. * @rx_buf: dma rx buffer cpu address
  175. * @rx_dma_buf: dma rx buffer bus address
  176. * @rx_buf_sz: dma rx buffer size
  177. * @difsel: bitmask to set single-ended/differential channel
  178. * @pcsel: bitmask to preselect channels on some devices
  179. * @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
  180. * @cal: optional calibration data on some devices
  181. * @chan_name: channel name array
  182. */
  183. struct stm32_adc {
  184. struct stm32_adc_common *common;
  185. u32 offset;
  186. const struct stm32_adc_cfg *cfg;
  187. struct completion completion;
  188. u16 buffer[STM32_ADC_MAX_SQ];
  189. struct clk *clk;
  190. int irq;
  191. spinlock_t lock; /* interrupt lock */
  192. unsigned int bufi;
  193. unsigned int num_conv;
  194. u32 res;
  195. u32 trigger_polarity;
  196. struct dma_chan *dma_chan;
  197. u8 *rx_buf;
  198. dma_addr_t rx_dma_buf;
  199. unsigned int rx_buf_sz;
  200. u32 difsel;
  201. u32 pcsel;
  202. u32 smpr_val[2];
  203. struct stm32_adc_calib cal;
  204. char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ];
  205. };
  206. struct stm32_adc_diff_channel {
  207. u32 vinp;
  208. u32 vinn;
  209. };
  210. /**
  211. * struct stm32_adc_info - stm32 ADC, per instance config data
  212. * @max_channels: Number of channels
  213. * @resolutions: available resolutions
  214. * @num_res: number of available resolutions
  215. */
  216. struct stm32_adc_info {
  217. int max_channels;
  218. const unsigned int *resolutions;
  219. const unsigned int num_res;
  220. };
  221. static const unsigned int stm32f4_adc_resolutions[] = {
  222. /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
  223. 12, 10, 8, 6,
  224. };
  225. /* stm32f4 can have up to 16 channels */
  226. static const struct stm32_adc_info stm32f4_adc_info = {
  227. .max_channels = 16,
  228. .resolutions = stm32f4_adc_resolutions,
  229. .num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
  230. };
  231. static const unsigned int stm32h7_adc_resolutions[] = {
  232. /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
  233. 16, 14, 12, 10, 8,
  234. };
  235. /* stm32h7 can have up to 20 channels */
  236. static const struct stm32_adc_info stm32h7_adc_info = {
  237. .max_channels = STM32_ADC_CH_MAX,
  238. .resolutions = stm32h7_adc_resolutions,
  239. .num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
  240. };
  241. /*
  242. * stm32f4_sq - describe regular sequence registers
  243. * - L: sequence len (register & bit field)
  244. * - SQ1..SQ16: sequence entries (register & bit field)
  245. */
  246. static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
  247. /* L: len bit field description to be kept as first element */
  248. { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
  249. /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
  250. { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
  251. { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
  252. { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
  253. { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
  254. { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
  255. { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
  256. { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
  257. { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
  258. { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
  259. { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
  260. { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
  261. { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
  262. { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
  263. { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
  264. { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
  265. { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
  266. };
  267. /* STM32F4 external trigger sources for all instances */
  268. static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
  269. { TIM1_CH1, STM32_EXT0 },
  270. { TIM1_CH2, STM32_EXT1 },
  271. { TIM1_CH3, STM32_EXT2 },
  272. { TIM2_CH2, STM32_EXT3 },
  273. { TIM2_CH3, STM32_EXT4 },
  274. { TIM2_CH4, STM32_EXT5 },
  275. { TIM2_TRGO, STM32_EXT6 },
  276. { TIM3_CH1, STM32_EXT7 },
  277. { TIM3_TRGO, STM32_EXT8 },
  278. { TIM4_CH4, STM32_EXT9 },
  279. { TIM5_CH1, STM32_EXT10 },
  280. { TIM5_CH2, STM32_EXT11 },
  281. { TIM5_CH3, STM32_EXT12 },
  282. { TIM8_CH1, STM32_EXT13 },
  283. { TIM8_TRGO, STM32_EXT14 },
  284. {}, /* sentinel */
  285. };
  286. /*
  287. * stm32f4_smp_bits[] - describe sampling time register index & bit fields
  288. * Sorted so it can be indexed by channel number.
  289. */
  290. static const struct stm32_adc_regs stm32f4_smp_bits[] = {
  291. /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
  292. { 1, GENMASK(2, 0), 0 },
  293. { 1, GENMASK(5, 3), 3 },
  294. { 1, GENMASK(8, 6), 6 },
  295. { 1, GENMASK(11, 9), 9 },
  296. { 1, GENMASK(14, 12), 12 },
  297. { 1, GENMASK(17, 15), 15 },
  298. { 1, GENMASK(20, 18), 18 },
  299. { 1, GENMASK(23, 21), 21 },
  300. { 1, GENMASK(26, 24), 24 },
  301. { 1, GENMASK(29, 27), 27 },
  302. /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
  303. { 0, GENMASK(2, 0), 0 },
  304. { 0, GENMASK(5, 3), 3 },
  305. { 0, GENMASK(8, 6), 6 },
  306. { 0, GENMASK(11, 9), 9 },
  307. { 0, GENMASK(14, 12), 12 },
  308. { 0, GENMASK(17, 15), 15 },
  309. { 0, GENMASK(20, 18), 18 },
  310. { 0, GENMASK(23, 21), 21 },
  311. { 0, GENMASK(26, 24), 24 },
  312. };
  313. /* STM32F4 programmable sampling time (ADC clock cycles) */
  314. static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
  315. 3, 15, 28, 56, 84, 112, 144, 480,
  316. };
  317. static const struct stm32_adc_regspec stm32f4_adc_regspec = {
  318. .dr = STM32F4_ADC_DR,
  319. .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
  320. .ier_ovr = { STM32F4_ADC_CR1, STM32F4_OVRIE },
  321. .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
  322. .isr_ovr = { STM32F4_ADC_SR, STM32F4_OVR },
  323. .sqr = stm32f4_sq,
  324. .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
  325. .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
  326. STM32F4_EXTSEL_SHIFT },
  327. .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
  328. .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
  329. .smp_bits = stm32f4_smp_bits,
  330. };
  331. static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
  332. /* L: len bit field description to be kept as first element */
  333. { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
  334. /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
  335. { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
  336. { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
  337. { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
  338. { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
  339. { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
  340. { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
  341. { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
  342. { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
  343. { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
  344. { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
  345. { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
  346. { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
  347. { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
  348. { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
  349. { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
  350. { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
  351. };
  352. /* STM32H7 external trigger sources for all instances */
  353. static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
  354. { TIM1_CH1, STM32_EXT0 },
  355. { TIM1_CH2, STM32_EXT1 },
  356. { TIM1_CH3, STM32_EXT2 },
  357. { TIM2_CH2, STM32_EXT3 },
  358. { TIM3_TRGO, STM32_EXT4 },
  359. { TIM4_CH4, STM32_EXT5 },
  360. { TIM8_TRGO, STM32_EXT7 },
  361. { TIM8_TRGO2, STM32_EXT8 },
  362. { TIM1_TRGO, STM32_EXT9 },
  363. { TIM1_TRGO2, STM32_EXT10 },
  364. { TIM2_TRGO, STM32_EXT11 },
  365. { TIM4_TRGO, STM32_EXT12 },
  366. { TIM6_TRGO, STM32_EXT13 },
  367. { TIM15_TRGO, STM32_EXT14 },
  368. { TIM3_CH4, STM32_EXT15 },
  369. { LPTIM1_OUT, STM32_EXT18 },
  370. { LPTIM2_OUT, STM32_EXT19 },
  371. { LPTIM3_OUT, STM32_EXT20 },
  372. {},
  373. };
  374. /*
  375. * stm32h7_smp_bits - describe sampling time register index & bit fields
  376. * Sorted so it can be indexed by channel number.
  377. */
  378. static const struct stm32_adc_regs stm32h7_smp_bits[] = {
  379. /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
  380. { 0, GENMASK(2, 0), 0 },
  381. { 0, GENMASK(5, 3), 3 },
  382. { 0, GENMASK(8, 6), 6 },
  383. { 0, GENMASK(11, 9), 9 },
  384. { 0, GENMASK(14, 12), 12 },
  385. { 0, GENMASK(17, 15), 15 },
  386. { 0, GENMASK(20, 18), 18 },
  387. { 0, GENMASK(23, 21), 21 },
  388. { 0, GENMASK(26, 24), 24 },
  389. { 0, GENMASK(29, 27), 27 },
  390. /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
  391. { 1, GENMASK(2, 0), 0 },
  392. { 1, GENMASK(5, 3), 3 },
  393. { 1, GENMASK(8, 6), 6 },
  394. { 1, GENMASK(11, 9), 9 },
  395. { 1, GENMASK(14, 12), 12 },
  396. { 1, GENMASK(17, 15), 15 },
  397. { 1, GENMASK(20, 18), 18 },
  398. { 1, GENMASK(23, 21), 21 },
  399. { 1, GENMASK(26, 24), 24 },
  400. { 1, GENMASK(29, 27), 27 },
  401. };
  402. /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
  403. static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
  404. 1, 2, 8, 16, 32, 64, 387, 810,
  405. };
  406. static const struct stm32_adc_regspec stm32h7_adc_regspec = {
  407. .dr = STM32H7_ADC_DR,
  408. .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
  409. .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE },
  410. .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
  411. .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR },
  412. .sqr = stm32h7_sq,
  413. .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
  414. .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
  415. STM32H7_EXTSEL_SHIFT },
  416. .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
  417. .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
  418. .smp_bits = stm32h7_smp_bits,
  419. };
  420. /**
  421. * STM32 ADC registers access routines
  422. * @adc: stm32 adc instance
  423. * @reg: reg offset in adc instance
  424. *
  425. * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
  426. * for adc1, adc2 and adc3.
  427. */
  428. static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
  429. {
  430. return readl_relaxed(adc->common->base + adc->offset + reg);
  431. }
  432. #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
  433. #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
  434. readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
  435. cond, sleep_us, timeout_us)
  436. static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
  437. {
  438. return readw_relaxed(adc->common->base + adc->offset + reg);
  439. }
  440. static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
  441. {
  442. writel_relaxed(val, adc->common->base + adc->offset + reg);
  443. }
  444. static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
  445. {
  446. unsigned long flags;
  447. spin_lock_irqsave(&adc->lock, flags);
  448. stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
  449. spin_unlock_irqrestore(&adc->lock, flags);
  450. }
  451. static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
  452. {
  453. unsigned long flags;
  454. spin_lock_irqsave(&adc->lock, flags);
  455. stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
  456. spin_unlock_irqrestore(&adc->lock, flags);
  457. }
  458. /**
  459. * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
  460. * @adc: stm32 adc instance
  461. */
  462. static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
  463. {
  464. stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
  465. adc->cfg->regs->ier_eoc.mask);
  466. };
  467. /**
  468. * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
  469. * @adc: stm32 adc instance
  470. */
  471. static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
  472. {
  473. stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
  474. adc->cfg->regs->ier_eoc.mask);
  475. }
  476. static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc)
  477. {
  478. stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg,
  479. adc->cfg->regs->ier_ovr.mask);
  480. }
  481. static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc)
  482. {
  483. stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg,
  484. adc->cfg->regs->ier_ovr.mask);
  485. }
  486. static void stm32_adc_set_res(struct stm32_adc *adc)
  487. {
  488. const struct stm32_adc_regs *res = &adc->cfg->regs->res;
  489. u32 val;
  490. val = stm32_adc_readl(adc, res->reg);
  491. val = (val & ~res->mask) | (adc->res << res->shift);
  492. stm32_adc_writel(adc, res->reg, val);
  493. }
  494. static int stm32_adc_hw_stop(struct device *dev)
  495. {
  496. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  497. struct stm32_adc *adc = iio_priv(indio_dev);
  498. if (adc->cfg->unprepare)
  499. adc->cfg->unprepare(indio_dev);
  500. if (adc->clk)
  501. clk_disable_unprepare(adc->clk);
  502. return 0;
  503. }
  504. static int stm32_adc_hw_start(struct device *dev)
  505. {
  506. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  507. struct stm32_adc *adc = iio_priv(indio_dev);
  508. int ret;
  509. if (adc->clk) {
  510. ret = clk_prepare_enable(adc->clk);
  511. if (ret)
  512. return ret;
  513. }
  514. stm32_adc_set_res(adc);
  515. if (adc->cfg->prepare) {
  516. ret = adc->cfg->prepare(indio_dev);
  517. if (ret)
  518. goto err_clk_dis;
  519. }
  520. return 0;
  521. err_clk_dis:
  522. if (adc->clk)
  523. clk_disable_unprepare(adc->clk);
  524. return ret;
  525. }
  526. /**
  527. * stm32f4_adc_start_conv() - Start conversions for regular channels.
  528. * @indio_dev: IIO device instance
  529. * @dma: use dma to transfer conversion result
  530. *
  531. * Start conversions for regular channels.
  532. * Also take care of normal or DMA mode. Circular DMA may be used for regular
  533. * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
  534. * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
  535. */
  536. static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma)
  537. {
  538. struct stm32_adc *adc = iio_priv(indio_dev);
  539. stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
  540. if (dma)
  541. stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
  542. STM32F4_DMA | STM32F4_DDS);
  543. stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
  544. /* Wait for Power-up time (tSTAB from datasheet) */
  545. usleep_range(2, 3);
  546. /* Software start ? (e.g. trigger detection disabled ?) */
  547. if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
  548. stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
  549. }
  550. static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev)
  551. {
  552. struct stm32_adc *adc = iio_priv(indio_dev);
  553. stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
  554. stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
  555. stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
  556. stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
  557. STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
  558. }
  559. static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
  560. {
  561. struct stm32_adc *adc = iio_priv(indio_dev);
  562. stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
  563. }
  564. static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma)
  565. {
  566. struct stm32_adc *adc = iio_priv(indio_dev);
  567. enum stm32h7_adc_dmngt dmngt;
  568. unsigned long flags;
  569. u32 val;
  570. if (dma)
  571. dmngt = STM32H7_DMNGT_DMA_CIRC;
  572. else
  573. dmngt = STM32H7_DMNGT_DR_ONLY;
  574. spin_lock_irqsave(&adc->lock, flags);
  575. val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
  576. val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
  577. stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
  578. spin_unlock_irqrestore(&adc->lock, flags);
  579. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
  580. }
  581. static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev)
  582. {
  583. struct stm32_adc *adc = iio_priv(indio_dev);
  584. int ret;
  585. u32 val;
  586. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
  587. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
  588. !(val & (STM32H7_ADSTART)),
  589. 100, STM32_ADC_TIMEOUT_US);
  590. if (ret)
  591. dev_warn(&indio_dev->dev, "stop failed\n");
  592. stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
  593. }
  594. static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
  595. {
  596. struct stm32_adc *adc = iio_priv(indio_dev);
  597. /* On STM32H7 IRQs are cleared by writing 1 into ISR register */
  598. stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
  599. }
  600. static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev)
  601. {
  602. struct stm32_adc *adc = iio_priv(indio_dev);
  603. int ret;
  604. u32 val;
  605. /* Exit deep power down, then enable ADC voltage regulator */
  606. stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
  607. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
  608. if (adc->common->rate > STM32H7_BOOST_CLKRATE)
  609. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
  610. /* Wait for startup time */
  611. if (!adc->cfg->has_vregready) {
  612. usleep_range(10, 20);
  613. return 0;
  614. }
  615. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
  616. val & STM32MP1_VREGREADY, 100,
  617. STM32_ADC_TIMEOUT_US);
  618. if (ret) {
  619. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
  620. dev_err(&indio_dev->dev, "Failed to exit power down\n");
  621. }
  622. return ret;
  623. }
  624. static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
  625. {
  626. stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
  627. /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
  628. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
  629. }
  630. static int stm32h7_adc_enable(struct iio_dev *indio_dev)
  631. {
  632. struct stm32_adc *adc = iio_priv(indio_dev);
  633. int ret;
  634. u32 val;
  635. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
  636. /* Poll for ADRDY to be set (after adc startup time) */
  637. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
  638. val & STM32H7_ADRDY,
  639. 100, STM32_ADC_TIMEOUT_US);
  640. if (ret) {
  641. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
  642. dev_err(&indio_dev->dev, "Failed to enable ADC\n");
  643. } else {
  644. /* Clear ADRDY by writing one */
  645. stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
  646. }
  647. return ret;
  648. }
  649. static void stm32h7_adc_disable(struct iio_dev *indio_dev)
  650. {
  651. struct stm32_adc *adc = iio_priv(indio_dev);
  652. int ret;
  653. u32 val;
  654. /* Disable ADC and wait until it's effectively disabled */
  655. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
  656. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
  657. !(val & STM32H7_ADEN), 100,
  658. STM32_ADC_TIMEOUT_US);
  659. if (ret)
  660. dev_warn(&indio_dev->dev, "Failed to disable\n");
  661. }
  662. /**
  663. * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
  664. * @indio_dev: IIO device instance
  665. * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
  666. */
  667. static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev)
  668. {
  669. struct stm32_adc *adc = iio_priv(indio_dev);
  670. int i, ret;
  671. u32 lincalrdyw_mask, val;
  672. /* Read linearity calibration */
  673. lincalrdyw_mask = STM32H7_LINCALRDYW6;
  674. for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
  675. /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
  676. stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
  677. /* Poll: wait calib data to be ready in CALFACT2 register */
  678. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
  679. !(val & lincalrdyw_mask),
  680. 100, STM32_ADC_TIMEOUT_US);
  681. if (ret) {
  682. dev_err(&indio_dev->dev, "Failed to read calfact\n");
  683. return ret;
  684. }
  685. val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
  686. adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
  687. adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
  688. lincalrdyw_mask >>= 1;
  689. }
  690. /* Read offset calibration */
  691. val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
  692. adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
  693. adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
  694. adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
  695. adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
  696. adc->cal.calibrated = true;
  697. return 0;
  698. }
  699. /**
  700. * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
  701. * @indio_dev: IIO device instance
  702. * Note: ADC must be enabled, with no on-going conversions.
  703. */
  704. static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev)
  705. {
  706. struct stm32_adc *adc = iio_priv(indio_dev);
  707. int i, ret;
  708. u32 lincalrdyw_mask, val;
  709. val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
  710. (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
  711. stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
  712. lincalrdyw_mask = STM32H7_LINCALRDYW6;
  713. for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
  714. /*
  715. * Write saved calibration data to shadow registers:
  716. * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
  717. * data write. Then poll to wait for complete transfer.
  718. */
  719. val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
  720. stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
  721. stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
  722. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
  723. val & lincalrdyw_mask,
  724. 100, STM32_ADC_TIMEOUT_US);
  725. if (ret) {
  726. dev_err(&indio_dev->dev, "Failed to write calfact\n");
  727. return ret;
  728. }
  729. /*
  730. * Read back calibration data, has two effects:
  731. * - It ensures bits LINCALRDYW[6..1] are kept cleared
  732. * for next time calibration needs to be restored.
  733. * - BTW, bit clear triggers a read, then check data has been
  734. * correctly written.
  735. */
  736. stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
  737. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
  738. !(val & lincalrdyw_mask),
  739. 100, STM32_ADC_TIMEOUT_US);
  740. if (ret) {
  741. dev_err(&indio_dev->dev, "Failed to read calfact\n");
  742. return ret;
  743. }
  744. val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
  745. if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
  746. dev_err(&indio_dev->dev, "calfact not consistent\n");
  747. return -EIO;
  748. }
  749. lincalrdyw_mask >>= 1;
  750. }
  751. return 0;
  752. }
  753. /**
  754. * Fixed timeout value for ADC calibration.
  755. * worst cases:
  756. * - low clock frequency
  757. * - maximum prescalers
  758. * Calibration requires:
  759. * - 131,072 ADC clock cycle for the linear calibration
  760. * - 20 ADC clock cycle for the offset calibration
  761. *
  762. * Set to 100ms for now
  763. */
  764. #define STM32H7_ADC_CALIB_TIMEOUT_US 100000
  765. /**
  766. * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
  767. * @indio_dev: IIO device instance
  768. * Note: Must be called once ADC is out of power down.
  769. */
  770. static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev)
  771. {
  772. struct stm32_adc *adc = iio_priv(indio_dev);
  773. int ret;
  774. u32 val;
  775. if (adc->cal.calibrated)
  776. return true;
  777. /*
  778. * Select calibration mode:
  779. * - Offset calibration for single ended inputs
  780. * - No linearity calibration (do it later, before reading it)
  781. */
  782. stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
  783. stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
  784. /* Start calibration, then wait for completion */
  785. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
  786. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
  787. !(val & STM32H7_ADCAL), 100,
  788. STM32H7_ADC_CALIB_TIMEOUT_US);
  789. if (ret) {
  790. dev_err(&indio_dev->dev, "calibration failed\n");
  791. goto out;
  792. }
  793. /*
  794. * Select calibration mode, then start calibration:
  795. * - Offset calibration for differential input
  796. * - Linearity calibration (needs to be done only once for single/diff)
  797. * will run simultaneously with offset calibration.
  798. */
  799. stm32_adc_set_bits(adc, STM32H7_ADC_CR,
  800. STM32H7_ADCALDIF | STM32H7_ADCALLIN);
  801. stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
  802. ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
  803. !(val & STM32H7_ADCAL), 100,
  804. STM32H7_ADC_CALIB_TIMEOUT_US);
  805. if (ret) {
  806. dev_err(&indio_dev->dev, "calibration failed\n");
  807. goto out;
  808. }
  809. out:
  810. stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
  811. STM32H7_ADCALDIF | STM32H7_ADCALLIN);
  812. return ret;
  813. }
  814. /**
  815. * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
  816. * @indio_dev: IIO device instance
  817. * Leave power down mode.
  818. * Configure channels as single ended or differential before enabling ADC.
  819. * Enable ADC.
  820. * Restore calibration data.
  821. * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
  822. * - Only one input is selected for single ended (e.g. 'vinp')
  823. * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
  824. */
  825. static int stm32h7_adc_prepare(struct iio_dev *indio_dev)
  826. {
  827. struct stm32_adc *adc = iio_priv(indio_dev);
  828. int calib, ret;
  829. ret = stm32h7_adc_exit_pwr_down(indio_dev);
  830. if (ret)
  831. return ret;
  832. ret = stm32h7_adc_selfcalib(indio_dev);
  833. if (ret < 0)
  834. goto pwr_dwn;
  835. calib = ret;
  836. stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);
  837. ret = stm32h7_adc_enable(indio_dev);
  838. if (ret)
  839. goto pwr_dwn;
  840. /* Either restore or read calibration result for future reference */
  841. if (calib)
  842. ret = stm32h7_adc_restore_selfcalib(indio_dev);
  843. else
  844. ret = stm32h7_adc_read_selfcalib(indio_dev);
  845. if (ret)
  846. goto disable;
  847. stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
  848. return 0;
  849. disable:
  850. stm32h7_adc_disable(indio_dev);
  851. pwr_dwn:
  852. stm32h7_adc_enter_pwr_down(adc);
  853. return ret;
  854. }
  855. static void stm32h7_adc_unprepare(struct iio_dev *indio_dev)
  856. {
  857. struct stm32_adc *adc = iio_priv(indio_dev);
  858. stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0);
  859. stm32h7_adc_disable(indio_dev);
  860. stm32h7_adc_enter_pwr_down(adc);
  861. }
  862. /**
  863. * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
  864. * @indio_dev: IIO device
  865. * @scan_mask: channels to be converted
  866. *
  867. * Conversion sequence :
  868. * Apply sampling time settings for all channels.
  869. * Configure ADC scan sequence based on selected channels in scan_mask.
  870. * Add channels to SQR registers, from scan_mask LSB to MSB, then
  871. * program sequence len.
  872. */
  873. static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
  874. const unsigned long *scan_mask)
  875. {
  876. struct stm32_adc *adc = iio_priv(indio_dev);
  877. const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
  878. const struct iio_chan_spec *chan;
  879. u32 val, bit;
  880. int i = 0;
  881. /* Apply sampling time settings */
  882. stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
  883. stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
  884. for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
  885. chan = indio_dev->channels + bit;
  886. /*
  887. * Assign one channel per SQ entry in regular
  888. * sequence, starting with SQ1.
  889. */
  890. i++;
  891. if (i > STM32_ADC_MAX_SQ)
  892. return -EINVAL;
  893. dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
  894. __func__, chan->channel, i);
  895. val = stm32_adc_readl(adc, sqr[i].reg);
  896. val &= ~sqr[i].mask;
  897. val |= chan->channel << sqr[i].shift;
  898. stm32_adc_writel(adc, sqr[i].reg, val);
  899. }
  900. if (!i)
  901. return -EINVAL;
  902. /* Sequence len */
  903. val = stm32_adc_readl(adc, sqr[0].reg);
  904. val &= ~sqr[0].mask;
  905. val |= ((i - 1) << sqr[0].shift);
  906. stm32_adc_writel(adc, sqr[0].reg, val);
  907. return 0;
  908. }
  909. /**
  910. * stm32_adc_get_trig_extsel() - Get external trigger selection
  911. * @indio_dev: IIO device structure
  912. * @trig: trigger
  913. *
  914. * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
  915. */
  916. static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
  917. struct iio_trigger *trig)
  918. {
  919. struct stm32_adc *adc = iio_priv(indio_dev);
  920. int i;
  921. /* lookup triggers registered by stm32 timer trigger driver */
  922. for (i = 0; adc->cfg->trigs[i].name; i++) {
  923. /**
  924. * Checking both stm32 timer trigger type and trig name
  925. * should be safe against arbitrary trigger names.
  926. */
  927. if ((is_stm32_timer_trigger(trig) ||
  928. is_stm32_lptim_trigger(trig)) &&
  929. !strcmp(adc->cfg->trigs[i].name, trig->name)) {
  930. return adc->cfg->trigs[i].extsel;
  931. }
  932. }
  933. return -EINVAL;
  934. }
  935. /**
  936. * stm32_adc_set_trig() - Set a regular trigger
  937. * @indio_dev: IIO device
  938. * @trig: IIO trigger
  939. *
  940. * Set trigger source/polarity (e.g. SW, or HW with polarity) :
  941. * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
  942. * - if HW trigger enabled, set source & polarity
  943. */
  944. static int stm32_adc_set_trig(struct iio_dev *indio_dev,
  945. struct iio_trigger *trig)
  946. {
  947. struct stm32_adc *adc = iio_priv(indio_dev);
  948. u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
  949. unsigned long flags;
  950. int ret;
  951. if (trig) {
  952. ret = stm32_adc_get_trig_extsel(indio_dev, trig);
  953. if (ret < 0)
  954. return ret;
  955. /* set trigger source and polarity (default to rising edge) */
  956. extsel = ret;
  957. exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
  958. }
  959. spin_lock_irqsave(&adc->lock, flags);
  960. val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
  961. val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
  962. val |= exten << adc->cfg->regs->exten.shift;
  963. val |= extsel << adc->cfg->regs->extsel.shift;
  964. stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
  965. spin_unlock_irqrestore(&adc->lock, flags);
  966. return 0;
  967. }
  968. static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
  969. const struct iio_chan_spec *chan,
  970. unsigned int type)
  971. {
  972. struct stm32_adc *adc = iio_priv(indio_dev);
  973. adc->trigger_polarity = type;
  974. return 0;
  975. }
  976. static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
  977. const struct iio_chan_spec *chan)
  978. {
  979. struct stm32_adc *adc = iio_priv(indio_dev);
  980. return adc->trigger_polarity;
  981. }
  982. static const char * const stm32_trig_pol_items[] = {
  983. "rising-edge", "falling-edge", "both-edges",
  984. };
  985. static const struct iio_enum stm32_adc_trig_pol = {
  986. .items = stm32_trig_pol_items,
  987. .num_items = ARRAY_SIZE(stm32_trig_pol_items),
  988. .get = stm32_adc_get_trig_pol,
  989. .set = stm32_adc_set_trig_pol,
  990. };
  991. /**
  992. * stm32_adc_single_conv() - Performs a single conversion
  993. * @indio_dev: IIO device
  994. * @chan: IIO channel
  995. * @res: conversion result
  996. *
  997. * The function performs a single conversion on a given channel:
  998. * - Apply sampling time settings
  999. * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
  1000. * - Use SW trigger
  1001. * - Start conversion, then wait for interrupt completion.
  1002. */
  1003. static int stm32_adc_single_conv(struct iio_dev *indio_dev,
  1004. const struct iio_chan_spec *chan,
  1005. int *res)
  1006. {
  1007. struct stm32_adc *adc = iio_priv(indio_dev);
  1008. struct device *dev = indio_dev->dev.parent;
  1009. const struct stm32_adc_regspec *regs = adc->cfg->regs;
  1010. long timeout;
  1011. u32 val;
  1012. int ret;
  1013. reinit_completion(&adc->completion);
  1014. adc->bufi = 0;
  1015. ret = pm_runtime_get_sync(dev);
  1016. if (ret < 0) {
  1017. pm_runtime_put_noidle(dev);
  1018. return ret;
  1019. }
  1020. /* Apply sampling time settings */
  1021. stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
  1022. stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
  1023. /* Program chan number in regular sequence (SQ1) */
  1024. val = stm32_adc_readl(adc, regs->sqr[1].reg);
  1025. val &= ~regs->sqr[1].mask;
  1026. val |= chan->channel << regs->sqr[1].shift;
  1027. stm32_adc_writel(adc, regs->sqr[1].reg, val);
  1028. /* Set regular sequence len (0 for 1 conversion) */
  1029. stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
  1030. /* Trigger detection disabled (conversion can be launched in SW) */
  1031. stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
  1032. stm32_adc_conv_irq_enable(adc);
  1033. adc->cfg->start_conv(indio_dev, false);
  1034. timeout = wait_for_completion_interruptible_timeout(
  1035. &adc->completion, STM32_ADC_TIMEOUT);
  1036. if (timeout == 0) {
  1037. ret = -ETIMEDOUT;
  1038. } else if (timeout < 0) {
  1039. ret = timeout;
  1040. } else {
  1041. *res = adc->buffer[0];
  1042. ret = IIO_VAL_INT;
  1043. }
  1044. adc->cfg->stop_conv(indio_dev);
  1045. stm32_adc_conv_irq_disable(adc);
  1046. pm_runtime_mark_last_busy(dev);
  1047. pm_runtime_put_autosuspend(dev);
  1048. return ret;
  1049. }
  1050. static int stm32_adc_read_raw(struct iio_dev *indio_dev,
  1051. struct iio_chan_spec const *chan,
  1052. int *val, int *val2, long mask)
  1053. {
  1054. struct stm32_adc *adc = iio_priv(indio_dev);
  1055. int ret;
  1056. switch (mask) {
  1057. case IIO_CHAN_INFO_RAW:
  1058. ret = iio_device_claim_direct_mode(indio_dev);
  1059. if (ret)
  1060. return ret;
  1061. if (chan->type == IIO_VOLTAGE)
  1062. ret = stm32_adc_single_conv(indio_dev, chan, val);
  1063. else
  1064. ret = -EINVAL;
  1065. iio_device_release_direct_mode(indio_dev);
  1066. return ret;
  1067. case IIO_CHAN_INFO_SCALE:
  1068. if (chan->differential) {
  1069. *val = adc->common->vref_mv * 2;
  1070. *val2 = chan->scan_type.realbits;
  1071. } else {
  1072. *val = adc->common->vref_mv;
  1073. *val2 = chan->scan_type.realbits;
  1074. }
  1075. return IIO_VAL_FRACTIONAL_LOG2;
  1076. case IIO_CHAN_INFO_OFFSET:
  1077. if (chan->differential)
  1078. /* ADC_full_scale / 2 */
  1079. *val = -((1 << chan->scan_type.realbits) / 2);
  1080. else
  1081. *val = 0;
  1082. return IIO_VAL_INT;
  1083. default:
  1084. return -EINVAL;
  1085. }
  1086. }
  1087. static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
  1088. {
  1089. struct stm32_adc *adc = iio_priv(indio_dev);
  1090. adc->cfg->irq_clear(indio_dev, msk);
  1091. }
  1092. static irqreturn_t stm32_adc_threaded_isr(int irq, void *data)
  1093. {
  1094. struct iio_dev *indio_dev = data;
  1095. struct stm32_adc *adc = iio_priv(indio_dev);
  1096. const struct stm32_adc_regspec *regs = adc->cfg->regs;
  1097. u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
  1098. u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg);
  1099. /* Check ovr status right now, as ovr mask should be already disabled */
  1100. if (status & regs->isr_ovr.mask) {
  1101. /*
  1102. * Clear ovr bit to avoid subsequent calls to IRQ handler.
  1103. * This requires to stop ADC first. OVR bit state in ISR,
  1104. * is propaged to CSR register by hardware.
  1105. */
  1106. adc->cfg->stop_conv(indio_dev);
  1107. stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask);
  1108. dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n");
  1109. return IRQ_HANDLED;
  1110. }
  1111. if (!(status & mask))
  1112. dev_err_ratelimited(&indio_dev->dev,
  1113. "Unexpected IRQ: IER=0x%08x, ISR=0x%08x\n",
  1114. mask, status);
  1115. return IRQ_NONE;
  1116. }
  1117. static irqreturn_t stm32_adc_isr(int irq, void *data)
  1118. {
  1119. struct iio_dev *indio_dev = data;
  1120. struct stm32_adc *adc = iio_priv(indio_dev);
  1121. const struct stm32_adc_regspec *regs = adc->cfg->regs;
  1122. u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
  1123. u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg);
  1124. if (!(status & mask))
  1125. return IRQ_WAKE_THREAD;
  1126. if (status & regs->isr_ovr.mask) {
  1127. /*
  1128. * Overrun occurred on regular conversions: data for wrong
  1129. * channel may be read. Unconditionally disable interrupts
  1130. * to stop processing data and print error message.
  1131. * Restarting the capture can be done by disabling, then
  1132. * re-enabling it (e.g. write 0, then 1 to buffer/enable).
  1133. */
  1134. stm32_adc_ovr_irq_disable(adc);
  1135. stm32_adc_conv_irq_disable(adc);
  1136. return IRQ_WAKE_THREAD;
  1137. }
  1138. if (status & regs->isr_eoc.mask) {
  1139. /* Reading DR also clears EOC status flag */
  1140. adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
  1141. if (iio_buffer_enabled(indio_dev)) {
  1142. adc->bufi++;
  1143. if (adc->bufi >= adc->num_conv) {
  1144. stm32_adc_conv_irq_disable(adc);
  1145. iio_trigger_poll(indio_dev->trig);
  1146. }
  1147. } else {
  1148. complete(&adc->completion);
  1149. }
  1150. return IRQ_HANDLED;
  1151. }
  1152. return IRQ_NONE;
  1153. }
  1154. /**
  1155. * stm32_adc_validate_trigger() - validate trigger for stm32 adc
  1156. * @indio_dev: IIO device
  1157. * @trig: new trigger
  1158. *
  1159. * Returns: 0 if trig matches one of the triggers registered by stm32 adc
  1160. * driver, -EINVAL otherwise.
  1161. */
  1162. static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
  1163. struct iio_trigger *trig)
  1164. {
  1165. return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
  1166. }
  1167. static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
  1168. {
  1169. struct stm32_adc *adc = iio_priv(indio_dev);
  1170. unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
  1171. unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE;
  1172. /*
  1173. * dma cyclic transfers are used, buffer is split into two periods.
  1174. * There should be :
  1175. * - always one buffer (period) dma is working on
  1176. * - one buffer (period) driver can push with iio_trigger_poll().
  1177. */
  1178. watermark = min(watermark, val * (unsigned)(sizeof(u16)));
  1179. adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
  1180. return 0;
  1181. }
  1182. static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
  1183. const unsigned long *scan_mask)
  1184. {
  1185. struct stm32_adc *adc = iio_priv(indio_dev);
  1186. struct device *dev = indio_dev->dev.parent;
  1187. int ret;
  1188. ret = pm_runtime_get_sync(dev);
  1189. if (ret < 0) {
  1190. pm_runtime_put_noidle(dev);
  1191. return ret;
  1192. }
  1193. adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
  1194. ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
  1195. pm_runtime_mark_last_busy(dev);
  1196. pm_runtime_put_autosuspend(dev);
  1197. return ret;
  1198. }
  1199. static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
  1200. const struct of_phandle_args *iiospec)
  1201. {
  1202. int i;
  1203. for (i = 0; i < indio_dev->num_channels; i++)
  1204. if (indio_dev->channels[i].channel == iiospec->args[0])
  1205. return i;
  1206. return -EINVAL;
  1207. }
  1208. /**
  1209. * stm32_adc_debugfs_reg_access - read or write register value
  1210. * @indio_dev: IIO device structure
  1211. * @reg: register offset
  1212. * @writeval: value to write
  1213. * @readval: value to read
  1214. *
  1215. * To read a value from an ADC register:
  1216. * echo [ADC reg offset] > direct_reg_access
  1217. * cat direct_reg_access
  1218. *
  1219. * To write a value in a ADC register:
  1220. * echo [ADC_reg_offset] [value] > direct_reg_access
  1221. */
  1222. static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
  1223. unsigned reg, unsigned writeval,
  1224. unsigned *readval)
  1225. {
  1226. struct stm32_adc *adc = iio_priv(indio_dev);
  1227. struct device *dev = indio_dev->dev.parent;
  1228. int ret;
  1229. ret = pm_runtime_get_sync(dev);
  1230. if (ret < 0) {
  1231. pm_runtime_put_noidle(dev);
  1232. return ret;
  1233. }
  1234. if (!readval)
  1235. stm32_adc_writel(adc, reg, writeval);
  1236. else
  1237. *readval = stm32_adc_readl(adc, reg);
  1238. pm_runtime_mark_last_busy(dev);
  1239. pm_runtime_put_autosuspend(dev);
  1240. return 0;
  1241. }
  1242. static const struct iio_info stm32_adc_iio_info = {
  1243. .read_raw = stm32_adc_read_raw,
  1244. .validate_trigger = stm32_adc_validate_trigger,
  1245. .hwfifo_set_watermark = stm32_adc_set_watermark,
  1246. .update_scan_mode = stm32_adc_update_scan_mode,
  1247. .debugfs_reg_access = stm32_adc_debugfs_reg_access,
  1248. .of_xlate = stm32_adc_of_xlate,
  1249. };
  1250. static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
  1251. {
  1252. struct dma_tx_state state;
  1253. enum dma_status status;
  1254. status = dmaengine_tx_status(adc->dma_chan,
  1255. adc->dma_chan->cookie,
  1256. &state);
  1257. if (status == DMA_IN_PROGRESS) {
  1258. /* Residue is size in bytes from end of buffer */
  1259. unsigned int i = adc->rx_buf_sz - state.residue;
  1260. unsigned int size;
  1261. /* Return available bytes */
  1262. if (i >= adc->bufi)
  1263. size = i - adc->bufi;
  1264. else
  1265. size = adc->rx_buf_sz + i - adc->bufi;
  1266. return size;
  1267. }
  1268. return 0;
  1269. }
  1270. static void stm32_adc_dma_buffer_done(void *data)
  1271. {
  1272. struct iio_dev *indio_dev = data;
  1273. struct stm32_adc *adc = iio_priv(indio_dev);
  1274. int residue = stm32_adc_dma_residue(adc);
  1275. /*
  1276. * In DMA mode the trigger services of IIO are not used
  1277. * (e.g. no call to iio_trigger_poll).
  1278. * Calling irq handler associated to the hardware trigger is not
  1279. * relevant as the conversions have already been done. Data
  1280. * transfers are performed directly in DMA callback instead.
  1281. * This implementation avoids to call trigger irq handler that
  1282. * may sleep, in an atomic context (DMA irq handler context).
  1283. */
  1284. dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
  1285. while (residue >= indio_dev->scan_bytes) {
  1286. u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
  1287. iio_push_to_buffers(indio_dev, buffer);
  1288. residue -= indio_dev->scan_bytes;
  1289. adc->bufi += indio_dev->scan_bytes;
  1290. if (adc->bufi >= adc->rx_buf_sz)
  1291. adc->bufi = 0;
  1292. }
  1293. }
  1294. static int stm32_adc_dma_start(struct iio_dev *indio_dev)
  1295. {
  1296. struct stm32_adc *adc = iio_priv(indio_dev);
  1297. struct dma_async_tx_descriptor *desc;
  1298. dma_cookie_t cookie;
  1299. int ret;
  1300. if (!adc->dma_chan)
  1301. return 0;
  1302. dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
  1303. adc->rx_buf_sz, adc->rx_buf_sz / 2);
  1304. /* Prepare a DMA cyclic transaction */
  1305. desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
  1306. adc->rx_dma_buf,
  1307. adc->rx_buf_sz, adc->rx_buf_sz / 2,
  1308. DMA_DEV_TO_MEM,
  1309. DMA_PREP_INTERRUPT);
  1310. if (!desc)
  1311. return -EBUSY;
  1312. desc->callback = stm32_adc_dma_buffer_done;
  1313. desc->callback_param = indio_dev;
  1314. cookie = dmaengine_submit(desc);
  1315. ret = dma_submit_error(cookie);
  1316. if (ret) {
  1317. dmaengine_terminate_sync(adc->dma_chan);
  1318. return ret;
  1319. }
  1320. /* Issue pending DMA requests */
  1321. dma_async_issue_pending(adc->dma_chan);
  1322. return 0;
  1323. }
  1324. static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
  1325. {
  1326. struct stm32_adc *adc = iio_priv(indio_dev);
  1327. struct device *dev = indio_dev->dev.parent;
  1328. int ret;
  1329. ret = pm_runtime_get_sync(dev);
  1330. if (ret < 0) {
  1331. pm_runtime_put_noidle(dev);
  1332. return ret;
  1333. }
  1334. ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
  1335. if (ret) {
  1336. dev_err(&indio_dev->dev, "Can't set trigger\n");
  1337. goto err_pm_put;
  1338. }
  1339. ret = stm32_adc_dma_start(indio_dev);
  1340. if (ret) {
  1341. dev_err(&indio_dev->dev, "Can't start dma\n");
  1342. goto err_clr_trig;
  1343. }
  1344. /* Reset adc buffer index */
  1345. adc->bufi = 0;
  1346. stm32_adc_ovr_irq_enable(adc);
  1347. if (!adc->dma_chan)
  1348. stm32_adc_conv_irq_enable(adc);
  1349. adc->cfg->start_conv(indio_dev, !!adc->dma_chan);
  1350. return 0;
  1351. err_clr_trig:
  1352. stm32_adc_set_trig(indio_dev, NULL);
  1353. err_pm_put:
  1354. pm_runtime_mark_last_busy(dev);
  1355. pm_runtime_put_autosuspend(dev);
  1356. return ret;
  1357. }
  1358. static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
  1359. {
  1360. struct stm32_adc *adc = iio_priv(indio_dev);
  1361. struct device *dev = indio_dev->dev.parent;
  1362. adc->cfg->stop_conv(indio_dev);
  1363. if (!adc->dma_chan)
  1364. stm32_adc_conv_irq_disable(adc);
  1365. stm32_adc_ovr_irq_disable(adc);
  1366. if (adc->dma_chan)
  1367. dmaengine_terminate_sync(adc->dma_chan);
  1368. if (stm32_adc_set_trig(indio_dev, NULL))
  1369. dev_err(&indio_dev->dev, "Can't clear trigger\n");
  1370. pm_runtime_mark_last_busy(dev);
  1371. pm_runtime_put_autosuspend(dev);
  1372. return 0;
  1373. }
  1374. static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
  1375. .postenable = &stm32_adc_buffer_postenable,
  1376. .predisable = &stm32_adc_buffer_predisable,
  1377. };
  1378. static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
  1379. {
  1380. struct iio_poll_func *pf = p;
  1381. struct iio_dev *indio_dev = pf->indio_dev;
  1382. struct stm32_adc *adc = iio_priv(indio_dev);
  1383. dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
  1384. if (!adc->dma_chan) {
  1385. /* reset buffer index */
  1386. adc->bufi = 0;
  1387. iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
  1388. pf->timestamp);
  1389. } else {
  1390. int residue = stm32_adc_dma_residue(adc);
  1391. while (residue >= indio_dev->scan_bytes) {
  1392. u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
  1393. iio_push_to_buffers_with_timestamp(indio_dev, buffer,
  1394. pf->timestamp);
  1395. residue -= indio_dev->scan_bytes;
  1396. adc->bufi += indio_dev->scan_bytes;
  1397. if (adc->bufi >= adc->rx_buf_sz)
  1398. adc->bufi = 0;
  1399. }
  1400. }
  1401. iio_trigger_notify_done(indio_dev->trig);
  1402. /* re-enable eoc irq */
  1403. if (!adc->dma_chan)
  1404. stm32_adc_conv_irq_enable(adc);
  1405. return IRQ_HANDLED;
  1406. }
  1407. static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
  1408. IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
  1409. {
  1410. .name = "trigger_polarity_available",
  1411. .shared = IIO_SHARED_BY_ALL,
  1412. .read = iio_enum_available_read,
  1413. .private = (uintptr_t)&stm32_adc_trig_pol,
  1414. },
  1415. {},
  1416. };
  1417. static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
  1418. {
  1419. struct device_node *node = indio_dev->dev.of_node;
  1420. struct stm32_adc *adc = iio_priv(indio_dev);
  1421. unsigned int i;
  1422. u32 res;
  1423. if (of_property_read_u32(node, "assigned-resolution-bits", &res))
  1424. res = adc->cfg->adc_info->resolutions[0];
  1425. for (i = 0; i < adc->cfg->adc_info->num_res; i++)
  1426. if (res == adc->cfg->adc_info->resolutions[i])
  1427. break;
  1428. if (i >= adc->cfg->adc_info->num_res) {
  1429. dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
  1430. return -EINVAL;
  1431. }
  1432. dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
  1433. adc->res = i;
  1434. return 0;
  1435. }
  1436. static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
  1437. {
  1438. const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
  1439. u32 period_ns, shift = smpr->shift, mask = smpr->mask;
  1440. unsigned int smp, r = smpr->reg;
  1441. /* Determine sampling time (ADC clock cycles) */
  1442. period_ns = NSEC_PER_SEC / adc->common->rate;
  1443. for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++)
  1444. if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
  1445. break;
  1446. if (smp > STM32_ADC_MAX_SMP)
  1447. smp = STM32_ADC_MAX_SMP;
  1448. /* pre-build sampling time registers (e.g. smpr1, smpr2) */
  1449. adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
  1450. }
  1451. static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
  1452. struct iio_chan_spec *chan, u32 vinp,
  1453. u32 vinn, int scan_index, bool differential)
  1454. {
  1455. struct stm32_adc *adc = iio_priv(indio_dev);
  1456. char *name = adc->chan_name[vinp];
  1457. chan->type = IIO_VOLTAGE;
  1458. chan->channel = vinp;
  1459. if (differential) {
  1460. chan->differential = 1;
  1461. chan->channel2 = vinn;
  1462. snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn);
  1463. } else {
  1464. snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp);
  1465. }
  1466. chan->datasheet_name = name;
  1467. chan->scan_index = scan_index;
  1468. chan->indexed = 1;
  1469. chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
  1470. chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
  1471. BIT(IIO_CHAN_INFO_OFFSET);
  1472. chan->scan_type.sign = 'u';
  1473. chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
  1474. chan->scan_type.storagebits = 16;
  1475. chan->ext_info = stm32_adc_ext_info;
  1476. /* pre-build selected channels mask */
  1477. adc->pcsel |= BIT(chan->channel);
  1478. if (differential) {
  1479. /* pre-build diff channels mask */
  1480. adc->difsel |= BIT(chan->channel);
  1481. /* Also add negative input to pre-selected channels */
  1482. adc->pcsel |= BIT(chan->channel2);
  1483. }
  1484. }
  1485. static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
  1486. {
  1487. struct device_node *node = indio_dev->dev.of_node;
  1488. struct stm32_adc *adc = iio_priv(indio_dev);
  1489. const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
  1490. struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX];
  1491. struct property *prop;
  1492. const __be32 *cur;
  1493. struct iio_chan_spec *channels;
  1494. int scan_index = 0, num_channels = 0, num_diff = 0, ret, i;
  1495. u32 val, smp = 0;
  1496. ret = of_property_count_u32_elems(node, "st,adc-channels");
  1497. if (ret > adc_info->max_channels) {
  1498. dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
  1499. return -EINVAL;
  1500. } else if (ret > 0) {
  1501. num_channels += ret;
  1502. }
  1503. ret = of_property_count_elems_of_size(node, "st,adc-diff-channels",
  1504. sizeof(*diff));
  1505. if (ret > adc_info->max_channels) {
  1506. dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
  1507. return -EINVAL;
  1508. } else if (ret > 0) {
  1509. int size = ret * sizeof(*diff) / sizeof(u32);
  1510. num_diff = ret;
  1511. num_channels += ret;
  1512. ret = of_property_read_u32_array(node, "st,adc-diff-channels",
  1513. (u32 *)diff, size);
  1514. if (ret)
  1515. return ret;
  1516. }
  1517. if (!num_channels) {
  1518. dev_err(&indio_dev->dev, "No channels configured\n");
  1519. return -ENODATA;
  1520. }
  1521. /* Optional sample time is provided either for each, or all channels */
  1522. ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
  1523. if (ret > 1 && ret != num_channels) {
  1524. dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
  1525. return -EINVAL;
  1526. }
  1527. channels = devm_kcalloc(&indio_dev->dev, num_channels,
  1528. sizeof(struct iio_chan_spec), GFP_KERNEL);
  1529. if (!channels)
  1530. return -ENOMEM;
  1531. of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
  1532. if (val >= adc_info->max_channels) {
  1533. dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
  1534. return -EINVAL;
  1535. }
  1536. /* Channel can't be configured both as single-ended & diff */
  1537. for (i = 0; i < num_diff; i++) {
  1538. if (val == diff[i].vinp) {
  1539. dev_err(&indio_dev->dev,
  1540. "channel %d miss-configured\n", val);
  1541. return -EINVAL;
  1542. }
  1543. }
  1544. stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
  1545. 0, scan_index, false);
  1546. scan_index++;
  1547. }
  1548. for (i = 0; i < num_diff; i++) {
  1549. if (diff[i].vinp >= adc_info->max_channels ||
  1550. diff[i].vinn >= adc_info->max_channels) {
  1551. dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",
  1552. diff[i].vinp, diff[i].vinn);
  1553. return -EINVAL;
  1554. }
  1555. stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
  1556. diff[i].vinp, diff[i].vinn, scan_index,
  1557. true);
  1558. scan_index++;
  1559. }
  1560. for (i = 0; i < scan_index; i++) {
  1561. /*
  1562. * Using of_property_read_u32_index(), smp value will only be
  1563. * modified if valid u32 value can be decoded. This allows to
  1564. * get either no value, 1 shared value for all indexes, or one
  1565. * value per channel.
  1566. */
  1567. of_property_read_u32_index(node, "st,min-sample-time-nsecs",
  1568. i, &smp);
  1569. /* Prepare sampling time settings */
  1570. stm32_adc_smpr_init(adc, channels[i].channel, smp);
  1571. }
  1572. indio_dev->num_channels = scan_index;
  1573. indio_dev->channels = channels;
  1574. return 0;
  1575. }
  1576. static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev)
  1577. {
  1578. struct stm32_adc *adc = iio_priv(indio_dev);
  1579. struct dma_slave_config config;
  1580. int ret;
  1581. adc->dma_chan = dma_request_chan(dev, "rx");
  1582. if (IS_ERR(adc->dma_chan)) {
  1583. ret = PTR_ERR(adc->dma_chan);
  1584. if (ret != -ENODEV)
  1585. return dev_err_probe(dev, ret,
  1586. "DMA channel request failed with\n");
  1587. /* DMA is optional: fall back to IRQ mode */
  1588. adc->dma_chan = NULL;
  1589. return 0;
  1590. }
  1591. adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
  1592. STM32_DMA_BUFFER_SIZE,
  1593. &adc->rx_dma_buf, GFP_KERNEL);
  1594. if (!adc->rx_buf) {
  1595. ret = -ENOMEM;
  1596. goto err_release;
  1597. }
  1598. /* Configure DMA channel to read data register */
  1599. memset(&config, 0, sizeof(config));
  1600. config.src_addr = (dma_addr_t)adc->common->phys_base;
  1601. config.src_addr += adc->offset + adc->cfg->regs->dr;
  1602. config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  1603. ret = dmaengine_slave_config(adc->dma_chan, &config);
  1604. if (ret)
  1605. goto err_free;
  1606. return 0;
  1607. err_free:
  1608. dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
  1609. adc->rx_buf, adc->rx_dma_buf);
  1610. err_release:
  1611. dma_release_channel(adc->dma_chan);
  1612. return ret;
  1613. }
  1614. static int stm32_adc_probe(struct platform_device *pdev)
  1615. {
  1616. struct iio_dev *indio_dev;
  1617. struct device *dev = &pdev->dev;
  1618. irqreturn_t (*handler)(int irq, void *p) = NULL;
  1619. struct stm32_adc *adc;
  1620. int ret;
  1621. if (!pdev->dev.of_node)
  1622. return -ENODEV;
  1623. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
  1624. if (!indio_dev)
  1625. return -ENOMEM;
  1626. adc = iio_priv(indio_dev);
  1627. adc->common = dev_get_drvdata(pdev->dev.parent);
  1628. spin_lock_init(&adc->lock);
  1629. init_completion(&adc->completion);
  1630. adc->cfg = (const struct stm32_adc_cfg *)
  1631. of_match_device(dev->driver->of_match_table, dev)->data;
  1632. indio_dev->name = dev_name(&pdev->dev);
  1633. indio_dev->dev.of_node = pdev->dev.of_node;
  1634. indio_dev->info = &stm32_adc_iio_info;
  1635. indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
  1636. platform_set_drvdata(pdev, indio_dev);
  1637. ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
  1638. if (ret != 0) {
  1639. dev_err(&pdev->dev, "missing reg property\n");
  1640. return -EINVAL;
  1641. }
  1642. adc->irq = platform_get_irq(pdev, 0);
  1643. if (adc->irq < 0)
  1644. return adc->irq;
  1645. ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr,
  1646. stm32_adc_threaded_isr,
  1647. 0, pdev->name, indio_dev);
  1648. if (ret) {
  1649. dev_err(&pdev->dev, "failed to request IRQ\n");
  1650. return ret;
  1651. }
  1652. adc->clk = devm_clk_get(&pdev->dev, NULL);
  1653. if (IS_ERR(adc->clk)) {
  1654. ret = PTR_ERR(adc->clk);
  1655. if (ret == -ENOENT && !adc->cfg->clk_required) {
  1656. adc->clk = NULL;
  1657. } else {
  1658. dev_err(&pdev->dev, "Can't get clock\n");
  1659. return ret;
  1660. }
  1661. }
  1662. ret = stm32_adc_of_get_resolution(indio_dev);
  1663. if (ret < 0)
  1664. return ret;
  1665. ret = stm32_adc_chan_of_init(indio_dev);
  1666. if (ret < 0)
  1667. return ret;
  1668. ret = stm32_adc_dma_request(dev, indio_dev);
  1669. if (ret < 0)
  1670. return ret;
  1671. if (!adc->dma_chan)
  1672. handler = &stm32_adc_trigger_handler;
  1673. ret = iio_triggered_buffer_setup(indio_dev,
  1674. &iio_pollfunc_store_time, handler,
  1675. &stm32_adc_buffer_setup_ops);
  1676. if (ret) {
  1677. dev_err(&pdev->dev, "buffer setup failed\n");
  1678. goto err_dma_disable;
  1679. }
  1680. /* Get stm32-adc-core PM online */
  1681. pm_runtime_get_noresume(dev);
  1682. pm_runtime_set_active(dev);
  1683. pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS);
  1684. pm_runtime_use_autosuspend(dev);
  1685. pm_runtime_enable(dev);
  1686. ret = stm32_adc_hw_start(dev);
  1687. if (ret)
  1688. goto err_buffer_cleanup;
  1689. ret = iio_device_register(indio_dev);
  1690. if (ret) {
  1691. dev_err(&pdev->dev, "iio dev register failed\n");
  1692. goto err_hw_stop;
  1693. }
  1694. pm_runtime_mark_last_busy(dev);
  1695. pm_runtime_put_autosuspend(dev);
  1696. return 0;
  1697. err_hw_stop:
  1698. stm32_adc_hw_stop(dev);
  1699. err_buffer_cleanup:
  1700. pm_runtime_disable(dev);
  1701. pm_runtime_set_suspended(dev);
  1702. pm_runtime_put_noidle(dev);
  1703. iio_triggered_buffer_cleanup(indio_dev);
  1704. err_dma_disable:
  1705. if (adc->dma_chan) {
  1706. dma_free_coherent(adc->dma_chan->device->dev,
  1707. STM32_DMA_BUFFER_SIZE,
  1708. adc->rx_buf, adc->rx_dma_buf);
  1709. dma_release_channel(adc->dma_chan);
  1710. }
  1711. return ret;
  1712. }
  1713. static int stm32_adc_remove(struct platform_device *pdev)
  1714. {
  1715. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  1716. struct stm32_adc *adc = iio_priv(indio_dev);
  1717. pm_runtime_get_sync(&pdev->dev);
  1718. iio_device_unregister(indio_dev);
  1719. stm32_adc_hw_stop(&pdev->dev);
  1720. pm_runtime_disable(&pdev->dev);
  1721. pm_runtime_set_suspended(&pdev->dev);
  1722. pm_runtime_put_noidle(&pdev->dev);
  1723. iio_triggered_buffer_cleanup(indio_dev);
  1724. if (adc->dma_chan) {
  1725. dma_free_coherent(adc->dma_chan->device->dev,
  1726. STM32_DMA_BUFFER_SIZE,
  1727. adc->rx_buf, adc->rx_dma_buf);
  1728. dma_release_channel(adc->dma_chan);
  1729. }
  1730. return 0;
  1731. }
  1732. #if defined(CONFIG_PM_SLEEP)
  1733. static int stm32_adc_suspend(struct device *dev)
  1734. {
  1735. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1736. if (iio_buffer_enabled(indio_dev))
  1737. stm32_adc_buffer_predisable(indio_dev);
  1738. return pm_runtime_force_suspend(dev);
  1739. }
  1740. static int stm32_adc_resume(struct device *dev)
  1741. {
  1742. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1743. int ret;
  1744. ret = pm_runtime_force_resume(dev);
  1745. if (ret < 0)
  1746. return ret;
  1747. if (!iio_buffer_enabled(indio_dev))
  1748. return 0;
  1749. ret = stm32_adc_update_scan_mode(indio_dev,
  1750. indio_dev->active_scan_mask);
  1751. if (ret < 0)
  1752. return ret;
  1753. return stm32_adc_buffer_postenable(indio_dev);
  1754. }
  1755. #endif
  1756. #if defined(CONFIG_PM)
  1757. static int stm32_adc_runtime_suspend(struct device *dev)
  1758. {
  1759. return stm32_adc_hw_stop(dev);
  1760. }
  1761. static int stm32_adc_runtime_resume(struct device *dev)
  1762. {
  1763. return stm32_adc_hw_start(dev);
  1764. }
  1765. #endif
  1766. static const struct dev_pm_ops stm32_adc_pm_ops = {
  1767. SET_SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume)
  1768. SET_RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume,
  1769. NULL)
  1770. };
  1771. static const struct stm32_adc_cfg stm32f4_adc_cfg = {
  1772. .regs = &stm32f4_adc_regspec,
  1773. .adc_info = &stm32f4_adc_info,
  1774. .trigs = stm32f4_adc_trigs,
  1775. .clk_required = true,
  1776. .start_conv = stm32f4_adc_start_conv,
  1777. .stop_conv = stm32f4_adc_stop_conv,
  1778. .smp_cycles = stm32f4_adc_smp_cycles,
  1779. .irq_clear = stm32f4_adc_irq_clear,
  1780. };
  1781. static const struct stm32_adc_cfg stm32h7_adc_cfg = {
  1782. .regs = &stm32h7_adc_regspec,
  1783. .adc_info = &stm32h7_adc_info,
  1784. .trigs = stm32h7_adc_trigs,
  1785. .start_conv = stm32h7_adc_start_conv,
  1786. .stop_conv = stm32h7_adc_stop_conv,
  1787. .prepare = stm32h7_adc_prepare,
  1788. .unprepare = stm32h7_adc_unprepare,
  1789. .smp_cycles = stm32h7_adc_smp_cycles,
  1790. .irq_clear = stm32h7_adc_irq_clear,
  1791. };
  1792. static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
  1793. .regs = &stm32h7_adc_regspec,
  1794. .adc_info = &stm32h7_adc_info,
  1795. .trigs = stm32h7_adc_trigs,
  1796. .has_vregready = true,
  1797. .start_conv = stm32h7_adc_start_conv,
  1798. .stop_conv = stm32h7_adc_stop_conv,
  1799. .prepare = stm32h7_adc_prepare,
  1800. .unprepare = stm32h7_adc_unprepare,
  1801. .smp_cycles = stm32h7_adc_smp_cycles,
  1802. .irq_clear = stm32h7_adc_irq_clear,
  1803. };
  1804. static const struct of_device_id stm32_adc_of_match[] = {
  1805. { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
  1806. { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
  1807. { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
  1808. {},
  1809. };
  1810. MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
  1811. static struct platform_driver stm32_adc_driver = {
  1812. .probe = stm32_adc_probe,
  1813. .remove = stm32_adc_remove,
  1814. .driver = {
  1815. .name = "stm32-adc",
  1816. .of_match_table = stm32_adc_of_match,
  1817. .pm = &stm32_adc_pm_ops,
  1818. },
  1819. };
  1820. module_platform_driver(stm32_adc_driver);
  1821. MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
  1822. MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
  1823. MODULE_LICENSE("GPL v2");
  1824. MODULE_ALIAS("platform:stm32-adc");