stm32-adc-core.h 5.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * This file is part of STM32 ADC driver
  4. *
  5. * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  6. * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
  7. *
  8. */
  9. #ifndef __STM32_ADC_H
  10. #define __STM32_ADC_H
  11. /*
  12. * STM32 - ADC global register map
  13. * ________________________________________________________
  14. * | Offset | Register |
  15. * --------------------------------------------------------
  16. * | 0x000 | Master ADC1 |
  17. * --------------------------------------------------------
  18. * | 0x100 | Slave ADC2 |
  19. * --------------------------------------------------------
  20. * | 0x200 | Slave ADC3 |
  21. * --------------------------------------------------------
  22. * | 0x300 | Master & Slave common regs |
  23. * --------------------------------------------------------
  24. */
  25. #define STM32_ADC_MAX_ADCS 3
  26. #define STM32_ADC_OFFSET 0x100
  27. #define STM32_ADCX_COMN_OFFSET 0x300
  28. /* STM32F4 - Registers for each ADC instance */
  29. #define STM32F4_ADC_SR 0x00
  30. #define STM32F4_ADC_CR1 0x04
  31. #define STM32F4_ADC_CR2 0x08
  32. #define STM32F4_ADC_SMPR1 0x0C
  33. #define STM32F4_ADC_SMPR2 0x10
  34. #define STM32F4_ADC_HTR 0x24
  35. #define STM32F4_ADC_LTR 0x28
  36. #define STM32F4_ADC_SQR1 0x2C
  37. #define STM32F4_ADC_SQR2 0x30
  38. #define STM32F4_ADC_SQR3 0x34
  39. #define STM32F4_ADC_JSQR 0x38
  40. #define STM32F4_ADC_JDR1 0x3C
  41. #define STM32F4_ADC_JDR2 0x40
  42. #define STM32F4_ADC_JDR3 0x44
  43. #define STM32F4_ADC_JDR4 0x48
  44. #define STM32F4_ADC_DR 0x4C
  45. /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
  46. #define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
  47. #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
  48. /* STM32F4_ADC_SR - bit fields */
  49. #define STM32F4_OVR BIT(5)
  50. #define STM32F4_STRT BIT(4)
  51. #define STM32F4_EOC BIT(1)
  52. /* STM32F4_ADC_CR1 - bit fields */
  53. #define STM32F4_OVRIE BIT(26)
  54. #define STM32F4_RES_SHIFT 24
  55. #define STM32F4_RES_MASK GENMASK(25, 24)
  56. #define STM32F4_SCAN BIT(8)
  57. #define STM32F4_EOCIE BIT(5)
  58. /* STM32F4_ADC_CR2 - bit fields */
  59. #define STM32F4_SWSTART BIT(30)
  60. #define STM32F4_EXTEN_SHIFT 28
  61. #define STM32F4_EXTEN_MASK GENMASK(29, 28)
  62. #define STM32F4_EXTSEL_SHIFT 24
  63. #define STM32F4_EXTSEL_MASK GENMASK(27, 24)
  64. #define STM32F4_EOCS BIT(10)
  65. #define STM32F4_DDS BIT(9)
  66. #define STM32F4_DMA BIT(8)
  67. #define STM32F4_ADON BIT(0)
  68. /* STM32F4_ADC_CSR - bit fields */
  69. #define STM32F4_OVR3 BIT(21)
  70. #define STM32F4_EOC3 BIT(17)
  71. #define STM32F4_OVR2 BIT(13)
  72. #define STM32F4_EOC2 BIT(9)
  73. #define STM32F4_OVR1 BIT(5)
  74. #define STM32F4_EOC1 BIT(1)
  75. /* STM32F4_ADC_CCR - bit fields */
  76. #define STM32F4_ADC_ADCPRE_SHIFT 16
  77. #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
  78. /* STM32H7 - Registers for each ADC instance */
  79. #define STM32H7_ADC_ISR 0x00
  80. #define STM32H7_ADC_IER 0x04
  81. #define STM32H7_ADC_CR 0x08
  82. #define STM32H7_ADC_CFGR 0x0C
  83. #define STM32H7_ADC_SMPR1 0x14
  84. #define STM32H7_ADC_SMPR2 0x18
  85. #define STM32H7_ADC_PCSEL 0x1C
  86. #define STM32H7_ADC_SQR1 0x30
  87. #define STM32H7_ADC_SQR2 0x34
  88. #define STM32H7_ADC_SQR3 0x38
  89. #define STM32H7_ADC_SQR4 0x3C
  90. #define STM32H7_ADC_DR 0x40
  91. #define STM32H7_ADC_DIFSEL 0xC0
  92. #define STM32H7_ADC_CALFACT 0xC4
  93. #define STM32H7_ADC_CALFACT2 0xC8
  94. /* STM32H7 - common registers for all ADC instances */
  95. #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
  96. #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
  97. /* STM32H7_ADC_ISR - bit fields */
  98. #define STM32MP1_VREGREADY BIT(12)
  99. #define STM32H7_OVR BIT(4)
  100. #define STM32H7_EOC BIT(2)
  101. #define STM32H7_ADRDY BIT(0)
  102. /* STM32H7_ADC_IER - bit fields */
  103. #define STM32H7_OVRIE STM32H7_OVR
  104. #define STM32H7_EOCIE STM32H7_EOC
  105. /* STM32H7_ADC_CR - bit fields */
  106. #define STM32H7_ADCAL BIT(31)
  107. #define STM32H7_ADCALDIF BIT(30)
  108. #define STM32H7_DEEPPWD BIT(29)
  109. #define STM32H7_ADVREGEN BIT(28)
  110. #define STM32H7_LINCALRDYW6 BIT(27)
  111. #define STM32H7_LINCALRDYW5 BIT(26)
  112. #define STM32H7_LINCALRDYW4 BIT(25)
  113. #define STM32H7_LINCALRDYW3 BIT(24)
  114. #define STM32H7_LINCALRDYW2 BIT(23)
  115. #define STM32H7_LINCALRDYW1 BIT(22)
  116. #define STM32H7_ADCALLIN BIT(16)
  117. #define STM32H7_BOOST BIT(8)
  118. #define STM32H7_ADSTP BIT(4)
  119. #define STM32H7_ADSTART BIT(2)
  120. #define STM32H7_ADDIS BIT(1)
  121. #define STM32H7_ADEN BIT(0)
  122. /* STM32H7_ADC_CFGR bit fields */
  123. #define STM32H7_EXTEN_SHIFT 10
  124. #define STM32H7_EXTEN_MASK GENMASK(11, 10)
  125. #define STM32H7_EXTSEL_SHIFT 5
  126. #define STM32H7_EXTSEL_MASK GENMASK(9, 5)
  127. #define STM32H7_RES_SHIFT 2
  128. #define STM32H7_RES_MASK GENMASK(4, 2)
  129. #define STM32H7_DMNGT_SHIFT 0
  130. #define STM32H7_DMNGT_MASK GENMASK(1, 0)
  131. enum stm32h7_adc_dmngt {
  132. STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
  133. STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
  134. STM32H7_DMNGT_DFSDM, /* DFSDM mode */
  135. STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
  136. };
  137. /* STM32H7_ADC_CALFACT - bit fields */
  138. #define STM32H7_CALFACT_D_SHIFT 16
  139. #define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
  140. #define STM32H7_CALFACT_S_SHIFT 0
  141. #define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
  142. /* STM32H7_ADC_CALFACT2 - bit fields */
  143. #define STM32H7_LINCALFACT_SHIFT 0
  144. #define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
  145. /* STM32H7_ADC_CSR - bit fields */
  146. #define STM32H7_OVR_SLV BIT(20)
  147. #define STM32H7_EOC_SLV BIT(18)
  148. #define STM32H7_OVR_MST BIT(4)
  149. #define STM32H7_EOC_MST BIT(2)
  150. /* STM32H7_ADC_CCR - bit fields */
  151. #define STM32H7_PRESC_SHIFT 18
  152. #define STM32H7_PRESC_MASK GENMASK(21, 18)
  153. #define STM32H7_CKMODE_SHIFT 16
  154. #define STM32H7_CKMODE_MASK GENMASK(17, 16)
  155. /**
  156. * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
  157. * @base: control registers base cpu addr
  158. * @phys_base: control registers base physical addr
  159. * @rate: clock rate used for analog circuitry
  160. * @vref_mv: vref voltage (mv)
  161. */
  162. struct stm32_adc_common {
  163. void __iomem *base;
  164. phys_addr_t phys_base;
  165. unsigned long rate;
  166. int vref_mv;
  167. };
  168. #endif