stm32-adc-core.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This file is part of STM32 ADC driver
  4. *
  5. * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  6. * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
  7. *
  8. * Inspired from: fsl-imx25-tsadc
  9. *
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irqchip/chained_irq.h>
  14. #include <linux/irqdesc.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <linux/module.h>
  18. #include <linux/of_device.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include "stm32-adc-core.h"
  24. #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
  25. /* SYSCFG registers */
  26. #define STM32MP1_SYSCFG_PMCSETR 0x04
  27. #define STM32MP1_SYSCFG_PMCCLRR 0x44
  28. /* SYSCFG bit fields */
  29. #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
  30. /* SYSCFG capability flags */
  31. #define HAS_VBOOSTER BIT(0)
  32. #define HAS_ANASWVDD BIT(1)
  33. /**
  34. * struct stm32_adc_common_regs - stm32 common registers
  35. * @csr: common status register offset
  36. * @ccr: common control register offset
  37. * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
  38. * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
  39. * @ier: interrupt enable register offset for each adc
  40. * @eocie_msk: end of conversion interrupt enable mask in @ier
  41. */
  42. struct stm32_adc_common_regs {
  43. u32 csr;
  44. u32 ccr;
  45. u32 eoc_msk[STM32_ADC_MAX_ADCS];
  46. u32 ovr_msk[STM32_ADC_MAX_ADCS];
  47. u32 ier;
  48. u32 eocie_msk;
  49. };
  50. struct stm32_adc_priv;
  51. /**
  52. * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
  53. * @regs: common registers for all instances
  54. * @clk_sel: clock selection routine
  55. * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
  56. * @has_syscfg: SYSCFG capability flags
  57. * @num_irqs: number of interrupt lines
  58. */
  59. struct stm32_adc_priv_cfg {
  60. const struct stm32_adc_common_regs *regs;
  61. int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
  62. u32 max_clk_rate_hz;
  63. unsigned int has_syscfg;
  64. unsigned int num_irqs;
  65. };
  66. /**
  67. * struct stm32_adc_priv - stm32 ADC core private data
  68. * @irq: irq(s) for ADC block
  69. * @domain: irq domain reference
  70. * @aclk: clock reference for the analog circuitry
  71. * @bclk: bus clock common for all ADCs, depends on part used
  72. * @max_clk_rate: desired maximum clock rate
  73. * @booster: booster supply reference
  74. * @vdd: vdd supply reference
  75. * @vdda: vdda analog supply reference
  76. * @vref: regulator reference
  77. * @vdd_uv: vdd supply voltage (microvolts)
  78. * @vdda_uv: vdda supply voltage (microvolts)
  79. * @cfg: compatible configuration data
  80. * @common: common data for all ADC instances
  81. * @ccr_bak: backup CCR in low power mode
  82. * @syscfg: reference to syscon, system control registers
  83. */
  84. struct stm32_adc_priv {
  85. int irq[STM32_ADC_MAX_ADCS];
  86. struct irq_domain *domain;
  87. struct clk *aclk;
  88. struct clk *bclk;
  89. u32 max_clk_rate;
  90. struct regulator *booster;
  91. struct regulator *vdd;
  92. struct regulator *vdda;
  93. struct regulator *vref;
  94. int vdd_uv;
  95. int vdda_uv;
  96. const struct stm32_adc_priv_cfg *cfg;
  97. struct stm32_adc_common common;
  98. u32 ccr_bak;
  99. struct regmap *syscfg;
  100. };
  101. static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
  102. {
  103. return container_of(com, struct stm32_adc_priv, common);
  104. }
  105. /* STM32F4 ADC internal common clock prescaler division ratios */
  106. static int stm32f4_pclk_div[] = {2, 4, 6, 8};
  107. /**
  108. * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
  109. * @pdev: platform device
  110. * @priv: stm32 ADC core private data
  111. * Select clock prescaler used for analog conversions, before using ADC.
  112. */
  113. static int stm32f4_adc_clk_sel(struct platform_device *pdev,
  114. struct stm32_adc_priv *priv)
  115. {
  116. unsigned long rate;
  117. u32 val;
  118. int i;
  119. /* stm32f4 has one clk input for analog (mandatory), enforce it here */
  120. if (!priv->aclk) {
  121. dev_err(&pdev->dev, "No 'adc' clock found\n");
  122. return -ENOENT;
  123. }
  124. rate = clk_get_rate(priv->aclk);
  125. if (!rate) {
  126. dev_err(&pdev->dev, "Invalid clock rate: 0\n");
  127. return -EINVAL;
  128. }
  129. for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
  130. if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
  131. break;
  132. }
  133. if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
  134. dev_err(&pdev->dev, "adc clk selection failed\n");
  135. return -EINVAL;
  136. }
  137. priv->common.rate = rate / stm32f4_pclk_div[i];
  138. val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
  139. val &= ~STM32F4_ADC_ADCPRE_MASK;
  140. val |= i << STM32F4_ADC_ADCPRE_SHIFT;
  141. writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
  142. dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
  143. priv->common.rate / 1000);
  144. return 0;
  145. }
  146. /**
  147. * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
  148. * @ckmode: ADC clock mode, Async or sync with prescaler.
  149. * @presc: prescaler bitfield for async clock mode
  150. * @div: prescaler division ratio
  151. */
  152. struct stm32h7_adc_ck_spec {
  153. u32 ckmode;
  154. u32 presc;
  155. int div;
  156. };
  157. static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
  158. /* 00: CK_ADC[1..3]: Asynchronous clock modes */
  159. { 0, 0, 1 },
  160. { 0, 1, 2 },
  161. { 0, 2, 4 },
  162. { 0, 3, 6 },
  163. { 0, 4, 8 },
  164. { 0, 5, 10 },
  165. { 0, 6, 12 },
  166. { 0, 7, 16 },
  167. { 0, 8, 32 },
  168. { 0, 9, 64 },
  169. { 0, 10, 128 },
  170. { 0, 11, 256 },
  171. /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
  172. { 1, 0, 1 },
  173. { 2, 0, 2 },
  174. { 3, 0, 4 },
  175. };
  176. static int stm32h7_adc_clk_sel(struct platform_device *pdev,
  177. struct stm32_adc_priv *priv)
  178. {
  179. u32 ckmode, presc, val;
  180. unsigned long rate;
  181. int i, div;
  182. /* stm32h7 bus clock is common for all ADC instances (mandatory) */
  183. if (!priv->bclk) {
  184. dev_err(&pdev->dev, "No 'bus' clock found\n");
  185. return -ENOENT;
  186. }
  187. /*
  188. * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
  189. * So, choice is to have bus clock mandatory and adc clock optional.
  190. * If optional 'adc' clock has been found, then try to use it first.
  191. */
  192. if (priv->aclk) {
  193. /*
  194. * Asynchronous clock modes (e.g. ckmode == 0)
  195. * From spec: PLL output musn't exceed max rate
  196. */
  197. rate = clk_get_rate(priv->aclk);
  198. if (!rate) {
  199. dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
  200. return -EINVAL;
  201. }
  202. for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
  203. ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
  204. presc = stm32h7_adc_ckmodes_spec[i].presc;
  205. div = stm32h7_adc_ckmodes_spec[i].div;
  206. if (ckmode)
  207. continue;
  208. if ((rate / div) <= priv->max_clk_rate)
  209. goto out;
  210. }
  211. }
  212. /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
  213. rate = clk_get_rate(priv->bclk);
  214. if (!rate) {
  215. dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
  216. return -EINVAL;
  217. }
  218. for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
  219. ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
  220. presc = stm32h7_adc_ckmodes_spec[i].presc;
  221. div = stm32h7_adc_ckmodes_spec[i].div;
  222. if (!ckmode)
  223. continue;
  224. if ((rate / div) <= priv->max_clk_rate)
  225. goto out;
  226. }
  227. dev_err(&pdev->dev, "adc clk selection failed\n");
  228. return -EINVAL;
  229. out:
  230. /* rate used later by each ADC instance to control BOOST mode */
  231. priv->common.rate = rate / div;
  232. /* Set common clock mode and prescaler */
  233. val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
  234. val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
  235. val |= ckmode << STM32H7_CKMODE_SHIFT;
  236. val |= presc << STM32H7_PRESC_SHIFT;
  237. writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
  238. dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
  239. ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
  240. return 0;
  241. }
  242. /* STM32F4 common registers definitions */
  243. static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
  244. .csr = STM32F4_ADC_CSR,
  245. .ccr = STM32F4_ADC_CCR,
  246. .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
  247. .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
  248. .ier = STM32F4_ADC_CR1,
  249. .eocie_msk = STM32F4_EOCIE,
  250. };
  251. /* STM32H7 common registers definitions */
  252. static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
  253. .csr = STM32H7_ADC_CSR,
  254. .ccr = STM32H7_ADC_CCR,
  255. .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
  256. .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
  257. .ier = STM32H7_ADC_IER,
  258. .eocie_msk = STM32H7_EOCIE,
  259. };
  260. static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
  261. 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
  262. };
  263. static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
  264. unsigned int adc)
  265. {
  266. u32 ier, offset = stm32_adc_offset[adc];
  267. ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
  268. return ier & priv->cfg->regs->eocie_msk;
  269. }
  270. /* ADC common interrupt for all instances */
  271. static void stm32_adc_irq_handler(struct irq_desc *desc)
  272. {
  273. struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
  274. struct irq_chip *chip = irq_desc_get_chip(desc);
  275. int i;
  276. u32 status;
  277. chained_irq_enter(chip, desc);
  278. status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
  279. /*
  280. * End of conversion may be handled by using IRQ or DMA. There may be a
  281. * race here when two conversions complete at the same time on several
  282. * ADCs. EOC may be read 'set' for several ADCs, with:
  283. * - an ADC configured to use DMA (EOC triggers the DMA request, and
  284. * is then automatically cleared by DR read in hardware)
  285. * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
  286. * be called in this case)
  287. * So both EOC status bit in CSR and EOCIE control bit must be checked
  288. * before invoking the interrupt handler (e.g. call ISR only for
  289. * IRQ-enabled ADCs).
  290. */
  291. for (i = 0; i < priv->cfg->num_irqs; i++) {
  292. if ((status & priv->cfg->regs->eoc_msk[i] &&
  293. stm32_adc_eoc_enabled(priv, i)) ||
  294. (status & priv->cfg->regs->ovr_msk[i]))
  295. generic_handle_irq(irq_find_mapping(priv->domain, i));
  296. }
  297. chained_irq_exit(chip, desc);
  298. };
  299. static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
  300. irq_hw_number_t hwirq)
  301. {
  302. irq_set_chip_data(irq, d->host_data);
  303. irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
  304. return 0;
  305. }
  306. static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
  307. {
  308. irq_set_chip_and_handler(irq, NULL, NULL);
  309. irq_set_chip_data(irq, NULL);
  310. }
  311. static const struct irq_domain_ops stm32_adc_domain_ops = {
  312. .map = stm32_adc_domain_map,
  313. .unmap = stm32_adc_domain_unmap,
  314. .xlate = irq_domain_xlate_onecell,
  315. };
  316. static int stm32_adc_irq_probe(struct platform_device *pdev,
  317. struct stm32_adc_priv *priv)
  318. {
  319. struct device_node *np = pdev->dev.of_node;
  320. unsigned int i;
  321. /*
  322. * Interrupt(s) must be provided, depending on the compatible:
  323. * - stm32f4/h7 shares a common interrupt line.
  324. * - stm32mp1, has one line per ADC
  325. */
  326. for (i = 0; i < priv->cfg->num_irqs; i++) {
  327. priv->irq[i] = platform_get_irq(pdev, i);
  328. if (priv->irq[i] < 0)
  329. return priv->irq[i];
  330. }
  331. priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
  332. &stm32_adc_domain_ops,
  333. priv);
  334. if (!priv->domain) {
  335. dev_err(&pdev->dev, "Failed to add irq domain\n");
  336. return -ENOMEM;
  337. }
  338. for (i = 0; i < priv->cfg->num_irqs; i++) {
  339. irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
  340. irq_set_handler_data(priv->irq[i], priv);
  341. }
  342. return 0;
  343. }
  344. static void stm32_adc_irq_remove(struct platform_device *pdev,
  345. struct stm32_adc_priv *priv)
  346. {
  347. int hwirq;
  348. unsigned int i;
  349. for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
  350. irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
  351. irq_domain_remove(priv->domain);
  352. for (i = 0; i < priv->cfg->num_irqs; i++)
  353. irq_set_chained_handler(priv->irq[i], NULL);
  354. }
  355. static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
  356. struct device *dev)
  357. {
  358. int ret;
  359. /*
  360. * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
  361. * switches (via PCSEL) which have reduced performances when their
  362. * supply is below 2.7V (vdda by default):
  363. * - Voltage booster can be used, to get full ADC performances
  364. * (increases power consumption).
  365. * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
  366. *
  367. * Recommended settings for ANASWVDD and EN_BOOSTER:
  368. * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
  369. * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
  370. * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
  371. */
  372. if (priv->vdda_uv < 2700000) {
  373. if (priv->syscfg && priv->vdd_uv > 2700000) {
  374. ret = regulator_enable(priv->vdd);
  375. if (ret < 0) {
  376. dev_err(dev, "vdd enable failed %d\n", ret);
  377. return ret;
  378. }
  379. ret = regmap_write(priv->syscfg,
  380. STM32MP1_SYSCFG_PMCSETR,
  381. STM32MP1_SYSCFG_ANASWVDD_MASK);
  382. if (ret < 0) {
  383. regulator_disable(priv->vdd);
  384. dev_err(dev, "vdd select failed, %d\n", ret);
  385. return ret;
  386. }
  387. dev_dbg(dev, "analog switches supplied by vdd\n");
  388. return 0;
  389. }
  390. if (priv->booster) {
  391. /*
  392. * This is optional, as this is a trade-off between
  393. * analog performance and power consumption.
  394. */
  395. ret = regulator_enable(priv->booster);
  396. if (ret < 0) {
  397. dev_err(dev, "booster enable failed %d\n", ret);
  398. return ret;
  399. }
  400. dev_dbg(dev, "analog switches supplied by booster\n");
  401. return 0;
  402. }
  403. }
  404. /* Fallback using vdda (default), nothing to do */
  405. dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
  406. priv->vdda_uv);
  407. return 0;
  408. }
  409. static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
  410. {
  411. if (priv->vdda_uv < 2700000) {
  412. if (priv->syscfg && priv->vdd_uv > 2700000) {
  413. regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
  414. STM32MP1_SYSCFG_ANASWVDD_MASK);
  415. regulator_disable(priv->vdd);
  416. return;
  417. }
  418. if (priv->booster)
  419. regulator_disable(priv->booster);
  420. }
  421. }
  422. static int stm32_adc_core_hw_start(struct device *dev)
  423. {
  424. struct stm32_adc_common *common = dev_get_drvdata(dev);
  425. struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
  426. int ret;
  427. ret = regulator_enable(priv->vdda);
  428. if (ret < 0) {
  429. dev_err(dev, "vdda enable failed %d\n", ret);
  430. return ret;
  431. }
  432. ret = regulator_get_voltage(priv->vdda);
  433. if (ret < 0) {
  434. dev_err(dev, "vdda get voltage failed, %d\n", ret);
  435. goto err_vdda_disable;
  436. }
  437. priv->vdda_uv = ret;
  438. ret = stm32_adc_core_switches_supply_en(priv, dev);
  439. if (ret < 0)
  440. goto err_vdda_disable;
  441. ret = regulator_enable(priv->vref);
  442. if (ret < 0) {
  443. dev_err(dev, "vref enable failed\n");
  444. goto err_switches_dis;
  445. }
  446. if (priv->bclk) {
  447. ret = clk_prepare_enable(priv->bclk);
  448. if (ret < 0) {
  449. dev_err(dev, "bus clk enable failed\n");
  450. goto err_regulator_disable;
  451. }
  452. }
  453. if (priv->aclk) {
  454. ret = clk_prepare_enable(priv->aclk);
  455. if (ret < 0) {
  456. dev_err(dev, "adc clk enable failed\n");
  457. goto err_bclk_disable;
  458. }
  459. }
  460. writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
  461. return 0;
  462. err_bclk_disable:
  463. if (priv->bclk)
  464. clk_disable_unprepare(priv->bclk);
  465. err_regulator_disable:
  466. regulator_disable(priv->vref);
  467. err_switches_dis:
  468. stm32_adc_core_switches_supply_dis(priv);
  469. err_vdda_disable:
  470. regulator_disable(priv->vdda);
  471. return ret;
  472. }
  473. static void stm32_adc_core_hw_stop(struct device *dev)
  474. {
  475. struct stm32_adc_common *common = dev_get_drvdata(dev);
  476. struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
  477. /* Backup CCR that may be lost (depends on power state to achieve) */
  478. priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
  479. if (priv->aclk)
  480. clk_disable_unprepare(priv->aclk);
  481. if (priv->bclk)
  482. clk_disable_unprepare(priv->bclk);
  483. regulator_disable(priv->vref);
  484. stm32_adc_core_switches_supply_dis(priv);
  485. regulator_disable(priv->vdda);
  486. }
  487. static int stm32_adc_core_switches_probe(struct device *dev,
  488. struct stm32_adc_priv *priv)
  489. {
  490. struct device_node *np = dev->of_node;
  491. int ret;
  492. /* Analog switches supply can be controlled by syscfg (optional) */
  493. priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
  494. if (IS_ERR(priv->syscfg)) {
  495. ret = PTR_ERR(priv->syscfg);
  496. if (ret != -ENODEV)
  497. return dev_err_probe(dev, ret, "Can't probe syscfg\n");
  498. priv->syscfg = NULL;
  499. }
  500. /* Booster can be used to supply analog switches (optional) */
  501. if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
  502. of_property_read_bool(np, "booster-supply")) {
  503. priv->booster = devm_regulator_get_optional(dev, "booster");
  504. if (IS_ERR(priv->booster)) {
  505. ret = PTR_ERR(priv->booster);
  506. if (ret != -ENODEV)
  507. return dev_err_probe(dev, ret, "can't get booster\n");
  508. priv->booster = NULL;
  509. }
  510. }
  511. /* Vdd can be used to supply analog switches (optional) */
  512. if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
  513. of_property_read_bool(np, "vdd-supply")) {
  514. priv->vdd = devm_regulator_get_optional(dev, "vdd");
  515. if (IS_ERR(priv->vdd)) {
  516. ret = PTR_ERR(priv->vdd);
  517. if (ret != -ENODEV)
  518. return dev_err_probe(dev, ret, "can't get vdd\n");
  519. priv->vdd = NULL;
  520. }
  521. }
  522. if (priv->vdd) {
  523. ret = regulator_enable(priv->vdd);
  524. if (ret < 0) {
  525. dev_err(dev, "vdd enable failed %d\n", ret);
  526. return ret;
  527. }
  528. ret = regulator_get_voltage(priv->vdd);
  529. if (ret < 0) {
  530. dev_err(dev, "vdd get voltage failed %d\n", ret);
  531. regulator_disable(priv->vdd);
  532. return ret;
  533. }
  534. priv->vdd_uv = ret;
  535. regulator_disable(priv->vdd);
  536. }
  537. return 0;
  538. }
  539. static int stm32_adc_probe(struct platform_device *pdev)
  540. {
  541. struct stm32_adc_priv *priv;
  542. struct device *dev = &pdev->dev;
  543. struct device_node *np = pdev->dev.of_node;
  544. struct resource *res;
  545. u32 max_rate;
  546. int ret;
  547. if (!pdev->dev.of_node)
  548. return -ENODEV;
  549. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  550. if (!priv)
  551. return -ENOMEM;
  552. platform_set_drvdata(pdev, &priv->common);
  553. priv->cfg = (const struct stm32_adc_priv_cfg *)
  554. of_match_device(dev->driver->of_match_table, dev)->data;
  555. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  556. priv->common.base = devm_ioremap_resource(&pdev->dev, res);
  557. if (IS_ERR(priv->common.base))
  558. return PTR_ERR(priv->common.base);
  559. priv->common.phys_base = res->start;
  560. priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
  561. if (IS_ERR(priv->vdda))
  562. return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
  563. "vdda get failed\n");
  564. priv->vref = devm_regulator_get(&pdev->dev, "vref");
  565. if (IS_ERR(priv->vref))
  566. return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
  567. "vref get failed\n");
  568. priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
  569. if (IS_ERR(priv->aclk))
  570. return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
  571. "Can't get 'adc' clock\n");
  572. priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
  573. if (IS_ERR(priv->bclk))
  574. return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
  575. "Can't get 'bus' clock\n");
  576. ret = stm32_adc_core_switches_probe(dev, priv);
  577. if (ret)
  578. return ret;
  579. pm_runtime_get_noresume(dev);
  580. pm_runtime_set_active(dev);
  581. pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
  582. pm_runtime_use_autosuspend(dev);
  583. pm_runtime_enable(dev);
  584. ret = stm32_adc_core_hw_start(dev);
  585. if (ret)
  586. goto err_pm_stop;
  587. ret = regulator_get_voltage(priv->vref);
  588. if (ret < 0) {
  589. dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
  590. goto err_hw_stop;
  591. }
  592. priv->common.vref_mv = ret / 1000;
  593. dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
  594. ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
  595. &max_rate);
  596. if (!ret)
  597. priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
  598. else
  599. priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
  600. ret = priv->cfg->clk_sel(pdev, priv);
  601. if (ret < 0)
  602. goto err_hw_stop;
  603. ret = stm32_adc_irq_probe(pdev, priv);
  604. if (ret < 0)
  605. goto err_hw_stop;
  606. ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
  607. if (ret < 0) {
  608. dev_err(&pdev->dev, "failed to populate DT children\n");
  609. goto err_irq_remove;
  610. }
  611. pm_runtime_mark_last_busy(dev);
  612. pm_runtime_put_autosuspend(dev);
  613. return 0;
  614. err_irq_remove:
  615. stm32_adc_irq_remove(pdev, priv);
  616. err_hw_stop:
  617. stm32_adc_core_hw_stop(dev);
  618. err_pm_stop:
  619. pm_runtime_disable(dev);
  620. pm_runtime_set_suspended(dev);
  621. pm_runtime_put_noidle(dev);
  622. return ret;
  623. }
  624. static int stm32_adc_remove(struct platform_device *pdev)
  625. {
  626. struct stm32_adc_common *common = platform_get_drvdata(pdev);
  627. struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
  628. pm_runtime_get_sync(&pdev->dev);
  629. of_platform_depopulate(&pdev->dev);
  630. stm32_adc_irq_remove(pdev, priv);
  631. stm32_adc_core_hw_stop(&pdev->dev);
  632. pm_runtime_disable(&pdev->dev);
  633. pm_runtime_set_suspended(&pdev->dev);
  634. pm_runtime_put_noidle(&pdev->dev);
  635. return 0;
  636. }
  637. #if defined(CONFIG_PM)
  638. static int stm32_adc_core_runtime_suspend(struct device *dev)
  639. {
  640. stm32_adc_core_hw_stop(dev);
  641. return 0;
  642. }
  643. static int stm32_adc_core_runtime_resume(struct device *dev)
  644. {
  645. return stm32_adc_core_hw_start(dev);
  646. }
  647. static int stm32_adc_core_runtime_idle(struct device *dev)
  648. {
  649. pm_runtime_mark_last_busy(dev);
  650. return 0;
  651. }
  652. #endif
  653. static const struct dev_pm_ops stm32_adc_core_pm_ops = {
  654. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  655. pm_runtime_force_resume)
  656. SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
  657. stm32_adc_core_runtime_resume,
  658. stm32_adc_core_runtime_idle)
  659. };
  660. static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
  661. .regs = &stm32f4_adc_common_regs,
  662. .clk_sel = stm32f4_adc_clk_sel,
  663. .max_clk_rate_hz = 36000000,
  664. .num_irqs = 1,
  665. };
  666. static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
  667. .regs = &stm32h7_adc_common_regs,
  668. .clk_sel = stm32h7_adc_clk_sel,
  669. .max_clk_rate_hz = 36000000,
  670. .has_syscfg = HAS_VBOOSTER,
  671. .num_irqs = 1,
  672. };
  673. static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
  674. .regs = &stm32h7_adc_common_regs,
  675. .clk_sel = stm32h7_adc_clk_sel,
  676. .max_clk_rate_hz = 40000000,
  677. .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
  678. .num_irqs = 2,
  679. };
  680. static const struct of_device_id stm32_adc_of_match[] = {
  681. {
  682. .compatible = "st,stm32f4-adc-core",
  683. .data = (void *)&stm32f4_adc_priv_cfg
  684. }, {
  685. .compatible = "st,stm32h7-adc-core",
  686. .data = (void *)&stm32h7_adc_priv_cfg
  687. }, {
  688. .compatible = "st,stm32mp1-adc-core",
  689. .data = (void *)&stm32mp1_adc_priv_cfg
  690. }, {
  691. },
  692. };
  693. MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
  694. static struct platform_driver stm32_adc_driver = {
  695. .probe = stm32_adc_probe,
  696. .remove = stm32_adc_remove,
  697. .driver = {
  698. .name = "stm32-adc-core",
  699. .of_match_table = stm32_adc_of_match,
  700. .pm = &stm32_adc_core_pm_ops,
  701. },
  702. };
  703. module_platform_driver(stm32_adc_driver);
  704. MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
  705. MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
  706. MODULE_LICENSE("GPL v2");
  707. MODULE_ALIAS("platform:stm32-adc-core");