spear_adc.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ST SPEAr ADC driver
  4. *
  5. * Copyright 2012 Stefan Roese <sr@denx.de>
  6. */
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/device.h>
  11. #include <linux/kernel.h>
  12. #include <linux/slab.h>
  13. #include <linux/io.h>
  14. #include <linux/clk.h>
  15. #include <linux/err.h>
  16. #include <linux/completion.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/iio/iio.h>
  20. #include <linux/iio/sysfs.h>
  21. /* SPEAR registers definitions */
  22. #define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF)
  23. #define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF)
  24. #define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0)
  25. #define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4)
  26. /* Bit definitions for SPEAR_ADC_STATUS */
  27. #define SPEAR_ADC_STATUS_START_CONVERSION BIT(0)
  28. #define SPEAR_ADC_STATUS_CHANNEL_NUM(x) ((x) << 1)
  29. #define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4)
  30. #define SPEAR_ADC_STATUS_AVG_SAMPLE(x) ((x) << 5)
  31. #define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9)
  32. #define SPEAR_ADC_DATA_MASK 0x03ff
  33. #define SPEAR_ADC_DATA_BITS 10
  34. #define SPEAR_ADC_MOD_NAME "spear-adc"
  35. #define SPEAR_ADC_CHANNEL_NUM 8
  36. #define SPEAR_ADC_CLK_MIN 2500000
  37. #define SPEAR_ADC_CLK_MAX 20000000
  38. struct adc_regs_spear3xx {
  39. u32 status;
  40. u32 average;
  41. u32 scan_rate;
  42. u32 clk; /* Not avail for 1340 & 1310 */
  43. u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
  44. u32 ch_data[SPEAR_ADC_CHANNEL_NUM];
  45. };
  46. struct chan_data {
  47. u32 lsb;
  48. u32 msb;
  49. };
  50. struct adc_regs_spear6xx {
  51. u32 status;
  52. u32 pad[2];
  53. u32 clk;
  54. u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
  55. struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM];
  56. u32 scan_rate_lo;
  57. u32 scan_rate_hi;
  58. struct chan_data average;
  59. };
  60. struct spear_adc_state {
  61. struct device_node *np;
  62. struct adc_regs_spear3xx __iomem *adc_base_spear3xx;
  63. struct adc_regs_spear6xx __iomem *adc_base_spear6xx;
  64. struct clk *clk;
  65. struct completion completion;
  66. u32 current_clk;
  67. u32 sampling_freq;
  68. u32 avg_samples;
  69. u32 vref_external;
  70. u32 value;
  71. };
  72. /*
  73. * Functions to access some SPEAr ADC register. Abstracted into
  74. * static inline functions, because of different register offsets
  75. * on different SoC variants (SPEAr300 vs SPEAr600 etc).
  76. */
  77. static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
  78. {
  79. __raw_writel(val, &st->adc_base_spear6xx->status);
  80. }
  81. static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
  82. {
  83. u32 clk_high, clk_low, count;
  84. u32 apb_clk = clk_get_rate(st->clk);
  85. count = DIV_ROUND_UP(apb_clk, val);
  86. clk_low = count / 2;
  87. clk_high = count - clk_low;
  88. st->current_clk = apb_clk / count;
  89. __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
  90. &st->adc_base_spear6xx->clk);
  91. }
  92. static void spear_adc_set_ctrl(struct spear_adc_state *st, int n,
  93. u32 val)
  94. {
  95. __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
  96. }
  97. static u32 spear_adc_get_average(struct spear_adc_state *st)
  98. {
  99. if (of_device_is_compatible(st->np, "st,spear600-adc")) {
  100. return __raw_readl(&st->adc_base_spear6xx->average.msb) &
  101. SPEAR_ADC_DATA_MASK;
  102. } else {
  103. return __raw_readl(&st->adc_base_spear3xx->average) &
  104. SPEAR_ADC_DATA_MASK;
  105. }
  106. }
  107. static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate)
  108. {
  109. if (of_device_is_compatible(st->np, "st,spear600-adc")) {
  110. __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
  111. &st->adc_base_spear6xx->scan_rate_lo);
  112. __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
  113. &st->adc_base_spear6xx->scan_rate_hi);
  114. } else {
  115. __raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
  116. }
  117. }
  118. static int spear_adc_read_raw(struct iio_dev *indio_dev,
  119. struct iio_chan_spec const *chan,
  120. int *val,
  121. int *val2,
  122. long mask)
  123. {
  124. struct spear_adc_state *st = iio_priv(indio_dev);
  125. u32 status;
  126. switch (mask) {
  127. case IIO_CHAN_INFO_RAW:
  128. mutex_lock(&indio_dev->mlock);
  129. status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) |
  130. SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) |
  131. SPEAR_ADC_STATUS_START_CONVERSION |
  132. SPEAR_ADC_STATUS_ADC_ENABLE;
  133. if (st->vref_external == 0)
  134. status |= SPEAR_ADC_STATUS_VREF_INTERNAL;
  135. spear_adc_set_status(st, status);
  136. wait_for_completion(&st->completion); /* set by ISR */
  137. *val = st->value;
  138. mutex_unlock(&indio_dev->mlock);
  139. return IIO_VAL_INT;
  140. case IIO_CHAN_INFO_SCALE:
  141. *val = st->vref_external;
  142. *val2 = SPEAR_ADC_DATA_BITS;
  143. return IIO_VAL_FRACTIONAL_LOG2;
  144. case IIO_CHAN_INFO_SAMP_FREQ:
  145. *val = st->current_clk;
  146. return IIO_VAL_INT;
  147. }
  148. return -EINVAL;
  149. }
  150. static int spear_adc_write_raw(struct iio_dev *indio_dev,
  151. struct iio_chan_spec const *chan,
  152. int val,
  153. int val2,
  154. long mask)
  155. {
  156. struct spear_adc_state *st = iio_priv(indio_dev);
  157. int ret = 0;
  158. if (mask != IIO_CHAN_INFO_SAMP_FREQ)
  159. return -EINVAL;
  160. mutex_lock(&indio_dev->mlock);
  161. if ((val < SPEAR_ADC_CLK_MIN) ||
  162. (val > SPEAR_ADC_CLK_MAX) ||
  163. (val2 != 0)) {
  164. ret = -EINVAL;
  165. goto out;
  166. }
  167. spear_adc_set_clk(st, val);
  168. out:
  169. mutex_unlock(&indio_dev->mlock);
  170. return ret;
  171. }
  172. #define SPEAR_ADC_CHAN(idx) { \
  173. .type = IIO_VOLTAGE, \
  174. .indexed = 1, \
  175. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  176. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  177. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
  178. .channel = idx, \
  179. }
  180. static const struct iio_chan_spec spear_adc_iio_channels[] = {
  181. SPEAR_ADC_CHAN(0),
  182. SPEAR_ADC_CHAN(1),
  183. SPEAR_ADC_CHAN(2),
  184. SPEAR_ADC_CHAN(3),
  185. SPEAR_ADC_CHAN(4),
  186. SPEAR_ADC_CHAN(5),
  187. SPEAR_ADC_CHAN(6),
  188. SPEAR_ADC_CHAN(7),
  189. };
  190. static irqreturn_t spear_adc_isr(int irq, void *dev_id)
  191. {
  192. struct spear_adc_state *st = dev_id;
  193. /* Read value to clear IRQ */
  194. st->value = spear_adc_get_average(st);
  195. complete(&st->completion);
  196. return IRQ_HANDLED;
  197. }
  198. static int spear_adc_configure(struct spear_adc_state *st)
  199. {
  200. int i;
  201. /* Reset ADC core */
  202. spear_adc_set_status(st, 0);
  203. __raw_writel(0, &st->adc_base_spear6xx->clk);
  204. for (i = 0; i < 8; i++)
  205. spear_adc_set_ctrl(st, i, 0);
  206. spear_adc_set_scanrate(st, 0);
  207. spear_adc_set_clk(st, st->sampling_freq);
  208. return 0;
  209. }
  210. static const struct iio_info spear_adc_info = {
  211. .read_raw = &spear_adc_read_raw,
  212. .write_raw = &spear_adc_write_raw,
  213. };
  214. static int spear_adc_probe(struct platform_device *pdev)
  215. {
  216. struct device_node *np = pdev->dev.of_node;
  217. struct device *dev = &pdev->dev;
  218. struct spear_adc_state *st;
  219. struct iio_dev *indio_dev = NULL;
  220. int ret = -ENODEV;
  221. int irq;
  222. indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state));
  223. if (!indio_dev) {
  224. dev_err(dev, "failed allocating iio device\n");
  225. return -ENOMEM;
  226. }
  227. st = iio_priv(indio_dev);
  228. st->np = np;
  229. /*
  230. * SPEAr600 has a different register layout than other SPEAr SoC's
  231. * (e.g. SPEAr3xx). Let's provide two register base addresses
  232. * to support multi-arch kernels.
  233. */
  234. st->adc_base_spear6xx = devm_platform_ioremap_resource(pdev, 0);
  235. if (IS_ERR(st->adc_base_spear6xx))
  236. return PTR_ERR(st->adc_base_spear6xx);
  237. st->adc_base_spear3xx =
  238. (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
  239. st->clk = devm_clk_get(dev, NULL);
  240. if (IS_ERR(st->clk)) {
  241. dev_err(dev, "failed getting clock\n");
  242. return PTR_ERR(st->clk);
  243. }
  244. ret = clk_prepare_enable(st->clk);
  245. if (ret) {
  246. dev_err(dev, "failed enabling clock\n");
  247. return ret;
  248. }
  249. irq = platform_get_irq(pdev, 0);
  250. if (irq <= 0) {
  251. ret = -EINVAL;
  252. goto errout2;
  253. }
  254. ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
  255. st);
  256. if (ret < 0) {
  257. dev_err(dev, "failed requesting interrupt\n");
  258. goto errout2;
  259. }
  260. if (of_property_read_u32(np, "sampling-frequency",
  261. &st->sampling_freq)) {
  262. dev_err(dev, "sampling-frequency missing in DT\n");
  263. ret = -EINVAL;
  264. goto errout2;
  265. }
  266. /*
  267. * Optional avg_samples defaults to 0, resulting in single data
  268. * conversion
  269. */
  270. of_property_read_u32(np, "average-samples", &st->avg_samples);
  271. /*
  272. * Optional vref_external defaults to 0, resulting in internal vref
  273. * selection
  274. */
  275. of_property_read_u32(np, "vref-external", &st->vref_external);
  276. spear_adc_configure(st);
  277. platform_set_drvdata(pdev, indio_dev);
  278. init_completion(&st->completion);
  279. indio_dev->name = SPEAR_ADC_MOD_NAME;
  280. indio_dev->info = &spear_adc_info;
  281. indio_dev->modes = INDIO_DIRECT_MODE;
  282. indio_dev->channels = spear_adc_iio_channels;
  283. indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels);
  284. ret = iio_device_register(indio_dev);
  285. if (ret)
  286. goto errout2;
  287. dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
  288. return 0;
  289. errout2:
  290. clk_disable_unprepare(st->clk);
  291. return ret;
  292. }
  293. static int spear_adc_remove(struct platform_device *pdev)
  294. {
  295. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  296. struct spear_adc_state *st = iio_priv(indio_dev);
  297. iio_device_unregister(indio_dev);
  298. clk_disable_unprepare(st->clk);
  299. return 0;
  300. }
  301. #ifdef CONFIG_OF
  302. static const struct of_device_id spear_adc_dt_ids[] = {
  303. { .compatible = "st,spear600-adc", },
  304. { /* sentinel */ }
  305. };
  306. MODULE_DEVICE_TABLE(of, spear_adc_dt_ids);
  307. #endif
  308. static struct platform_driver spear_adc_driver = {
  309. .probe = spear_adc_probe,
  310. .remove = spear_adc_remove,
  311. .driver = {
  312. .name = SPEAR_ADC_MOD_NAME,
  313. .of_match_table = of_match_ptr(spear_adc_dt_ids),
  314. },
  315. };
  316. module_platform_driver(spear_adc_driver);
  317. MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
  318. MODULE_DESCRIPTION("SPEAr ADC driver");
  319. MODULE_LICENSE("GPL");