sc27xx_adc.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2018 Spreadtrum Communications Inc.
  3. #include <linux/hwspinlock.h>
  4. #include <linux/iio/iio.h>
  5. #include <linux/module.h>
  6. #include <linux/nvmem-consumer.h>
  7. #include <linux/of.h>
  8. #include <linux/of_device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regmap.h>
  11. #include <linux/slab.h>
  12. /* PMIC global registers definition */
  13. #define SC27XX_MODULE_EN 0xc08
  14. #define SC27XX_MODULE_ADC_EN BIT(5)
  15. #define SC27XX_ARM_CLK_EN 0xc10
  16. #define SC27XX_CLK_ADC_EN BIT(5)
  17. #define SC27XX_CLK_ADC_CLK_EN BIT(6)
  18. /* ADC controller registers definition */
  19. #define SC27XX_ADC_CTL 0x0
  20. #define SC27XX_ADC_CH_CFG 0x4
  21. #define SC27XX_ADC_DATA 0x4c
  22. #define SC27XX_ADC_INT_EN 0x50
  23. #define SC27XX_ADC_INT_CLR 0x54
  24. #define SC27XX_ADC_INT_STS 0x58
  25. #define SC27XX_ADC_INT_RAW 0x5c
  26. /* Bits and mask definition for SC27XX_ADC_CTL register */
  27. #define SC27XX_ADC_EN BIT(0)
  28. #define SC27XX_ADC_CHN_RUN BIT(1)
  29. #define SC27XX_ADC_12BIT_MODE BIT(2)
  30. #define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4)
  31. #define SC27XX_ADC_RUN_NUM_SHIFT 4
  32. /* Bits and mask definition for SC27XX_ADC_CH_CFG register */
  33. #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0)
  34. #define SC27XX_ADC_SCALE_MASK GENMASK(10, 8)
  35. #define SC27XX_ADC_SCALE_SHIFT 8
  36. /* Bits definitions for SC27XX_ADC_INT_EN registers */
  37. #define SC27XX_ADC_IRQ_EN BIT(0)
  38. /* Bits definitions for SC27XX_ADC_INT_CLR registers */
  39. #define SC27XX_ADC_IRQ_CLR BIT(0)
  40. /* Bits definitions for SC27XX_ADC_INT_RAW registers */
  41. #define SC27XX_ADC_IRQ_RAW BIT(0)
  42. /* Mask definition for SC27XX_ADC_DATA register */
  43. #define SC27XX_ADC_DATA_MASK GENMASK(11, 0)
  44. /* Timeout (ms) for the trylock of hardware spinlocks */
  45. #define SC27XX_ADC_HWLOCK_TIMEOUT 5000
  46. /* Timeout (us) for ADC data conversion according to ADC datasheet */
  47. #define SC27XX_ADC_RDY_TIMEOUT 1000000
  48. #define SC27XX_ADC_POLL_RAW_STATUS 500
  49. /* Maximum ADC channel number */
  50. #define SC27XX_ADC_CHANNEL_MAX 32
  51. /* ADC voltage ratio definition */
  52. #define SC27XX_VOLT_RATIO(n, d) \
  53. (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d))
  54. #define SC27XX_RATIO_NUMERATOR_OFFSET 16
  55. #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0)
  56. struct sc27xx_adc_data {
  57. struct device *dev;
  58. struct regmap *regmap;
  59. /*
  60. * One hardware spinlock to synchronize between the multiple
  61. * subsystems which will access the unique ADC controller.
  62. */
  63. struct hwspinlock *hwlock;
  64. int channel_scale[SC27XX_ADC_CHANNEL_MAX];
  65. u32 base;
  66. int irq;
  67. };
  68. struct sc27xx_adc_linear_graph {
  69. int volt0;
  70. int adc0;
  71. int volt1;
  72. int adc1;
  73. };
  74. /*
  75. * According to the datasheet, we can convert one ADC value to one voltage value
  76. * through 2 points in the linear graph. If the voltage is less than 1.2v, we
  77. * should use the small-scale graph, and if more than 1.2v, we should use the
  78. * big-scale graph.
  79. */
  80. static struct sc27xx_adc_linear_graph big_scale_graph = {
  81. 4200, 3310,
  82. 3600, 2832,
  83. };
  84. static struct sc27xx_adc_linear_graph small_scale_graph = {
  85. 1000, 3413,
  86. 100, 341,
  87. };
  88. static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
  89. 4200, 856,
  90. 3600, 733,
  91. };
  92. static const struct sc27xx_adc_linear_graph small_scale_graph_calib = {
  93. 1000, 833,
  94. 100, 80,
  95. };
  96. static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
  97. {
  98. return ((calib_data & 0xff) + calib_adc - 128) * 4;
  99. }
  100. static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
  101. bool big_scale)
  102. {
  103. const struct sc27xx_adc_linear_graph *calib_graph;
  104. struct sc27xx_adc_linear_graph *graph;
  105. struct nvmem_cell *cell;
  106. const char *cell_name;
  107. u32 calib_data = 0;
  108. void *buf;
  109. size_t len;
  110. if (big_scale) {
  111. calib_graph = &big_scale_graph_calib;
  112. graph = &big_scale_graph;
  113. cell_name = "big_scale_calib";
  114. } else {
  115. calib_graph = &small_scale_graph_calib;
  116. graph = &small_scale_graph;
  117. cell_name = "small_scale_calib";
  118. }
  119. cell = nvmem_cell_get(data->dev, cell_name);
  120. if (IS_ERR(cell))
  121. return PTR_ERR(cell);
  122. buf = nvmem_cell_read(cell, &len);
  123. nvmem_cell_put(cell);
  124. if (IS_ERR(buf))
  125. return PTR_ERR(buf);
  126. memcpy(&calib_data, buf, min(len, sizeof(u32)));
  127. /* Only need to calibrate the adc values in the linear graph. */
  128. graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
  129. graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
  130. calib_graph->adc1);
  131. kfree(buf);
  132. return 0;
  133. }
  134. static int sc27xx_adc_get_ratio(int channel, int scale)
  135. {
  136. switch (channel) {
  137. case 1:
  138. case 2:
  139. case 3:
  140. case 4:
  141. return scale ? SC27XX_VOLT_RATIO(400, 1025) :
  142. SC27XX_VOLT_RATIO(1, 1);
  143. case 5:
  144. return SC27XX_VOLT_RATIO(7, 29);
  145. case 6:
  146. return SC27XX_VOLT_RATIO(375, 9000);
  147. case 7:
  148. case 8:
  149. return scale ? SC27XX_VOLT_RATIO(100, 125) :
  150. SC27XX_VOLT_RATIO(1, 1);
  151. case 19:
  152. return SC27XX_VOLT_RATIO(1, 3);
  153. default:
  154. return SC27XX_VOLT_RATIO(1, 1);
  155. }
  156. return SC27XX_VOLT_RATIO(1, 1);
  157. }
  158. static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel,
  159. int scale, int *val)
  160. {
  161. int ret;
  162. u32 tmp, value, status;
  163. ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT);
  164. if (ret) {
  165. dev_err(data->dev, "timeout to get the hwspinlock\n");
  166. return ret;
  167. }
  168. ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
  169. SC27XX_ADC_EN, SC27XX_ADC_EN);
  170. if (ret)
  171. goto unlock_adc;
  172. ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
  173. SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
  174. if (ret)
  175. goto disable_adc;
  176. /* Configure the channel id and scale */
  177. tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK;
  178. tmp |= channel & SC27XX_ADC_CHN_ID_MASK;
  179. ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG,
  180. SC27XX_ADC_CHN_ID_MASK | SC27XX_ADC_SCALE_MASK,
  181. tmp);
  182. if (ret)
  183. goto disable_adc;
  184. /* Select 12bit conversion mode, and only sample 1 time */
  185. tmp = SC27XX_ADC_12BIT_MODE;
  186. tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK;
  187. ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
  188. SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE,
  189. tmp);
  190. if (ret)
  191. goto disable_adc;
  192. ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
  193. SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN);
  194. if (ret)
  195. goto disable_adc;
  196. ret = regmap_read_poll_timeout(data->regmap,
  197. data->base + SC27XX_ADC_INT_RAW,
  198. status, (status & SC27XX_ADC_IRQ_RAW),
  199. SC27XX_ADC_POLL_RAW_STATUS,
  200. SC27XX_ADC_RDY_TIMEOUT);
  201. if (ret) {
  202. dev_err(data->dev, "read adc timeout, status = 0x%x\n", status);
  203. goto disable_adc;
  204. }
  205. ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value);
  206. if (ret)
  207. goto disable_adc;
  208. value &= SC27XX_ADC_DATA_MASK;
  209. disable_adc:
  210. regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
  211. SC27XX_ADC_EN, 0);
  212. unlock_adc:
  213. hwspin_unlock_raw(data->hwlock);
  214. if (!ret)
  215. *val = value;
  216. return ret;
  217. }
  218. static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data,
  219. int channel, int scale,
  220. u32 *div_numerator, u32 *div_denominator)
  221. {
  222. u32 ratio = sc27xx_adc_get_ratio(channel, scale);
  223. *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET;
  224. *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
  225. }
  226. static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
  227. int raw_adc)
  228. {
  229. int tmp;
  230. tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1);
  231. tmp /= (graph->adc0 - graph->adc1);
  232. tmp += graph->volt1;
  233. return tmp < 0 ? 0 : tmp;
  234. }
  235. static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel,
  236. int scale, int raw_adc)
  237. {
  238. u32 numerator, denominator;
  239. u32 volt;
  240. /*
  241. * Convert ADC values to voltage values according to the linear graph,
  242. * and channel 5 and channel 1 has been calibrated, so we can just
  243. * return the voltage values calculated by the linear graph. But other
  244. * channels need be calculated to the real voltage values with the
  245. * voltage ratio.
  246. */
  247. switch (channel) {
  248. case 5:
  249. return sc27xx_adc_to_volt(&big_scale_graph, raw_adc);
  250. case 1:
  251. return sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
  252. default:
  253. volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
  254. break;
  255. }
  256. sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator);
  257. return (volt * denominator + numerator / 2) / numerator;
  258. }
  259. static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data,
  260. int channel, int scale, int *val)
  261. {
  262. int ret, raw_adc;
  263. ret = sc27xx_adc_read(data, channel, scale, &raw_adc);
  264. if (ret)
  265. return ret;
  266. *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc);
  267. return 0;
  268. }
  269. static int sc27xx_adc_read_raw(struct iio_dev *indio_dev,
  270. struct iio_chan_spec const *chan,
  271. int *val, int *val2, long mask)
  272. {
  273. struct sc27xx_adc_data *data = iio_priv(indio_dev);
  274. int scale = data->channel_scale[chan->channel];
  275. int ret, tmp;
  276. switch (mask) {
  277. case IIO_CHAN_INFO_RAW:
  278. mutex_lock(&indio_dev->mlock);
  279. ret = sc27xx_adc_read(data, chan->channel, scale, &tmp);
  280. mutex_unlock(&indio_dev->mlock);
  281. if (ret)
  282. return ret;
  283. *val = tmp;
  284. return IIO_VAL_INT;
  285. case IIO_CHAN_INFO_PROCESSED:
  286. mutex_lock(&indio_dev->mlock);
  287. ret = sc27xx_adc_read_processed(data, chan->channel, scale,
  288. &tmp);
  289. mutex_unlock(&indio_dev->mlock);
  290. if (ret)
  291. return ret;
  292. *val = tmp;
  293. return IIO_VAL_INT;
  294. case IIO_CHAN_INFO_SCALE:
  295. *val = scale;
  296. return IIO_VAL_INT;
  297. default:
  298. return -EINVAL;
  299. }
  300. }
  301. static int sc27xx_adc_write_raw(struct iio_dev *indio_dev,
  302. struct iio_chan_spec const *chan,
  303. int val, int val2, long mask)
  304. {
  305. struct sc27xx_adc_data *data = iio_priv(indio_dev);
  306. switch (mask) {
  307. case IIO_CHAN_INFO_SCALE:
  308. data->channel_scale[chan->channel] = val;
  309. return IIO_VAL_INT;
  310. default:
  311. return -EINVAL;
  312. }
  313. }
  314. static const struct iio_info sc27xx_info = {
  315. .read_raw = &sc27xx_adc_read_raw,
  316. .write_raw = &sc27xx_adc_write_raw,
  317. };
  318. #define SC27XX_ADC_CHANNEL(index, mask) { \
  319. .type = IIO_VOLTAGE, \
  320. .channel = index, \
  321. .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \
  322. .datasheet_name = "CH##index", \
  323. .indexed = 1, \
  324. }
  325. static const struct iio_chan_spec sc27xx_channels[] = {
  326. SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
  327. SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
  328. SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
  329. SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
  330. SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
  331. SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
  332. SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
  333. SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
  334. SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
  335. SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
  336. SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
  337. SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
  338. SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
  339. SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
  340. SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
  341. SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
  342. SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
  343. SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
  344. SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
  345. SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
  346. SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
  347. SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
  348. SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
  349. SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
  350. SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
  351. SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
  352. SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
  353. SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
  354. SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
  355. SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
  356. SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
  357. SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)),
  358. };
  359. static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
  360. {
  361. int ret;
  362. ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
  363. SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN);
  364. if (ret)
  365. return ret;
  366. /* Enable ADC work clock and controller clock */
  367. ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
  368. SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN,
  369. SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
  370. if (ret)
  371. goto disable_adc;
  372. /* ADC channel scales' calibration from nvmem device */
  373. ret = sc27xx_adc_scale_calibration(data, true);
  374. if (ret)
  375. goto disable_clk;
  376. ret = sc27xx_adc_scale_calibration(data, false);
  377. if (ret)
  378. goto disable_clk;
  379. return 0;
  380. disable_clk:
  381. regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
  382. SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
  383. disable_adc:
  384. regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
  385. SC27XX_MODULE_ADC_EN, 0);
  386. return ret;
  387. }
  388. static void sc27xx_adc_disable(void *_data)
  389. {
  390. struct sc27xx_adc_data *data = _data;
  391. /* Disable ADC work clock and controller clock */
  392. regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
  393. SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
  394. regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
  395. SC27XX_MODULE_ADC_EN, 0);
  396. }
  397. static int sc27xx_adc_probe(struct platform_device *pdev)
  398. {
  399. struct device *dev = &pdev->dev;
  400. struct device_node *np = dev->of_node;
  401. struct sc27xx_adc_data *sc27xx_data;
  402. struct iio_dev *indio_dev;
  403. int ret;
  404. indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data));
  405. if (!indio_dev)
  406. return -ENOMEM;
  407. sc27xx_data = iio_priv(indio_dev);
  408. sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL);
  409. if (!sc27xx_data->regmap) {
  410. dev_err(dev, "failed to get ADC regmap\n");
  411. return -ENODEV;
  412. }
  413. ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
  414. if (ret) {
  415. dev_err(dev, "failed to get ADC base address\n");
  416. return ret;
  417. }
  418. sc27xx_data->irq = platform_get_irq(pdev, 0);
  419. if (sc27xx_data->irq < 0)
  420. return sc27xx_data->irq;
  421. ret = of_hwspin_lock_get_id(np, 0);
  422. if (ret < 0) {
  423. dev_err(dev, "failed to get hwspinlock id\n");
  424. return ret;
  425. }
  426. sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
  427. if (!sc27xx_data->hwlock) {
  428. dev_err(dev, "failed to request hwspinlock\n");
  429. return -ENXIO;
  430. }
  431. sc27xx_data->dev = dev;
  432. ret = sc27xx_adc_enable(sc27xx_data);
  433. if (ret) {
  434. dev_err(dev, "failed to enable ADC module\n");
  435. return ret;
  436. }
  437. ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data);
  438. if (ret) {
  439. dev_err(dev, "failed to add ADC disable action\n");
  440. return ret;
  441. }
  442. indio_dev->name = dev_name(dev);
  443. indio_dev->modes = INDIO_DIRECT_MODE;
  444. indio_dev->info = &sc27xx_info;
  445. indio_dev->channels = sc27xx_channels;
  446. indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels);
  447. ret = devm_iio_device_register(dev, indio_dev);
  448. if (ret)
  449. dev_err(dev, "could not register iio (ADC)");
  450. return ret;
  451. }
  452. static const struct of_device_id sc27xx_adc_of_match[] = {
  453. { .compatible = "sprd,sc2731-adc", },
  454. { }
  455. };
  456. static struct platform_driver sc27xx_adc_driver = {
  457. .probe = sc27xx_adc_probe,
  458. .driver = {
  459. .name = "sc27xx-adc",
  460. .of_match_table = sc27xx_adc_of_match,
  461. },
  462. };
  463. module_platform_driver(sc27xx_adc_driver);
  464. MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
  465. MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");
  466. MODULE_LICENSE("GPL v2");