rockchip_saradc.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Rockchip Successive Approximation Register (SAR) A/D Converter
  4. * Copyright (C) 2014 ROCKCHIP, Inc.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/clk.h>
  13. #include <linux/completion.h>
  14. #include <linux/delay.h>
  15. #include <linux/reset.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/iio/buffer.h>
  18. #include <linux/iio/iio.h>
  19. #include <linux/iio/trigger_consumer.h>
  20. #include <linux/iio/triggered_buffer.h>
  21. #define SARADC_DATA 0x00
  22. #define SARADC_STAS 0x04
  23. #define SARADC_STAS_BUSY BIT(0)
  24. #define SARADC_CTRL 0x08
  25. #define SARADC_CTRL_IRQ_STATUS BIT(6)
  26. #define SARADC_CTRL_IRQ_ENABLE BIT(5)
  27. #define SARADC_CTRL_POWER_CTRL BIT(3)
  28. #define SARADC_CTRL_CHN_MASK 0x7
  29. #define SARADC_DLY_PU_SOC 0x0c
  30. #define SARADC_DLY_PU_SOC_MASK 0x3f
  31. #define SARADC_TIMEOUT msecs_to_jiffies(100)
  32. #define SARADC_MAX_CHANNELS 6
  33. struct rockchip_saradc_data {
  34. const struct iio_chan_spec *channels;
  35. int num_channels;
  36. unsigned long clk_rate;
  37. };
  38. struct rockchip_saradc {
  39. void __iomem *regs;
  40. struct clk *pclk;
  41. struct clk *clk;
  42. struct completion completion;
  43. struct regulator *vref;
  44. struct reset_control *reset;
  45. const struct rockchip_saradc_data *data;
  46. u16 last_val;
  47. const struct iio_chan_spec *last_chan;
  48. };
  49. static void rockchip_saradc_power_down(struct rockchip_saradc *info)
  50. {
  51. /* Clear irq & power down adc */
  52. writel_relaxed(0, info->regs + SARADC_CTRL);
  53. }
  54. static int rockchip_saradc_conversion(struct rockchip_saradc *info,
  55. struct iio_chan_spec const *chan)
  56. {
  57. reinit_completion(&info->completion);
  58. /* 8 clock periods as delay between power up and start cmd */
  59. writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
  60. info->last_chan = chan;
  61. /* Select the channel to be used and trigger conversion */
  62. writel(SARADC_CTRL_POWER_CTRL
  63. | (chan->channel & SARADC_CTRL_CHN_MASK)
  64. | SARADC_CTRL_IRQ_ENABLE,
  65. info->regs + SARADC_CTRL);
  66. if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
  67. return -ETIMEDOUT;
  68. return 0;
  69. }
  70. static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
  71. struct iio_chan_spec const *chan,
  72. int *val, int *val2, long mask)
  73. {
  74. struct rockchip_saradc *info = iio_priv(indio_dev);
  75. int ret;
  76. switch (mask) {
  77. case IIO_CHAN_INFO_RAW:
  78. mutex_lock(&indio_dev->mlock);
  79. ret = rockchip_saradc_conversion(info, chan);
  80. if (ret) {
  81. rockchip_saradc_power_down(info);
  82. mutex_unlock(&indio_dev->mlock);
  83. return ret;
  84. }
  85. *val = info->last_val;
  86. mutex_unlock(&indio_dev->mlock);
  87. return IIO_VAL_INT;
  88. case IIO_CHAN_INFO_SCALE:
  89. ret = regulator_get_voltage(info->vref);
  90. if (ret < 0) {
  91. dev_err(&indio_dev->dev, "failed to get voltage\n");
  92. return ret;
  93. }
  94. *val = ret / 1000;
  95. *val2 = chan->scan_type.realbits;
  96. return IIO_VAL_FRACTIONAL_LOG2;
  97. default:
  98. return -EINVAL;
  99. }
  100. }
  101. static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
  102. {
  103. struct rockchip_saradc *info = dev_id;
  104. /* Read value */
  105. info->last_val = readl_relaxed(info->regs + SARADC_DATA);
  106. info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
  107. rockchip_saradc_power_down(info);
  108. complete(&info->completion);
  109. return IRQ_HANDLED;
  110. }
  111. static const struct iio_info rockchip_saradc_iio_info = {
  112. .read_raw = rockchip_saradc_read_raw,
  113. };
  114. #define SARADC_CHANNEL(_index, _id, _res) { \
  115. .type = IIO_VOLTAGE, \
  116. .indexed = 1, \
  117. .channel = _index, \
  118. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  119. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  120. .datasheet_name = _id, \
  121. .scan_index = _index, \
  122. .scan_type = { \
  123. .sign = 'u', \
  124. .realbits = _res, \
  125. .storagebits = 16, \
  126. .endianness = IIO_CPU, \
  127. }, \
  128. }
  129. static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
  130. SARADC_CHANNEL(0, "adc0", 10),
  131. SARADC_CHANNEL(1, "adc1", 10),
  132. SARADC_CHANNEL(2, "adc2", 10),
  133. };
  134. static const struct rockchip_saradc_data saradc_data = {
  135. .channels = rockchip_saradc_iio_channels,
  136. .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
  137. .clk_rate = 1000000,
  138. };
  139. static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
  140. SARADC_CHANNEL(0, "adc0", 12),
  141. SARADC_CHANNEL(1, "adc1", 12),
  142. };
  143. static const struct rockchip_saradc_data rk3066_tsadc_data = {
  144. .channels = rockchip_rk3066_tsadc_iio_channels,
  145. .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
  146. .clk_rate = 50000,
  147. };
  148. static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
  149. SARADC_CHANNEL(0, "adc0", 10),
  150. SARADC_CHANNEL(1, "adc1", 10),
  151. SARADC_CHANNEL(2, "adc2", 10),
  152. SARADC_CHANNEL(3, "adc3", 10),
  153. SARADC_CHANNEL(4, "adc4", 10),
  154. SARADC_CHANNEL(5, "adc5", 10),
  155. };
  156. static const struct rockchip_saradc_data rk3399_saradc_data = {
  157. .channels = rockchip_rk3399_saradc_iio_channels,
  158. .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
  159. .clk_rate = 1000000,
  160. };
  161. static const struct of_device_id rockchip_saradc_match[] = {
  162. {
  163. .compatible = "rockchip,saradc",
  164. .data = &saradc_data,
  165. }, {
  166. .compatible = "rockchip,rk3066-tsadc",
  167. .data = &rk3066_tsadc_data,
  168. }, {
  169. .compatible = "rockchip,rk3399-saradc",
  170. .data = &rk3399_saradc_data,
  171. },
  172. {},
  173. };
  174. MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
  175. /*
  176. * Reset SARADC Controller.
  177. */
  178. static void rockchip_saradc_reset_controller(struct reset_control *reset)
  179. {
  180. reset_control_assert(reset);
  181. usleep_range(10, 20);
  182. reset_control_deassert(reset);
  183. }
  184. static void rockchip_saradc_clk_disable(void *data)
  185. {
  186. struct rockchip_saradc *info = data;
  187. clk_disable_unprepare(info->clk);
  188. }
  189. static void rockchip_saradc_pclk_disable(void *data)
  190. {
  191. struct rockchip_saradc *info = data;
  192. clk_disable_unprepare(info->pclk);
  193. }
  194. static void rockchip_saradc_regulator_disable(void *data)
  195. {
  196. struct rockchip_saradc *info = data;
  197. regulator_disable(info->vref);
  198. }
  199. static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
  200. {
  201. struct iio_poll_func *pf = p;
  202. struct iio_dev *i_dev = pf->indio_dev;
  203. struct rockchip_saradc *info = iio_priv(i_dev);
  204. /*
  205. * @values: each channel takes an u16 value
  206. * @timestamp: will be 8-byte aligned automatically
  207. */
  208. struct {
  209. u16 values[SARADC_MAX_CHANNELS];
  210. int64_t timestamp;
  211. } data;
  212. int ret;
  213. int i, j = 0;
  214. mutex_lock(&i_dev->mlock);
  215. for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
  216. const struct iio_chan_spec *chan = &i_dev->channels[i];
  217. ret = rockchip_saradc_conversion(info, chan);
  218. if (ret) {
  219. rockchip_saradc_power_down(info);
  220. goto out;
  221. }
  222. data.values[j] = info->last_val;
  223. j++;
  224. }
  225. iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
  226. out:
  227. mutex_unlock(&i_dev->mlock);
  228. iio_trigger_notify_done(i_dev->trig);
  229. return IRQ_HANDLED;
  230. }
  231. static int rockchip_saradc_probe(struct platform_device *pdev)
  232. {
  233. struct rockchip_saradc *info = NULL;
  234. struct device_node *np = pdev->dev.of_node;
  235. struct iio_dev *indio_dev = NULL;
  236. struct resource *mem;
  237. const struct of_device_id *match;
  238. int ret;
  239. int irq;
  240. if (!np)
  241. return -ENODEV;
  242. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
  243. if (!indio_dev) {
  244. dev_err(&pdev->dev, "failed allocating iio device\n");
  245. return -ENOMEM;
  246. }
  247. info = iio_priv(indio_dev);
  248. match = of_match_device(rockchip_saradc_match, &pdev->dev);
  249. if (!match) {
  250. dev_err(&pdev->dev, "failed to match device\n");
  251. return -ENODEV;
  252. }
  253. info->data = match->data;
  254. /* Sanity check for possible later IP variants with more channels */
  255. if (info->data->num_channels > SARADC_MAX_CHANNELS) {
  256. dev_err(&pdev->dev, "max channels exceeded");
  257. return -EINVAL;
  258. }
  259. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  260. info->regs = devm_ioremap_resource(&pdev->dev, mem);
  261. if (IS_ERR(info->regs))
  262. return PTR_ERR(info->regs);
  263. /*
  264. * The reset should be an optional property, as it should work
  265. * with old devicetrees as well
  266. */
  267. info->reset = devm_reset_control_get_exclusive(&pdev->dev,
  268. "saradc-apb");
  269. if (IS_ERR(info->reset)) {
  270. ret = PTR_ERR(info->reset);
  271. if (ret != -ENOENT)
  272. return ret;
  273. dev_dbg(&pdev->dev, "no reset control found\n");
  274. info->reset = NULL;
  275. }
  276. init_completion(&info->completion);
  277. irq = platform_get_irq(pdev, 0);
  278. if (irq < 0)
  279. return irq;
  280. ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
  281. 0, dev_name(&pdev->dev), info);
  282. if (ret < 0) {
  283. dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
  284. return ret;
  285. }
  286. info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
  287. if (IS_ERR(info->pclk)) {
  288. dev_err(&pdev->dev, "failed to get pclk\n");
  289. return PTR_ERR(info->pclk);
  290. }
  291. info->clk = devm_clk_get(&pdev->dev, "saradc");
  292. if (IS_ERR(info->clk)) {
  293. dev_err(&pdev->dev, "failed to get adc clock\n");
  294. return PTR_ERR(info->clk);
  295. }
  296. info->vref = devm_regulator_get(&pdev->dev, "vref");
  297. if (IS_ERR(info->vref)) {
  298. dev_err(&pdev->dev, "failed to get regulator, %ld\n",
  299. PTR_ERR(info->vref));
  300. return PTR_ERR(info->vref);
  301. }
  302. if (info->reset)
  303. rockchip_saradc_reset_controller(info->reset);
  304. /*
  305. * Use a default value for the converter clock.
  306. * This may become user-configurable in the future.
  307. */
  308. ret = clk_set_rate(info->clk, info->data->clk_rate);
  309. if (ret < 0) {
  310. dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
  311. return ret;
  312. }
  313. ret = regulator_enable(info->vref);
  314. if (ret < 0) {
  315. dev_err(&pdev->dev, "failed to enable vref regulator\n");
  316. return ret;
  317. }
  318. ret = devm_add_action_or_reset(&pdev->dev,
  319. rockchip_saradc_regulator_disable, info);
  320. if (ret) {
  321. dev_err(&pdev->dev, "failed to register devm action, %d\n",
  322. ret);
  323. return ret;
  324. }
  325. ret = clk_prepare_enable(info->pclk);
  326. if (ret < 0) {
  327. dev_err(&pdev->dev, "failed to enable pclk\n");
  328. return ret;
  329. }
  330. ret = devm_add_action_or_reset(&pdev->dev,
  331. rockchip_saradc_pclk_disable, info);
  332. if (ret) {
  333. dev_err(&pdev->dev, "failed to register devm action, %d\n",
  334. ret);
  335. return ret;
  336. }
  337. ret = clk_prepare_enable(info->clk);
  338. if (ret < 0) {
  339. dev_err(&pdev->dev, "failed to enable converter clock\n");
  340. return ret;
  341. }
  342. ret = devm_add_action_or_reset(&pdev->dev,
  343. rockchip_saradc_clk_disable, info);
  344. if (ret) {
  345. dev_err(&pdev->dev, "failed to register devm action, %d\n",
  346. ret);
  347. return ret;
  348. }
  349. platform_set_drvdata(pdev, indio_dev);
  350. indio_dev->name = dev_name(&pdev->dev);
  351. indio_dev->info = &rockchip_saradc_iio_info;
  352. indio_dev->modes = INDIO_DIRECT_MODE;
  353. indio_dev->channels = info->data->channels;
  354. indio_dev->num_channels = info->data->num_channels;
  355. ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
  356. rockchip_saradc_trigger_handler,
  357. NULL);
  358. if (ret)
  359. return ret;
  360. return devm_iio_device_register(&pdev->dev, indio_dev);
  361. }
  362. #ifdef CONFIG_PM_SLEEP
  363. static int rockchip_saradc_suspend(struct device *dev)
  364. {
  365. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  366. struct rockchip_saradc *info = iio_priv(indio_dev);
  367. clk_disable_unprepare(info->clk);
  368. clk_disable_unprepare(info->pclk);
  369. regulator_disable(info->vref);
  370. return 0;
  371. }
  372. static int rockchip_saradc_resume(struct device *dev)
  373. {
  374. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  375. struct rockchip_saradc *info = iio_priv(indio_dev);
  376. int ret;
  377. ret = regulator_enable(info->vref);
  378. if (ret)
  379. return ret;
  380. ret = clk_prepare_enable(info->pclk);
  381. if (ret)
  382. return ret;
  383. ret = clk_prepare_enable(info->clk);
  384. if (ret)
  385. clk_disable_unprepare(info->pclk);
  386. return ret;
  387. }
  388. #endif
  389. static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
  390. rockchip_saradc_suspend, rockchip_saradc_resume);
  391. static struct platform_driver rockchip_saradc_driver = {
  392. .probe = rockchip_saradc_probe,
  393. .driver = {
  394. .name = "rockchip-saradc",
  395. .of_match_table = rockchip_saradc_match,
  396. .pm = &rockchip_saradc_pm_ops,
  397. },
  398. };
  399. module_platform_driver(rockchip_saradc_driver);
  400. MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
  401. MODULE_DESCRIPTION("Rockchip SARADC driver");
  402. MODULE_LICENSE("GPL v2");